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x1000: Correct SFC TMODE bit definitions

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We were using a definition of 0b100 for "Quad Input / Quad Output" mode
which is marked as "reserved" in the X1000 TRM.  The correct value is
0b101.

Somehow this "worked" for some devices but failed for others?

Credit for this discovery+fix goes to forum user ZappBranigan2972

Change-Id: Iedbd2d1b6da55113e266ad8aa51fc9c3130bf2b8
This commit is contained in:
Solomon Peachy 2026-02-02 08:11:07 -05:00
parent 78778d6e6f
commit 9f216921b8
1 changed files with 4 additions and 3 deletions
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7
firmware/target/mips/ingenic_x1000/sfc-x1000.h
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@ -36,9 +36,10 @@
#define SFC_TMODE_1_1_2 1
#define SFC_TMODE_1_2_2 2
#define SFC_TMODE_2_2_2 3
#define SFC_TMODE_1_1_4 4
#define SFC_TMODE_1_4_4 5
#define SFC_TMODE_4_4_4 6
#define SFC_TMODE_RESERVED 4 // See 10.7.3.6 SFC Transfer Configure Register MODE Field
#define SFC_TMODE_1_1_4 5
#define SFC_TMODE_1_4_4 6
#define SFC_TMODE_4_4_4 7
/* Phase format
* _____________________