len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2026-07-10 13:29:52 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

stm32h7: update linker scripts for ELF boot

Browse source 
Use flash & AXI SRAM for the bootloader, ITCM/DTCM and
SDRAM for Rockbox. Hardly the most optimal use of SRAMs
but it's good enough to get started.

Fixes the Echo R1 app build, which wasn't fitting in
AXI SRAM.

Change-Id: I4f7e5f618d27b553e5ff8dec1d5c4c61ac9d8eb0
This commit is contained in:
Aidan MacDonald 2026-01-22 13:42:05 +00:00 • committed by Solomon Peachy
parent 174b33cc07
commit 98990df08f
2 changed files with 39 additions and 64 deletions
Download patch file Download diff file Expand all files Collapse all files

78
firmware/target/arm/stm32/app.lds
View file

@ -1,67 +1,25 @@
#include "cpu.h"
/*
* TODO: this is temporary and has not been tested
*/
ENTRY(main)
ENTRY(crt0_start)
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
STARTUP(target/arm/stm32/crt0-stm32h7.o)
MEMORY
{
SRAM_AXI (rwx) : ORIGIN = STM32_SRAM_AXI_BASE, LENGTH = STM32_SRAM_AXI_SIZE
DTCM (rwx) : ORIGIN = STM32_DTCM_BASE, LENGTH = STM32_DTCM_SIZE
ITCM (rwx) : ORIGIN = STM32_ITCM_BASE, LENGTH = STM32_ITCM_SIZE
SDRAM (rwx) : ORIGIN = STM32_SDRAM1_BASE, LENGTH = MEMORYSIZE * 1024 * 1024
}
/*
* to control section alignment (only affects on-disk alignment):
* -Wl,-z,max-page-size=0x1
*/
PHDRS
{
sram_rx PT_LOAD ;
sram_ro PT_LOAD ;
sram_rw PT_LOAD ;
itcm PT_LOAD ;
dtcm PT_LOAD ;
sdram_rx PT_LOAD ;
sdram_rw PT_LOAD ;
DTCM (rw) : ORIGIN = STM32_DTCM_BASE, LENGTH = STM32_DTCM_SIZE
ITCM (rx) : ORIGIN = STM32_ITCM_BASE, LENGTH = STM32_ITCM_SIZE
SDRAM (rwx) : ORIGIN = STM32_SDRAM1_BASE, LENGTH = MEMORYSIZE * 1024 * 1024
}
SECTIONS
{
.text :
{
loadaddress = .; /* only needed to keep ROLO happy */
*(.init*)
*(.text*)
} > SRAM_AXI :sram_rx
.rodata :
{
*(.rodata*)
} > SRAM_AXI :sram_ro
.data :
{
_databegin = .;
*(.data*)
_dataend = .;
} > SRAM_AXI :sram_rw
_datacopy = LOADADDR(.data);
.itext :
{
KEEP(*(.vectors.arm))
KEEP(*(.vectors.platform))
KEEP(*(.vectors.arm));
KEEP(*(.vectors.platform));
*(.icode*);
} > ITCM :itcm
} > ITCM
.stack (NOLOAD) :
{
@ -72,9 +30,25 @@ SECTIONS
stackbegin = .;
. += 0x2000;
stackend = .;
} > DTCM
*(.stack);
} > DTCM :dtcm
.text :
{
loadaddress = .; /* only needed to keep ROLO happy */
*(.init*);
*(.text*);
} > SDRAM
.rodata :
{
*(.rodata*);
} > SDRAM
.data :
{
*(.data*);
} > SDRAM
.bss (NOLOAD) :
{
@ -82,7 +56,7 @@ SECTIONS
*(.bss*);
*(COMMON);
_bssend = .;
} > SDRAM :sdram_rw
} > SDRAM
audiobuffer = ALIGN(32);
audiobufend = ORIGIN(SDRAM) + LENGTH(SDRAM) - CODEC_SIZE - PLUGIN_BUFFER_SIZE;

25
firmware/target/arm/stm32/boot.lds
View file

@ -7,26 +7,29 @@ STARTUP(target/arm/stm32/crt0-stm32h7.o)
MEMORY
{
SRAM_AXI (rwx) : ORIGIN = STM32_SRAM_AXI_BASE, LENGTH = STM32_SRAM_AXI_SIZE
DTCM (rwx) : ORIGIN = STM32_DTCM_BASE, LENGTH = STM32_DTCM_SIZE
FLASH1 (rx) : ORIGIN = STM32_FLASH_BANK1_BASE, LENGTH = STM32_FLASH_BANK1_SIZE
SRAM_AXI (rw) : ORIGIN = STM32_SRAM_AXI_BASE, LENGTH = STM32_SRAM_AXI_SIZE
FLASH1 (rx) : ORIGIN = STM32_FLASH_BANK1_BASE, LENGTH = STM32_FLASH_BANK1_SIZE
}
SECTIONS
{
.text :
{
KEEP(*(.vectors.arm))
KEEP(*(.vectors.platform))
*(.init*)
*(.text*)
*(.rodata*)
KEEP(*(.vectors.arm));
KEEP(*(.vectors.platform));
*(.init*);
*(.text*);
} > FLASH1
.rodata :
{
*(.rodata*);
} > FLASH1
.data :
{
_databegin = .;
*(.data*)
*(.data*);
_dataend = .;
} > SRAM_AXI AT> FLASH1
_datacopy = LOADADDR(.data);
@ -48,9 +51,7 @@ SECTIONS
stackbegin = .;
. += 0x2000;
stackend = .;
*(.stack);
} > DTCM
} > SRAM_AXI
}
EXTERN(__vectors_arm);