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HD200 - Setup codec as I2S master and enable recording
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27250 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcin Bukat
parent
15d0ac0134
commit
971a6e9c94
5 changed files with 138 additions and 79 deletions
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@ -42,6 +42,14 @@ const struct sound_settings_info audiohw_settings[] = {
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[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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[SOUND_DEPTH_3D] = {"", 0, 1, 0, 15, 0},
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#endif
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#ifdef HAVE_RECORDING
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[SOUND_LEFT_GAIN] = {"dB", 1, 1,-172, 300, 0},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1,-172, 300, 0},
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[SOUND_MIC_GAIN] = {"dB", 1, 1,-172, 300, 0},
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#endif
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};
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/* Flags used in combination with settings */
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@ -110,7 +118,7 @@ static int recvol2hw(int value)
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/* 010111 == 0dB (0x17) */
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/* 000000 == -17.25dB */
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return (3*(value/10 - 0x17))/4;
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return ((4*(value))/30 + 0x17);
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}
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#endif
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static void audiohw_mute(bool mute)
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@ -167,6 +175,14 @@ void audiohw_postinit(void)
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/* 4. Enable line and / or headphone output buffers as required. */
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#if defined(MROBE_100) || defined(MPIO_HD200)
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/* fix for high pitch noise after power-up on HD200
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* it is *NOT* required step according to the
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* Datasheet for WM8750L but real life is different :-)
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*/
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wmcodec_write(LOUT1, LOUT1_BITS);
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wmcodec_write(ROUT1, ROUT1_BITS);
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/* power-up output stage */
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wmcodec_write(PWRMGMT2, PWRMGMT2_DACL | PWRMGMT2_DACR |
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PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1);
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#else
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@ -196,16 +212,6 @@ void audiohw_postinit(void)
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#endif
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#endif
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#ifdef MPIO_HD200
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/* Crude fix for high pitch noise at startup
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* I should find out what realy causes this
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*/
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wmcodec_write(LOUT1, LOUT1_BITS|0x7f);
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wmcodec_write(ROUT1, ROUT1_BITS|0x7f);
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wmcodec_write(LOUT1, LOUT1_BITS);
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wmcodec_write(ROUT1, ROUT1_BITS);
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#endif
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/* lower power consumption */
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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@ -276,10 +282,12 @@ void audiohw_close(void)
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wmcodec_write(PWRMGMT1, 0x0);
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}
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/* According to datasheet of WM8750
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* clocking setup is needed in both slave and master mode
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*/
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void audiohw_set_frequency(int fsel)
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{
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(void)fsel;
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#ifndef CODEC_SLAVE
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static const unsigned char srctrl_table[HW_NUM_FREQ] =
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{
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HW_HAVE_11_([HW_FREQ_11] = CODEC_SRCTRL_11025HZ,)
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@ -292,10 +300,23 @@ void audiohw_set_frequency(int fsel)
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fsel = HW_FREQ_DEFAULT;
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wmcodec_write(CLOCKING, srctrl_table[fsel]);
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#endif
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}
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#if defined(HAVE_WM8750)
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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/* Set the depth of the 3D effect */
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void audiohw_set_depth_3d(int val)
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{
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if (val)
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wmcodec_write(ENHANCE_3D,
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ENHANCE_3D_MODE3D_PLAYBACK | ENHANCE_3D_DEPTH(val) |
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ENHANCE_3D_3DEN);
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else
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wmcodec_write(ENHANCE_3D,ENHANCE_3D_MODE3D_PLAYBACK);
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}
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#endif
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#ifdef HAVE_RECORDING
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void audiohw_set_recsrc(int source, bool recording)
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{
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/* INPUT1 - FM radio
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@ -307,17 +328,30 @@ void audiohw_set_recsrc(int source, bool recording)
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* turn on output buffer(s)
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*
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* if recording == true we route input signal to PGA
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* and monitoring picks up signal after PGA in analog domain
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* and monitoring picks up signal after PGA and ADC
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* turn on ADC, PGA, DAC, output buffer(s)
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*/
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switch(source)
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{
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case AUDIO_SRC_PLAYBACK:
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/* mute PGA, disable all audio paths but DAC and output stage*/
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wmcodec_write(LINVOL, LINVOL_LINMUTE | LINVOL_LINVOL(23)); /* 0dB */
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wmcodec_write(RINVOL, RINVOL_RINMUTE | RINVOL_RINVOL(23)); /* 0dB */
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/* turn off DAC and ADC in order to setup Enchance 3D function
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* for playback. This does not turn on enchancement but
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* the switch between playback/record has to be done with
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* DAC and ADC off
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*/
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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wmcodec_write(PWRMGMT2, 0x00);
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wmcodec_write(ENHANCE_3D, ENHANCE_3D_MODE3D_PLAYBACK);
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#endif
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/* mute PGA, disable all audio paths but DAC and output stage*/
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wmcodec_write(LINVOL, LINVOL_LINMUTE | LINVOL_LINVOL(0x17)); /* 0dB */
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wmcodec_write(RINVOL, RINVOL_RINMUTE | RINVOL_RINVOL(0x17)); /* 0dB */
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wmcodec_write(LOUT1, LOUT1_BITS);
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wmcodec_write(ROUT1, ROUT1_BITS);
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wmcodec_write(PWRMGMT2, PWRMGMT2_DACL | PWRMGMT2_DACR |
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PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1);
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@ -332,15 +366,26 @@ void audiohw_set_recsrc(int source, bool recording)
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case AUDIO_SRC_FMRADIO:
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if(recording)
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{
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/* Set input volume to PGA */
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wmcodec_write(LINVOL, LINVOL_LINVOL(23));
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wmcodec_write(RINVOL, RINVOL_RINVOL(23));
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/* turn off DAC and ADC in order to setup Enchance 3D function
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* for playback. This does not turn on enchancement but
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* the switch between playback/record has to be done with
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* DAC and ADC off
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*/
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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wmcodec_write(PWRMGMT2, 0x00);
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wmcodec_write(ENHANCE_3D, ENHANCE_3D_MODE3D_RECORD);
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#endif
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/* Turn on PGA and ADC */
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K |
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PWRMGMT1_AINL | PWRMGMT1_AINR |
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PWRMGMT1_ADCL | PWRMGMT1_ADCR);
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/* Set input volume to PGA 0dB*/
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wmcodec_write(LINVOL, LINVOL_LIVU|LINVOL_LINVOL(0x17));
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wmcodec_write(RINVOL, RINVOL_RIVU|RINVOL_RINVOL(0x17));
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/* Setup input source for PGA as INPUT1
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* MICBOOST disabled
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*/
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@ -356,18 +401,18 @@ void audiohw_set_recsrc(int source, bool recording)
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wmcodec_write(PWRMGMT2, PWRMGMT2_DACL | PWRMGMT2_DACR |
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PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1);
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/* analog monitor */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LMIXSEL_ADCLIN |
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LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RMIXSEL_ADCRIN |
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RIGHTMIX2_RD2RO);
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/* route DAC signal to output mixer */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RD2RO);
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}
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else
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{
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/* turn off ADC, PGA */
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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wmcodec_write(LOUT1, LOUT1_BITS);
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wmcodec_write(ROUT1, ROUT1_BITS);
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/* turn on DAC and output stage */
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wmcodec_write(PWRMGMT2, PWRMGMT2_DACL | PWRMGMT2_DACR |
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PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1);
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@ -377,17 +422,24 @@ void audiohw_set_recsrc(int source, bool recording)
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*/
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wmcodec_write(LEFTMIX1, LEFTMIX1_LI2LO | LEFTMIX1_LMIXSEL_LINPUT1 |
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LEFTMIX1_LI2LOVOL(0x20) | LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RI2RO | RIGHTMIX2_RMIXSEL_RINPUT1 |
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wmcodec_write(RIGHTMIX1, RIGHTMIX1_RMIXSEL_RINPUT1);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RI2RO |
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RIGHTMIX2_RI2ROVOL(0x20) | RIGHTMIX2_RD2RO);
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}
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break;
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case AUDIO_SRC_LINEIN:
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/* Set input volume to PGA */
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wmcodec_write(LINVOL, LINVOL_LINVOL(23));
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wmcodec_write(RINVOL, RINVOL_RINVOL(23));
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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wmcodec_write(PWRMGMT2, 0x00);
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wmcodec_write(ENHANCE_3D, ENHANCE_3D_MODE3D_RECORD);
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#endif
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/* Turn on PGA, ADC, DAC */
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/* Set input volume to PGA */
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wmcodec_write(LINVOL, LINVOL_LIVU | LINVOL_LINVOL(23));
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wmcodec_write(RINVOL, RINVOL_RIVU | RINVOL_RINVOL(23));
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/* Turn on PGA, ADC */
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K |
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PWRMGMT1_AINL | PWRMGMT1_AINR |
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PWRMGMT1_ADCL | PWRMGMT1_ADCR);
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@ -406,18 +458,21 @@ void audiohw_set_recsrc(int source, bool recording)
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* default is LADC -> LDATA, RADC -> RDATA
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* so we don't touch this
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*/
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/* digital monitor */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LMIXSEL_ADCLIN |
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LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RMIXSEL_ADCRIN |
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RIGHTMIX2_RD2RO);
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/* route DAC signal to output mixer */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RD2RO);
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break;
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case AUDIO_SRC_MIC:
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#ifdef AUDIOHW_HAVE_DEPTH_3D
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K);
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wmcodec_write(PWRMGMT2, 0x00);
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wmcodec_write(ENHANCE_3D, ENHANCE_3D_MODE3D_RECORD);
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#endif
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/* Set input volume to PGA */
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wmcodec_write(LINVOL, LINVOL_LINVOL(23));
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wmcodec_write(RINVOL, RINVOL_RINVOL(23));
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wmcodec_write(LINVOL, LINVOL_LIVU | LINVOL_LINVOL(23));
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wmcodec_write(RINVOL, RINVOL_RIVU | RINVOL_RINVOL(23));
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/* Turn on PGA and ADC, turn off DAC */
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wmcodec_write(PWRMGMT1, PWRMGMT1_VREF | PWRMGMT1_VMIDSEL_50K |
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@ -439,21 +494,19 @@ void audiohw_set_recsrc(int source, bool recording)
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* so we don't touch this
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*/
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/* analog monitor */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LMIXSEL_ADCLIN |
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LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RMIXSEL_ADCRIN |
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RIGHTMIX2_RD2RO);
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break;
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/* route DAC signal to output mixer */
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wmcodec_write(LEFTMIX1, LEFTMIX1_LD2LO);
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wmcodec_write(RIGHTMIX2, RIGHTMIX2_RD2RO);
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} /* switch(source) */
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}
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/* Setup PGA gain */
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void audiohw_set_recvol(int left, int right, int type)
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void audiohw_set_recvol(int vol_l, int vol_r, int type)
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{
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(void)type;
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wmcodec_write(LINVOL, LINVOL_LINVOL(recvol2hw(left)));
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wmcodec_write(RINVOL, RINVOL_RINVOL(recvol2hw(right)));
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wmcodec_write(LINVOL, LINVOL_LIZC|LINVOL_LINVOL(recvol2hw(vol_l)));
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wmcodec_write(RINVOL, RINVOL_RIZC|RINVOL_RIVU|RINVOL_RINVOL(recvol2hw(vol_r)));
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}
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#endif
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#endif /* HAVE_RECORDING */
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#endif /* HAVE_WM8750 */
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@ -14,26 +14,18 @@
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#define ATA_SWAP_WORDS
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/* define this if you have recording possibility */
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/* not implemented yet
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* #define HAVE_RECORDING
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*/
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#define HAVE_RECORDING
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/* Define bitmask of input sources - recordable bitmask can be defined
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* explicitly if different
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* not implemented yet
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*/
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#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO)
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/* define the bitmask of hardware sample rates */
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#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
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/* define the bitmask of recording sample rates
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* not implemented yet
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*#define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
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*/
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/* define the bitmask of recording sample rates */
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#define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
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/* define this if you have a bitmap LCD display */
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#define HAVE_LCD_BITMAP
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@ -114,9 +106,17 @@
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#define CONFIG_TUNER_XTAL 32768
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/* we have WM8750 codec in I2S slave mode */
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/* we have WM8750 codec in I2S master mode */
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#define HAVE_WM8750
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#define CODEC_SLAVE
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/* clocking setup based on 11.2896 MHz master clock
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* provided to the codec by MCU
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* WM8750L Datasheet Table 40, page 46
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*/
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#define CODEC_SRCTRL_11025HZ (0x18 << 1)
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#define CODEC_SRCTRL_22050HZ (0x1A << 1)
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#define CODEC_SRCTRL_44100HZ (0x10 << 1)
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#define CODEC_SRCTRL_88200HZ (0x1E << 1)
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#define BATTERY_CAPACITY_DEFAULT 950 /* default battery capacity */
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#define BATTERY_CAPACITY_MIN 950 /* min. capacity selectable */
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@ -142,12 +142,6 @@
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/* Define this if you want to use coldfire's i2c interface */
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#define CONFIG_I2C I2C_COLDFIRE
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/* OF resets device instead of poweroff while charging
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* this triggers bootloader code which takes care of charging.
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* I have feeling that powering off while charging may cause
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* partition table corruption I am experiencing from time to time
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*/
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/* define this if the hardware can be powered off while charging */
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/* #define HAVE_POWEROFF_WHILE_CHARGING */
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@ -25,13 +25,19 @@
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#define VOLUME_MIN -730
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#define VOLUME_MAX 60
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/* turn off 3D Enchance feature of WM8750 for now
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#if defined(HAVE_WM8750)
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#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP | DEPTH_3D_CAP)
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#else
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*/
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#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP | PRESCALER_CAP)
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/* #endif */
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extern int tenthdb2master(int db);
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extern void audiohw_set_master_vol(int vol_l, int vol_r);
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extern void audiohw_set_lineout_vol(int vol_l, int vol_r);
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#if defined(HAVE_WM8750)
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#if defined(HAVE_WM8750) && defined(HAVE_RECORDING)
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void audiohw_set_recsrc(int source, bool recording);
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#endif
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@ -222,7 +228,7 @@ void audiohw_set_recsrc(int source, bool recording);
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#define ADCL_LMICBOOST_13DB (1 << 4)
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#define ADCL_LMICBOOST_20DB (2 << 4)
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#define ADCL_LMICBOOST_29DB (3 << 4)
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#define ADCL_LMICBOOST(x) ((x) & (0x3 << 7))
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#define ADCL_LMICBOOST(x) (((x) & 0x3) << 4))
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#define ADCL_LINSEL_LINPUT1 (0 << 6)
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#define ADCL_LINSEL_LINPUT2 (1 << 6)
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#define ADCL_LINSEL_LINPUT3 (2 << 6)
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@ -46,6 +46,7 @@ void audio_set_output_source(int source)
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if ((unsigned)source >= AUDIO_NUM_SOURCES)
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source = AUDIO_SRC_PLAYBACK;
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/* route incoming audio samples to DAC */
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IIS2CONFIG = (IIS2CONFIG & ~(7 << 8)) | (txsrc_select[source+1] << 8);
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restore_irq(level);
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@ -89,10 +90,10 @@ void audio_input_mux(int source, unsigned flags)
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last_recording = recording;
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audiohw_set_recsrc(source,recording);
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/* Int. when 6 samples in FIFO, PDIR2 src = iis1RcvData */
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coldfire_set_dataincontrol(recording ?
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((3 << 14) | (4 << 3)) : 0);
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audiohw_set_recsrc(source, recording);
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break;
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}
|
||||
|
||||
|
|
|
|||
|
|
@ -84,13 +84,18 @@ static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
|
|||
#endif
|
||||
|
||||
#if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750)
|
||||
/* We run codec in master mode.
|
||||
* Codec can reconstruct all frequencies
|
||||
* from single 11.2896 MHz master clock
|
||||
*/
|
||||
static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
|
||||
{
|
||||
[HW_FREQ_88] = { 0x0c, 0x01 },
|
||||
[HW_FREQ_44] = { 0x06, 0x01 },
|
||||
[HW_FREQ_22] = { 0x04, 0x01 },
|
||||
[HW_FREQ_11] = { 0x02, 0x01 },
|
||||
[HW_FREQ_88] = { 0x00, 0x01 },
|
||||
[HW_FREQ_44] = { 0x00, 0x01 },
|
||||
[HW_FREQ_22] = { 0x00, 0x01 },
|
||||
[HW_FREQ_11] = { 0x00, 0x01 },
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue