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Rework ATA driver to get rid of lots of target-specific constants and allow for non-memory-mapped task file registers.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28950 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann 2011-01-02 22:51:47 +00:00
parent 0ce42df073
commit 9339be1279
11 changed files with 117 additions and 331 deletions
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196
firmware/drivers/ata.c
View file

@ -19,6 +19,7 @@
* *
****************************************************************************/ ****************************************************************************/
#include <stdbool.h> #include <stdbool.h>
#include <inttypes.h>
#include "ata.h" #include "ata.h"
#include "kernel.h" #include "kernel.h"
#include "thread.h" #include "thread.h"
@ -34,7 +35,37 @@
#include "ata-target.h" #include "ata-target.h"
#include "storage.h" #include "storage.h"
#define SECTOR_SIZE (512)
#ifndef ATA_OUT8
#define ATA_OUT8(reg, data) (reg) = (data)
#endif
#ifndef ATA_OUT16
#define ATA_OUT16(reg, data) (reg) = (data)
#endif
#ifndef ATA_IN8
#define ATA_IN8(reg) (reg)
#endif
#ifndef ATA_IN16
#define ATA_IN16(reg) (reg)
#endif
#ifndef ATA_SWAP_IDENTIFY
#define ATA_SWAP_IDENTIFY(word) (word)
#endif
#define SECTOR_SIZE 512
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define STATUS_DF 0x20
#define ERROR_IDNF 0x10
#define ERROR_ABRT 0x04
#define TEST_PATTERN1 0xa5
#define TEST_PATTERN2 0x5a
#define TEST_PATTERN3 0xaa
#define TEST_PATTERN4 0x55
#define ATA_FEATURE ATA_ERROR #define ATA_FEATURE ATA_ERROR
@ -210,7 +241,7 @@ STATICIRAM ICODE_ATTR int wait_for_bsy(void)
do do
{ {
if (!(ATA_STATUS & STATUS_BSY)) if (!(ATA_IN8(ATA_STATUS) & STATUS_BSY))
return 1; return 1;
last_disk_activity = current_tick; last_disk_activity = current_tick;
yield(); yield();
@ -230,7 +261,7 @@ STATICIRAM ICODE_ATTR int wait_for_rdy(void)
do do
{ {
if (ATA_ALT_STATUS & STATUS_RDY) if (ATA_IN8(ATA_ALT_STATUS) & STATUS_RDY)
return 1; return 1;
last_disk_activity = current_tick; last_disk_activity = current_tick;
yield(); yield();
@ -244,14 +275,14 @@ STATICIRAM ICODE_ATTR int wait_for_start_of_transfer(void)
if (!wait_for_bsy()) if (!wait_for_bsy())
return 0; return 0;
return (ATA_ALT_STATUS & (STATUS_BSY|STATUS_DRQ)) == STATUS_DRQ; return (ATA_IN8(ATA_ALT_STATUS) & (STATUS_BSY|STATUS_DRQ)) == STATUS_DRQ;
} }
STATICIRAM ICODE_ATTR int wait_for_end_of_transfer(void) STATICIRAM ICODE_ATTR int wait_for_end_of_transfer(void)
{ {
if (!wait_for_bsy()) if (!wait_for_bsy())
return 0; return 0;
return (ATA_ALT_STATUS & return (ATA_IN8(ATA_ALT_STATUS) &
(STATUS_BSY|STATUS_RDY|STATUS_DF|STATUS_DRQ|STATUS_ERR)) (STATUS_BSY|STATUS_RDY|STATUS_DF|STATUS_DRQ|STATUS_ERR))
== STATUS_RDY; == STATUS_RDY;
} }
@ -279,8 +310,8 @@ STATICIRAM ICODE_ATTR void copy_read_sectors(unsigned char* buf, int wordcount)
unsigned char* bufend = buf + wordcount*2; unsigned char* bufend = buf + wordcount*2;
do do
{ {
tmp = ATA_DATA; tmp = ATA_IN16(ATA_DATA);
#if defined(ATA_SWAP_WORDS) || defined(ROCKBOX_LITTLE_ENDIAN) #if defined(ROCKBOX_LITTLE_ENDIAN)
*buf++ = tmp & 0xff; /* I assume big endian */ *buf++ = tmp & 0xff; /* I assume big endian */
*buf++ = tmp >> 8; /* and don't use the SWAB16 macro */ *buf++ = tmp >> 8; /* and don't use the SWAB16 macro */
#else #else
@ -295,11 +326,7 @@ STATICIRAM ICODE_ATTR void copy_read_sectors(unsigned char* buf, int wordcount)
unsigned short* wbufend = wbuf + wordcount; unsigned short* wbufend = wbuf + wordcount;
do do
{ {
#ifdef ATA_SWAP_WORDS *wbuf = ATA_IN16(ATA_DATA);
*wbuf = swap16(ATA_DATA);
#else
*wbuf = ATA_DATA;
#endif
} while (++wbuf < wbufend); /* tail loop is faster */ } while (++wbuf < wbufend); /* tail loop is faster */
} }
} }
@ -315,15 +342,14 @@ STATICIRAM ICODE_ATTR void copy_write_sectors(const unsigned char* buf,
const unsigned char* bufend = buf + wordcount*2; const unsigned char* bufend = buf + wordcount*2;
do do
{ {
#if defined(ATA_SWAP_WORDS) || defined(ROCKBOX_LITTLE_ENDIAN) #if defined(ROCKBOX_LITTLE_ENDIAN)
tmp = (unsigned short) *buf++; tmp = (unsigned short) *buf++;
tmp |= (unsigned short) *buf++ << 8; tmp |= (unsigned short) *buf++ << 8;
SET_16BITREG(ATA_DATA, tmp);
#else #else
tmp = (unsigned short) *buf++ << 8; tmp = (unsigned short) *buf++ << 8;
tmp |= (unsigned short) *buf++; tmp |= (unsigned short) *buf++;
SET_16BITREG(ATA_DATA, tmp);
#endif #endif
ATA_OUT16(ATA_DATA, tmp);
} while (buf < bufend); /* tail loop is faster */ } while (buf < bufend); /* tail loop is faster */
} }
else else
@ -332,11 +358,7 @@ STATICIRAM ICODE_ATTR void copy_write_sectors(const unsigned char* buf,
unsigned short* wbufend = wbuf + wordcount; unsigned short* wbufend = wbuf + wordcount;
do do
{ {
#ifdef ATA_SWAP_WORDS ATA_OUT16(ATA_DATA, *wbuf);
SET_16BITREG(ATA_DATA, swap16(*wbuf));
#else
SET_16BITREG(ATA_DATA, *wbuf);
#endif
} while (++wbuf < wbufend); /* tail loop is faster */ } while (++wbuf < wbufend); /* tail loop is faster */
} }
} }
@ -389,7 +411,7 @@ static int ata_transfer_sectors(unsigned long start,
timeout = current_tick + READWRITE_TIMEOUT; timeout = current_tick + READWRITE_TIMEOUT;
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if (!wait_for_rdy()) if (!wait_for_rdy())
{ {
ret = -3; ret = -3;
@ -412,39 +434,39 @@ static int ata_transfer_sectors(unsigned long start,
#ifdef HAVE_LBA48 #ifdef HAVE_LBA48
if (lba48) if (lba48)
{ {
SET_REG(ATA_NSECTOR, count >> 8); ATA_OUT8(ATA_NSECTOR, count >> 8);
SET_REG(ATA_NSECTOR, count & 0xff); ATA_OUT8(ATA_NSECTOR, count & 0xff);
SET_REG(ATA_SECTOR, (start >> 24) & 0xff); /* 31:24 */ ATA_OUT8(ATA_SECTOR, (start >> 24) & 0xff); /* 31:24 */
SET_REG(ATA_SECTOR, start & 0xff); /* 7:0 */ ATA_OUT8(ATA_SECTOR, start & 0xff); /* 7:0 */
SET_REG(ATA_LCYL, 0); /* 39:32 */ ATA_OUT8(ATA_LCYL, 0); /* 39:32 */
SET_REG(ATA_LCYL, (start >> 8) & 0xff); /* 15:8 */ ATA_OUT8(ATA_LCYL, (start >> 8) & 0xff); /* 15:8 */
SET_REG(ATA_HCYL, 0); /* 47:40 */ ATA_OUT8(ATA_HCYL, 0); /* 47:40 */
SET_REG(ATA_HCYL, (start >> 16) & 0xff); /* 23:16 */ ATA_OUT8(ATA_HCYL, (start >> 16) & 0xff); /* 23:16 */
SET_REG(ATA_SELECT, SELECT_LBA | ata_device); ATA_OUT8(ATA_SELECT, SELECT_LBA | ata_device);
#ifdef HAVE_ATA_DMA #ifdef HAVE_ATA_DMA
if (write) if (write)
SET_REG(ATA_COMMAND, usedma ? CMD_WRITE_DMA_EXT : CMD_WRITE_MULTIPLE_EXT); ATA_OUT8(ATA_COMMAND, usedma ? CMD_WRITE_DMA_EXT : CMD_WRITE_MULTIPLE_EXT);
else else
SET_REG(ATA_COMMAND, usedma ? CMD_READ_DMA_EXT : CMD_READ_MULTIPLE_EXT); ATA_OUT8(ATA_COMMAND, usedma ? CMD_READ_DMA_EXT : CMD_READ_MULTIPLE_EXT);
#else #else
SET_REG(ATA_COMMAND, write ? CMD_WRITE_MULTIPLE_EXT : CMD_READ_MULTIPLE_EXT); ATA_OUT8(ATA_COMMAND, write ? CMD_WRITE_MULTIPLE_EXT : CMD_READ_MULTIPLE_EXT);
#endif #endif
} }
else else
#endif #endif
{ {
SET_REG(ATA_NSECTOR, count & 0xff); /* 0 means 256 sectors */ ATA_OUT8(ATA_NSECTOR, count & 0xff); /* 0 means 256 sectors */
SET_REG(ATA_SECTOR, start & 0xff); ATA_OUT8(ATA_SECTOR, start & 0xff);
SET_REG(ATA_LCYL, (start >> 8) & 0xff); ATA_OUT8(ATA_LCYL, (start >> 8) & 0xff);
SET_REG(ATA_HCYL, (start >> 16) & 0xff); ATA_OUT8(ATA_HCYL, (start >> 16) & 0xff);
SET_REG(ATA_SELECT, ((start >> 24) & 0xf) | SELECT_LBA | ata_device); ATA_OUT8(ATA_SELECT, ((start >> 24) & 0xf) | SELECT_LBA | ata_device);
#ifdef HAVE_ATA_DMA #ifdef HAVE_ATA_DMA
if (write) if (write)
SET_REG(ATA_COMMAND, usedma ? CMD_WRITE_DMA : CMD_WRITE_MULTIPLE); ATA_OUT8(ATA_COMMAND, usedma ? CMD_WRITE_DMA : CMD_WRITE_MULTIPLE);
else else
SET_REG(ATA_COMMAND, usedma ? CMD_READ_DMA : CMD_READ_MULTIPLE); ATA_OUT8(ATA_COMMAND, usedma ? CMD_READ_DMA : CMD_READ_MULTIPLE);
#else #else
SET_REG(ATA_COMMAND, write ? CMD_WRITE_MULTIPLE : CMD_READ_MULTIPLE); ATA_OUT8(ATA_COMMAND, write ? CMD_WRITE_MULTIPLE : CMD_READ_MULTIPLE);
#endif #endif
} }
@ -501,10 +523,10 @@ static int ata_transfer_sectors(unsigned long start,
} }
/* read the status register exactly once per loop */ /* read the status register exactly once per loop */
status = ATA_STATUS; status = ATA_IN8(ATA_STATUS);
error = ATA_ERROR; error = ATA_IN8(ATA_ERROR);
if (count >= multisectors ) if (count >= multisectors)
sectors = multisectors; sectors = multisectors;
else else
sectors = count; sectors = count;
@ -543,7 +565,7 @@ static int ata_transfer_sectors(unsigned long start,
if(!ret && !wait_for_end_of_transfer()) { if(!ret && !wait_for_end_of_transfer()) {
int error; int error;
error = ATA_ERROR; error = ATA_IN8(ATA_ERROR);
perform_soft_reset(); perform_soft_reset();
ret = -4; ret = -4;
/* no point retrying IDNF, sector no. was invalid */ /* no point retrying IDNF, sector no. was invalid */
@ -767,20 +789,23 @@ int ata_write_sectors(IF_MD2(int drive,)
static int check_registers(void) static int check_registers(void)
{ {
int i; int i;
if ( ATA_STATUS & STATUS_BSY ) wait_for_bsy();
if (ATA_IN8(ATA_STATUS) & STATUS_BSY)
return -1; return -1;
for (i = 0; i<64; i++) { for (i = 0; i<64; i++) {
SET_REG(ATA_NSECTOR, WRITE_PATTERN1); ATA_OUT8(ATA_NSECTOR, TEST_PATTERN1);
SET_REG(ATA_SECTOR, WRITE_PATTERN2); ATA_OUT8(ATA_SECTOR, TEST_PATTERN2);
SET_REG(ATA_LCYL, WRITE_PATTERN3); ATA_OUT8(ATA_LCYL, TEST_PATTERN3);
SET_REG(ATA_HCYL, WRITE_PATTERN4); ATA_OUT8(ATA_HCYL, TEST_PATTERN4);
if (((ATA_NSECTOR & READ_PATTERN1_MASK) == READ_PATTERN1) && if ((ATA_IN8(ATA_NSECTOR) == TEST_PATTERN1) &&
((ATA_SECTOR & READ_PATTERN2_MASK) == READ_PATTERN2) && (ATA_IN8(ATA_SECTOR) == TEST_PATTERN2) &&
((ATA_LCYL & READ_PATTERN3_MASK) == READ_PATTERN3) && (ATA_IN8(ATA_LCYL) == TEST_PATTERN3) &&
((ATA_HCYL & READ_PATTERN4_MASK) == READ_PATTERN4)) (ATA_IN8(ATA_HCYL) == TEST_PATTERN4))
return 0; return 0;
sleep(1);
} }
return -2; return -2;
} }
@ -790,12 +815,12 @@ static int freeze_lock(void)
/* does the disk support Security Mode feature set? */ /* does the disk support Security Mode feature set? */
if (identify_info[82] & 2) if (identify_info[82] & 2)
{ {
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if (!wait_for_rdy()) if (!wait_for_rdy())
return -1; return -1;
SET_REG(ATA_COMMAND, CMD_SECURITY_FREEZE_LOCK); ATA_OUT8(ATA_COMMAND, CMD_SECURITY_FREEZE_LOCK);
if (!wait_for_rdy()) if (!wait_for_rdy())
return -2; return -2;
@ -822,14 +847,14 @@ static int ata_perform_sleep(void)
return 0; return 0;
} }
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if(!wait_for_rdy()) { if(!wait_for_rdy()) {
DEBUGF("ata_perform_sleep() - not RDY\n"); DEBUGF("ata_perform_sleep() - not RDY\n");
return -1; return -1;
} }
SET_REG(ATA_COMMAND, CMD_SLEEP); ATA_OUT8(ATA_COMMAND, CMD_SLEEP);
if (!wait_for_rdy()) if (!wait_for_rdy())
{ {
@ -989,7 +1014,7 @@ static int ata_hard_reset(void)
ata_reset(); ata_reset();
/* state HRR2 */ /* state HRR2 */
SET_REG(ATA_SELECT, ata_device); /* select the right device */ ATA_OUT8(ATA_SELECT, ata_device); /* select the right device */
ret = wait_for_bsy(); ret = wait_for_bsy();
/* Massage the return code so it is 0 on success and -1 on failure */ /* Massage the return code so it is 0 on success and -1 on failure */
@ -1010,15 +1035,15 @@ static int perform_soft_reset(void)
int ret; int ret;
int retry_count; int retry_count;
SET_REG(ATA_SELECT, SELECT_LBA | ata_device ); ATA_OUT8(ATA_SELECT, SELECT_LBA | ata_device );
SET_REG(ATA_CONTROL, CONTROL_nIEN|CONTROL_SRST ); ATA_OUT8(ATA_CONTROL, CONTROL_nIEN|CONTROL_SRST );
sleep(1); /* >= 5us */ sleep(1); /* >= 5us */
#ifdef HAVE_ATA_DMA #ifdef HAVE_ATA_DMA
/* DMA requires INTRQ be enabled */ /* DMA requires INTRQ be enabled */
SET_REG(ATA_CONTROL, 0); ATA_OUT8(ATA_CONTROL, 0);
#else #else
SET_REG(ATA_CONTROL, CONTROL_nIEN); ATA_OUT8(ATA_CONTROL, CONTROL_nIEN);
#endif #endif
sleep(1); /* >2ms */ sleep(1); /* >2ms */
@ -1089,15 +1114,15 @@ static int ata_power_on(void)
static int master_slave_detect(void) static int master_slave_detect(void)
{ {
/* master? */ /* master? */
SET_REG(ATA_SELECT, 0); ATA_OUT8(ATA_SELECT, 0);
if ( ATA_STATUS & (STATUS_RDY|STATUS_BSY) ) { if (ATA_IN8(ATA_STATUS) & (STATUS_RDY|STATUS_BSY)) {
ata_device = 0; ata_device = 0;
DEBUGF("Found master harddisk\n"); DEBUGF("Found master harddisk\n");
} }
else { else {
/* slave? */ /* slave? */
SET_REG(ATA_SELECT, SELECT_DEVICE1); ATA_OUT8(ATA_SELECT, SELECT_DEVICE1);
if ( ATA_STATUS & (STATUS_RDY|STATUS_BSY) ) { if (ATA_IN8(ATA_STATUS) & (STATUS_RDY|STATUS_BSY)) {
ata_device = SELECT_DEVICE1; ata_device = SELECT_DEVICE1;
DEBUGF("Found slave harddisk\n"); DEBUGF("Found slave harddisk\n");
} }
@ -1111,13 +1136,13 @@ static int identify(void)
{ {
int i; int i;
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if(!wait_for_rdy()) { if(!wait_for_rdy()) {
DEBUGF("identify() - not RDY\n"); DEBUGF("identify() - not RDY\n");
return -1; return -1;
} }
SET_REG(ATA_COMMAND, CMD_IDENTIFY); ATA_OUT8(ATA_COMMAND, CMD_IDENTIFY);
if (!wait_for_start_of_transfer()) if (!wait_for_start_of_transfer())
{ {
@ -1128,11 +1153,7 @@ static int identify(void)
for (i=0; i<SECTOR_SIZE/2; i++) { for (i=0; i<SECTOR_SIZE/2; i++) {
/* the IDENTIFY words are already swapped, so we need to treat /* the IDENTIFY words are already swapped, so we need to treat
this info differently that normal sector data */ this info differently that normal sector data */
#if defined(ROCKBOX_BIG_ENDIAN) && !defined(ATA_SWAP_WORDS) identify_info[i] = ATA_SWAP_IDENTIFY(ATA_IN16(ATA_DATA));
identify_info[i] = swap16(ATA_DATA);
#else
identify_info[i] = ATA_DATA;
#endif
} }
return 0; return 0;
@ -1140,15 +1161,15 @@ static int identify(void)
static int set_multiple_mode(int sectors) static int set_multiple_mode(int sectors)
{ {
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if(!wait_for_rdy()) { if(!wait_for_rdy()) {
DEBUGF("set_multiple_mode() - not RDY\n"); DEBUGF("set_multiple_mode() - not RDY\n");
return -1; return -1;
} }
SET_REG(ATA_NSECTOR, sectors); ATA_OUT8(ATA_NSECTOR, sectors);
SET_REG(ATA_COMMAND, CMD_SET_MULTIPLE_MODE); ATA_OUT8(ATA_COMMAND, CMD_SET_MULTIPLE_MODE);
if (!wait_for_rdy()) if (!wait_for_rdy())
{ {
@ -1221,7 +1242,7 @@ static int set_features(void)
features[4].parameter = dma_mode; features[4].parameter = dma_mode;
#endif /* HAVE_ATA_DMA */ #endif /* HAVE_ATA_DMA */
SET_REG(ATA_SELECT, ata_device); ATA_OUT8(ATA_SELECT, ata_device);
if (!wait_for_rdy()) { if (!wait_for_rdy()) {
DEBUGF("set_features() - not RDY\n"); DEBUGF("set_features() - not RDY\n");
@ -1230,19 +1251,19 @@ static int set_features(void)
for (i=0; i < (int)(sizeof(features)/sizeof(features[0])); i++) { for (i=0; i < (int)(sizeof(features)/sizeof(features[0])); i++) {
if (identify_info[features[i].id_word] & BIT_N(features[i].id_bit)) { if (identify_info[features[i].id_word] & BIT_N(features[i].id_bit)) {
SET_REG(ATA_FEATURE, features[i].subcommand); ATA_OUT8(ATA_FEATURE, features[i].subcommand);
SET_REG(ATA_NSECTOR, features[i].parameter); ATA_OUT8(ATA_NSECTOR, features[i].parameter);
SET_REG(ATA_COMMAND, CMD_SET_FEATURES); ATA_OUT8(ATA_COMMAND, CMD_SET_FEATURES);
if (!wait_for_rdy()) { if (!wait_for_rdy()) {
DEBUGF("set_features() - CMD failed\n"); DEBUGF("set_features() - CMD failed\n");
return -10 - i; return -10 - i;
} }
if((ATA_ALT_STATUS & STATUS_ERR) && (i != 1)) { if((ATA_IN8(ATA_ALT_STATUS) & STATUS_ERR) && (i != 1)) {
/* some CF cards don't like advanced powermanagement /* some CF cards don't like advanced powermanagement
even if they mark it as supported - go figure... */ even if they mark it as supported - go figure... */
if(ATA_ERROR & ERROR_ABRT) { if(ATA_IN8(ATA_ERROR) & ERROR_ABRT) {
return -20 - i; return -20 - i;
} }
} }
@ -1327,7 +1348,7 @@ int ata_init(void)
#ifdef HAVE_ATA_DMA #ifdef HAVE_ATA_DMA
/* DMA requires INTRQ be enabled */ /* DMA requires INTRQ be enabled */
SET_REG(ATA_CONTROL, 0); ATA_OUT8(ATA_CONTROL, 0);
#endif #endif
/* first try, hard reset at cold start only */ /* first try, hard reset at cold start only */
@ -1335,9 +1356,9 @@ int ata_init(void)
if (rc) if (rc)
{ /* failed? -> second try, always with hard reset */ { /* failed? -> second try, always with hard reset */
DEBUGF("ata: init failed, retrying...\n"); // DEBUGF("ata: init failed, retrying...\n");
rc = init_and_check(true); // rc = init_and_check(true);
if (rc) // if (rc)
return rc; return rc;
} }
@ -1469,7 +1490,6 @@ void ata_get_info(IF_MD2(int drive,)struct storage_info *info)
#endif #endif
int i; int i;
info->sector_size = SECTOR_SIZE; info->sector_size = SECTOR_SIZE;
info->num_sectors= total_sectors;
src = (unsigned short*)&identify_info[27]; src = (unsigned short*)&identify_info[27];
dest = (unsigned short*)vendor; dest = (unsigned short*)vendor;

26
firmware/target/arm/archos/av300/ata-target.h
View file

@ -33,32 +33,6 @@
#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0x340))) #define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0x340)))
#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x380))) #define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x380)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_enable(bool on); void ata_enable(bool on);
bool ata_is_coldstart(void); bool ata_is_coldstart(void);

31
firmware/target/arm/ata-target.h
View file

@ -32,43 +32,16 @@
#define ATA_COMMAND (*((volatile unsigned char*)(IDE_BASE + 0x1fc))) #define ATA_COMMAND (*((volatile unsigned char*)(IDE_BASE + 0x1fc)))
#define ATA_CONTROL (*((volatile unsigned char*)(IDE_BASE + 0x3f8))) #define ATA_CONTROL (*((volatile unsigned char*)(IDE_BASE + 0x3f8)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#if (CONFIG_CPU == PP5002) #if (CONFIG_CPU == PP5002)
#define SET_REG(reg,val) do { reg = (val); \ #define ATA_OUT8(reg,val) do { reg = (val); \
while (!(IDE_CFG_STATUS & 0x40)); \ while (!(IDE_CFG_STATUS & 0x40)); \
} while (0) } while (0)
#define SET_16BITREG(reg,val) reg = (val)
/* Plain C reading and writing. See comment in ata-as-arm.S */ /* Plain C reading and writing. See comment in ata-as-arm.S */
#elif defined CPU_PP502x #elif defined CPU_PP502x
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
/* asm optimized reading and writing */ /* asm optimized reading and writing */
#define ATA_OPTIMIZED_READING #define ATA_OPTIMIZED_READING
#define ATA_OPTIMIZED_WRITING #define ATA_OPTIMIZED_WRITING

26
firmware/target/arm/imx31/ata-target.h
View file

@ -46,32 +46,6 @@
#define ATA_COMMAND ATA_DRIVE_COMMAND #define ATA_COMMAND ATA_DRIVE_COMMAND
#define ATA_CONTROL ATA_DRIVE_CONTROL #define ATA_CONTROL ATA_DRIVE_CONTROL
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_device_init(void); void ata_device_init(void);
bool ata_is_coldstart(void); bool ata_is_coldstart(void);

26
firmware/target/arm/s3c2440/gigabeat-fx/ata-target.h
View file

@ -44,32 +44,6 @@ void copy_read_sectors(unsigned char* buf, int wordcount);
#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x0E))) #define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x0E)))
#define ATA_CONTROL (*((volatile unsigned char*)(0x20000000 + 0x1C))) #define ATA_CONTROL (*((volatile unsigned char*)(0x20000000 + 0x1C)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_device_init(void); void ata_device_init(void);
bool ata_is_coldstart(void); bool ata_is_coldstart(void);

26
firmware/target/arm/tms320dm320/creative-zvm/ata-target.h
View file

@ -53,32 +53,6 @@ extern int _ata_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE+0xE))) #define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE+0xE)))
#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE+0x800C))) #define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE+0x800C)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_device_init(void); void ata_device_init(void);
bool ata_is_coldstart(void); bool ata_is_coldstart(void);

6
firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c
View file

@ -62,7 +62,7 @@ void dma_ata_read(unsigned char* buf, int shortcount)
while((unsigned long)buf & 0x1F) while((unsigned long)buf & 0x1F)
{ {
unsigned short tmp; unsigned short tmp;
tmp = ATA_DATA; tmp = ATA_IN16(ATA_DATA);
*buf++ = tmp & 0xFF; *buf++ = tmp & 0xFF;
*buf++ = tmp >> 8; *buf++ = tmp >> 8;
shortcount--; shortcount--;
@ -86,7 +86,7 @@ void dma_ata_read(unsigned char* buf, int shortcount)
if(shortcount % 2) if(shortcount % 2)
{ {
unsigned short tmp; unsigned short tmp;
tmp = ATA_DATA; tmp = ATA_IN16(ATA_DATA);
*buf++ = tmp & 0xFF; *buf++ = tmp & 0xFF;
*buf++ = tmp >> 8; *buf++ = tmp >> 8;
} }
@ -102,7 +102,7 @@ void dma_ata_write(unsigned char* buf, int wordcount)
unsigned short tmp; unsigned short tmp;
tmp = (unsigned short) *buf++; tmp = (unsigned short) *buf++;
tmp |= (unsigned short) *buf++ << 8; tmp |= (unsigned short) *buf++ << 8;
SET_16BITREG(ATA_DATA, tmp); ATA_OUT16(ATA_DATA, tmp);
wordcount--; wordcount--;
} }

26
firmware/target/arm/tms320dm320/mrobe-500/ata-target.h
View file

@ -49,32 +49,6 @@ void copy_write_sectors(const unsigned char* buf, int wordcount);
#define ATA_COMMAND (*((volatile unsigned char*)(REGISTER_OFFSET + (0x07 << IDE_SHIFT)))) #define ATA_COMMAND (*((volatile unsigned char*)(REGISTER_OFFSET + (0x07 << IDE_SHIFT))))
#define ATA_CONTROL (*((volatile unsigned char*)(CONTROL_OFFSET + (0x06 << IDE_SHIFT)))) #define ATA_CONTROL (*((volatile unsigned char*)(CONTROL_OFFSET + (0x06 << IDE_SHIFT))))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_device_init(void); void ata_device_init(void);
bool ata_is_coldstart(void); bool ata_is_coldstart(void);

30
firmware/target/coldfire/ata-target.h
View file

@ -37,32 +37,10 @@
#define ATA_SELECT (*((volatile unsigned short*)(ATA_IOBASE + 0x2c))) #define ATA_SELECT (*((volatile unsigned short*)(ATA_IOBASE + 0x2c)))
#define ATA_COMMAND (*((volatile unsigned short*)(ATA_IOBASE + 0x2e))) #define ATA_COMMAND (*((volatile unsigned short*)(ATA_IOBASE + 0x2e)))
#define STATUS_BSY 0x8000 #define ATA_OUT8(reg,val) reg = ((val) << 8)
#define STATUS_RDY 0x4000 #define ATA_OUT16(reg,val) reg = swap16(val)
#define STATUS_DF 0x2000 #define ATA_IN8(reg) ((reg) >> 8)
#define STATUS_DRQ 0x0800 #define ATA_IN16(reg) (swap16(reg))
#define STATUS_ERR 0x0100
#define ERROR_ABRT 0x0400
#define ERROR_IDNF 0x1000
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa500
#define READ_PATTERN2 0x5a00
#define READ_PATTERN3 0xaa00
#define READ_PATTERN4 0x5500
#define READ_PATTERN1_MASK 0xff00
#define READ_PATTERN2_MASK 0xff00
#define READ_PATTERN3_MASK 0xff00
#define READ_PATTERN4_MASK 0xff00
#define SET_REG(reg,val) reg = ((val) << 8)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_enable(bool on); void ata_enable(bool on);

28
firmware/target/coldfire/mpio/ata-target.h
View file

@ -36,34 +36,6 @@
#define ATA_SELECT (*((volatile unsigned short*)(ATA_IOBASE + 0x2c))) #define ATA_SELECT (*((volatile unsigned short*)(ATA_IOBASE + 0x2c)))
#define ATA_COMMAND (*((volatile unsigned short*)(ATA_IOBASE + 0x2e))) #define ATA_COMMAND (*((volatile unsigned short*)(ATA_IOBASE + 0x2e)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
void ata_reset(void); void ata_reset(void);
void ata_enable(bool on); void ata_enable(bool on);
void ata_device_init(void); void ata_device_init(void);

27
firmware/target/sh/archos/ata-target.h
View file

@ -39,33 +39,6 @@
#define ATA_SELECT (*((volatile unsigned char*)ATA_IOBASE + 6)) #define ATA_SELECT (*((volatile unsigned char*)ATA_IOBASE + 6))
#define ATA_COMMAND (*((volatile unsigned char*)ATA_IOBASE + 7)) #define ATA_COMMAND (*((volatile unsigned char*)ATA_IOBASE + 7))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define ERROR_IDNF 0x10
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define READ_PATTERN1_MASK 0xff
#define READ_PATTERN2_MASK 0xff
#define READ_PATTERN3_MASK 0xff
#define READ_PATTERN4_MASK 0xff
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
extern volatile unsigned char* ata_control; extern volatile unsigned char* ata_control;
void ata_reset(void); void ata_reset(void);