mirror of
https://github.com/Rockbox/rockbox.git
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DM320: Re-write of crt0.S and update to app linker script.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29224 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun
parent
02dbde7097
commit
9241210050
2 changed files with 384 additions and 173 deletions
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@ -1,6 +1,6 @@
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#include "config.h"
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ENTRY(start)
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ENTRY(_start)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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@ -16,7 +16,7 @@ STARTUP(target/arm/tms320dm320/crt0.o)
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#define LCD_FUDGE LCD_NATIVE_WIDTH%32
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#define LCD_BUFFER_SIZE ((LCD_NATIVE_WIDTH+LCD_FUDGE)*LCD_NATIVE_HEIGHT*2)
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#define LCD_BUFFER_SIZE ((LCD_NATIVE_WIDTH+LCD_FUDGE)*LCD_NATIVE_HEIGHT*2)
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/* must be 16Kb (0x4000) aligned */
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#define TTB_SIZE 0x4000
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@ -30,112 +30,144 @@ STARTUP(target/arm/tms320dm320/crt0.o)
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#define DRAMSIZE (MEMORYSIZE * 0x100000)
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#define DRAMORIG 0x00900000
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 0x4000
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#define FLASHORIG 0x00100000
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#define FLASHSIZE 0x00800000
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#define ITCMORIG 0x00000000
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#define ITCMSIZE 0x4000
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#define DTCMORIG 0x00020000
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#define DTCMSIZE 0x4000
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PRO_STACK_SIZE = 0x2000;
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IRQ_STACK_SIZE = 0x600;
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FIQ_STACK_SIZE = 0x400;
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/* End of the audio buffer, where the codec buffer starts */
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#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_TTB_AREA)
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#define ENDAUDIOADDR \
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(DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_TTB_AREA)
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MEMORY
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{
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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ITCM : ORIGIN = ITCMORIG, LENGTH = ITCMSIZE
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DTCM : ORIGIN = DTCMORIG, LENGTH = DTCMSIZE
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}
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SECTIONS
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{
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/* Set up variables needed for memory initialization */
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_sdram_start = DRAMORIG;
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_sdram_sizem = ((_endsdram - _sdram_start) / 0x100000);
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_flash_start = FLASHORIG;
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_flash_sizem = (FLASHSIZE / 0x100000);
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/* crt0.S initialization */
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.init :
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{
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. = ALIGN(0x4);
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loadaddress = .;
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*(.init)
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} > DRAM
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.vectors ITCMORIG :
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{
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. = ALIGN(0x4);
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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} > ITCM AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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*(.text*)
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} > DRAM
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/* Thumb interworking sections - for some reason LD dies even if these
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* sections are empty.
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*/
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.glue :
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{
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. = ALIGN(0x4);
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*(.glue_7) /* ARM calling Thumb */
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*(.glue_7t) /* Thumb calling ARM */
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} > DRAM
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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. = ALIGN(0x4);
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*(.rodata*)
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} > DRAM
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.data :
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{
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*(.data*)
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. = ALIGN(0x4);
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*(.data*)
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} > DRAM
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/DISCARD/ :
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.bss (NOLOAD) :
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{
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*(.eh_frame)
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}
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.vectors IRAMORIG :
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{
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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} > IRAM AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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. = ALIGN(0x4);
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_bss_start = .;
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*(.bss*)
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*(COMMON)
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_bss_end = .;
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} > DRAM
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.iram :
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{
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. = ALIGN(0x4);
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_iramstart = .;
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*(.icode)
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*(.irodata*)
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*(.irodata)
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*(.idata)
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. = ALIGN(0x4);
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_iramend = .;
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} > IRAM AT> DRAM
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} > ITCM AT> DRAM
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_iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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.ibss DTCMORIG + _iramend (NOLOAD) :
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{
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_iedata = .;
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. = ALIGN(0x4);
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_ibss_start = .;
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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} > IRAM
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_ibss_end = .;
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} > DTCM
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.stack (NOLOAD) :
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/* Program stack space */
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.pro_stack (NOLOAD):
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{
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*(.stack)
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stackbegin = .;
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. += 0x2000;
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stackend = .;
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} > IRAM
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.irqstack (NOLOAD) :
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{
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*(.stack)
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. += 0x400;
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irq_stack = .;
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} > IRAM
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.fiqstack (NOLOAD) :
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{
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*(.stack)
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. += 0x400;
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fiq_stack = .;
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} > IRAM
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/* This overwrites the iram (in ram), so make sure that the iram is copied
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* out in crt0.s before the bss section and the rest are used.
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*/
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.bss (NOLOAD) :
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{
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. = ADDR(.data) + SIZEOF(.data);
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_edata = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(0x4);
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_end = .;
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} > DRAM
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*(.stack)
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stackbegin = .; /* Variable for thread.c */
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_pro_stack_end = .;
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. += PRO_STACK_SIZE;
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_pro_stack_start = .;
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stackend = .; /* Variable for tread.c */
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} > DTCM
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/* IRQ stack space */
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.irq_stack (NOLOAD):
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{
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. = ALIGN(0x4);
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_irq_stack_end = .;
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. += IRQ_STACK_SIZE;
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_irq_stack_start = .;
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} > DTCM
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/* FIQ stack space */
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.fiq_stack (NOLOAD):
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{
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. = ALIGN(0x4);
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_fiq_stack_end = .;
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. += FIQ_STACK_SIZE;
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_fiq_stack_start = .;
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} > DTCM
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.audiobuf (NOLOAD) :
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{
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@ -160,6 +192,8 @@ SECTIONS
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. += PLUGIN_BUFFER_SIZE;
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} > DRAM
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_endsdram = .;
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.ttbtable (NOLOAD) :
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{
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. = ALIGN (0x4000);
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@ -7,12 +7,7 @@
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* Arm bootloader and startup code based on startup.s from the iPodLinux loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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* Copyright (C) 2010 by Karl Kurbjun
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -26,25 +21,83 @@
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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#define CACHE_NONE 0
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#define CACHE_ALL 0x0C
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#define BUFFERED 0x04
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.global start
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start:
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msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#define LONG_VECTORS 1
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#ifndef CREATIVE_ZVx
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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/******************************************************************************
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* vectors: *
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* This is the ARM vector table *
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* Long call exception handlers are used for simplicity between flash *
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* bootloader and SDRAM main-application. These need to be copied to address *
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* 0x0 at start. *
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******************************************************************************/
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.section .vectors,"ax"
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.code 32
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.global _vectors
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@entry:
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_vectors:
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#if defined(SHORT_VECTORS) /* Use relative branch vectors (64 MB limit) */
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b _start /* Reset Vector */
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b _undefined_instruction /* Undefined instruction */
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b _software_interrupt /* Software Vector */
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b _prefetch_abort /* Prefetch Abort */
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b _data_abort /* Data Abort */
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b _dead_loop /* Reserved/Unused */
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b irq_handler /* IRQ vector */
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b fiq_handler /* FIQ vector */
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#else
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#if defined(LONG_VECTORS)
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/* Load the PC with the word values stored below */
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ldr pc, [pc, #0x18] /* Reset */
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ldr pc, [pc, #0x18] /* Undefined instruction */
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ldr pc, [pc, #0x18] /* Software interrupt */
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ldr pc, [pc, #0x18] /* Prefetch Abort */
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ldr pc, [pc, #0x18] /* Data Abort */
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ldr pc, [pc, #0x18] /* Reserved/Unused */
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ldr pc, [pc, #0x18] /* IRQ */
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ldr pc, [pc, #0x18] /* FIQ */
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/* Addresses of the handlers */
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.word _start
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.word _undefined_instruction
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.word _software_interrupt
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.word _prefetch_abort
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.word _data_abort
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.word _dead_loop
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.word irq_handler
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.word fiq_handler
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#else
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#error Vector type undefined
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#endif
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#endif
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/* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
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/******************************************************************************
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* _start: *
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* This is the main entry point to the program *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _start
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_start:
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/* Go into supervisor state with IRQ's disabled.
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* This register is described in section "A2.5 Program status registers"
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* of the "ARM Architecture Reference Manual".
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*/
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msr cpsr, #0xd3
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/* Disable all the fancy stuff */
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mov r0, #0
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mcr p15, 0, r0, c1, c0, 0
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/* Disable data and instruction cache, high vectors (at 0xffff0000 instead
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* of 0x00000000)
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*/
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mrc p15, 0, r0, c1, c0, 0
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/* clear bits 13, 9:8 (--VI --RS) */
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bic r0, r0, #0x00003300
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@ -54,112 +107,236 @@ start:
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orr r0, r0, #0x00000002
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mcr p15, 0, r0, c1, c0, 0
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#if !defined(STUB)
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Add a few cycles of delay before continuing due to system requirements */
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mov r0, #0x20
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bl _delay_cycles
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#ifndef CREATIVE_ZVx
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#if defined(BOOTLOADER)
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bl _init_board
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#endif
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#endif /* !STUB */
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/* Copy exception handler code to address 0 */
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ldr r0, =_vectorscopy
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ldr r1, =_vectorsstart
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ldr r2, =_vectorsend
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bl _copy_section
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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bsszero:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi bsszero
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/* Add some delay time to make sure JTAG can be accessed cleanly */
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mov r0, #0x100000
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bl _delay_cycles
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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stackmunge:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi stackmunge
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#if defined(BOOTLOADER)
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/* Copy the DRAM */
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ldr r0, =_dramcopy
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ldr r1, =_dramstart
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ldr r2, =_dramend
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bl _copy_section
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#endif
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2 /* IRQ disabled, FIQ enabled */
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */
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ldr sp, =fiq_stack
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/* Zero out the IBSS */
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mov r0, #0
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ldr r1, =_ibss_start
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ldr r2, =_ibss_end
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bl _init_section
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/* Let abort and undefined modes use IRQ stack */
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msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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/* Copy the IRAM */
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ldr r0, =_iramcopy
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ldr r1, =_iramstart
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ldr r2, =_iramend
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bl _copy_section
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/* Switch to supervisor mode (no IRQ) */
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msr cpsr_c, #0xd3
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ldr sp, =stackend
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/* Zero out the BSS */
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mov r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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bl _init_section
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start_loc:
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bl main
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/* main() should never return */
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/* Initialize fiq stack */
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ldr r0, =0xDEADBEEF
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ldr r1, =_fiq_stack_end /* Stack counts backwards, so end is first*/
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ldr r2, =_fiq_stack_start
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bl _init_section
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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.section .vectors,"aw"
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b start
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b undef_instr_handler
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b software_int_handler
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b prefetch_abort_handler
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b data_abort_handler
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b reserved_handler
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b irq_handler
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b fiq_handler
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msr cpsr_c, #0xd1 /* Go into fiq state */
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ldr sp, =_fiq_stack_start /* set the fiq stack pointer */
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.text
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/* Initialize irq stack */
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ldr r0, =0xDEADBEEF /* Can be taken out; left for clarity */
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ldr r1, =_irq_stack_end /* Stack counts backwards, so end is first*/
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ldr r2, =_irq_stack_start
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bl _init_section
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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we're in. Second parameter is exception number, used for a string lookup
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in UIE.
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msr cpsr_c, #0xd2 /* Go into irq state */
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ldr sp, =_irq_stack_start /* set the irq stack pointer */
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|
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/* This should not be needed, but set the stack location for abort and
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* undefined to at least a known stack location (IRQ)
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*/
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msr cpsr_c, #0xd7 /* Go into abort state */
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ldr sp, =_irq_stack_start /* set the stack pointer */
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|
||||
msr cpsr_c, #0xdb /* Go into undefined state */
|
||||
ldr sp, =_irq_stack_start /* set the stack pointer */
|
||||
|
||||
/* Initialize program stack */
|
||||
msr cpsr_c, #0xd3 /* Go into supervisor state */
|
||||
ldr r0, =0xDEADBEEF /* Can be taken out; left for clarity */
|
||||
ldr r1, =_pro_stack_end /* Stack counts backwards, so end is first*/
|
||||
ldr r2, =_pro_stack_start
|
||||
bl _init_section
|
||||
|
||||
ldr sp, =_pro_stack_start /* set the supervisor stack pointer */
|
||||
|
||||
/* MMU initialization */
|
||||
bl ttb_init
|
||||
|
||||
/* Make sure everything is mapped on itself */
|
||||
ldr r0, =0x0
|
||||
ldr r1, =0x0
|
||||
ldr r2, =0x1000
|
||||
mov r3, #CACHE_NONE
|
||||
bl map_section
|
||||
|
||||
/* Enable caching for FLASH */
|
||||
ldr r0, =_flash_start
|
||||
ldr r1, =_flash_start
|
||||
ldr r2, =_flash_sizem
|
||||
mov r3, #CACHE_ALL
|
||||
bl map_section
|
||||
|
||||
/* Enable caching for RAM */
|
||||
ldr r0, =_sdram_start
|
||||
ldr r1, =_sdram_start
|
||||
ldr r2, =_sdram_sizem
|
||||
mov r3, #CACHE_ALL
|
||||
bl map_section
|
||||
|
||||
bl enable_mmu
|
||||
|
||||
/* Initial setup is complete, go into main */
|
||||
ldr pc, =main
|
||||
|
||||
/* If main returns go into an infinite loop */
|
||||
b _dead_loop
|
||||
|
||||
/* Constants go here (from _start - .ltorg): */
|
||||
.ltorg
|
||||
|
||||
/******************************************************************************
|
||||
* _init_section: *
|
||||
* This function initializes a section with the 32-bit value specified. *
|
||||
******************************************************************************/
|
||||
.section .init, "ax"
|
||||
.code 32
|
||||
.align 0x04
|
||||
.global _init_section
|
||||
.type _init_section, %function
|
||||
/* r0 = init value
|
||||
* r1 = start location
|
||||
* r2 = end location
|
||||
*/
|
||||
undef_instr_handler:
|
||||
|
||||
/* This function will not run if end is less than or equal to start */
|
||||
_init_section:
|
||||
cmp r2, r1
|
||||
strhi r0, [r1], #4 /* store and increment start location */
|
||||
bhi _init_section
|
||||
bx lr
|
||||
.ltorg
|
||||
.size _init_section, .-_init_section
|
||||
|
||||
/******************************************************************************
|
||||
* _copy_section: *
|
||||
* This function copies a section to a new location *
|
||||
******************************************************************************/
|
||||
.section .init, "ax"
|
||||
.code 32
|
||||
.align 0x04
|
||||
.global _copy_section
|
||||
.type _copy_section, %function
|
||||
/* r0 = source address
|
||||
* r1 = destination start address
|
||||
* r2 = destination end address
|
||||
*
|
||||
* r3 is a scratch register
|
||||
*/
|
||||
|
||||
_copy_section:
|
||||
cmp r2, r1
|
||||
ldrhi r3, [r0], #4
|
||||
strhi r3, [r1], #4
|
||||
bhi _copy_section
|
||||
bx lr
|
||||
.ltorg
|
||||
.size _copy_section, .-_copy_section
|
||||
|
||||
/******************************************************************************
|
||||
* _delay_cycles: *
|
||||
* This function delays for the specified number of cycles *
|
||||
******************************************************************************/
|
||||
.section .init, "ax"
|
||||
.code 32
|
||||
.align 0x04
|
||||
.global _delay_cycles
|
||||
.type _delay_cycles, %function
|
||||
/* r0 = number of cycles to delay */
|
||||
|
||||
/* If r0 is zero it will be the maximum length delay */
|
||||
_delay_cycles:
|
||||
subs r0, r0, #1
|
||||
bne _delay_cycles
|
||||
bx lr
|
||||
.ltorg
|
||||
.size _delay_cycles, .-_delay_cycles
|
||||
|
||||
/******************************************************************************
|
||||
* Unused exception vectors. These call the UIE function. *
|
||||
* Arguements are: *
|
||||
* r0: PC of exception *
|
||||
* r1: Exception number. *
|
||||
* Exception numbers are as defined: *
|
||||
* 0: Undefined Instruction *
|
||||
* 1: Prefetch Abort *
|
||||
* 2: Data Abort *
|
||||
* The exceptions return operations are documented in section A2.6 of the *
|
||||
* ARM Architecture Reference Manual. *
|
||||
******************************************************************************/
|
||||
|
||||
/* A2.6.3: Undefined Instruction Exception - LR=PC of next instruction */
|
||||
_undefined_instruction:
|
||||
sub r0, lr, #4
|
||||
mov r1, #0
|
||||
b UIE
|
||||
bl UIE
|
||||
|
||||
/* We run supervisor mode most of the time, and should never see a software
|
||||
exception being thrown. Perhaps make it illegal and call UIE?
|
||||
/* A2.6.4: Software Interrupt exception - These should not happen in Rockbox,
|
||||
* but for now leave this as a placeholder and continue with the program.
|
||||
* LR=PC of next instruction.
|
||||
*/
|
||||
software_int_handler:
|
||||
reserved_handler:
|
||||
movs pc, lr
|
||||
_software_interrupt:
|
||||
mov pc, lr
|
||||
|
||||
prefetch_abort_handler:
|
||||
/* A2.6.5 Prefetch Abort - This is also the BKPT instruction since this is a
|
||||
* v5 target. Pass it on to UIE since it is not currently used.
|
||||
*/
|
||||
_prefetch_abort:
|
||||
sub r0, lr, #4
|
||||
mov r1, #1
|
||||
b UIE
|
||||
bl UIE
|
||||
|
||||
data_abort_handler:
|
||||
/* A2.6.6 Data Abort - There was a memory abort, can return after fixing cause
|
||||
* with the LR address.
|
||||
*/
|
||||
_data_abort:
|
||||
sub r0, lr, #8
|
||||
mov r1, #2
|
||||
b UIE
|
||||
bl UIE
|
||||
|
||||
#ifdef STUB
|
||||
UIE:
|
||||
b UIE
|
||||
#endif
|
||||
/******************************************************************************
|
||||
* _dead_loop: Something really unexpected happened (like a reserved *
|
||||
* exception). Just hang. *
|
||||
******************************************************************************/
|
||||
_dead_loop:
|
||||
b _dead_loop
|
||||
|
||||
.ltorg
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue