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Coldfire: Properly handle the SDRAM refresh timing on CPU frequency changes. For >= 92 MHz operation, tRC needs to be 6 clocks, otherwise 3 clocks are sufficient.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7743 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2005-11-03 20:01:58 +00:00
parent 4b03c14a3e
commit 8f71973918
1 changed files with 5 additions and 4 deletions
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7
firmware/system.c
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@ -587,7 +587,7 @@ void set_cpu_frequency(long frequency)
switch(frequency)
{
case CPUFREQ_MAX:
DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
/* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
@ -597,7 +597,7 @@ void set_cpu_frequency(long frequency)
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
This may take up to 10ms! */
timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
DCR = (DCR & ~0x01ff) | MAX_REFRESH_TIMER; /* Refresh timer */
DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_MAX;
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
@ -614,7 +614,7 @@ void set_cpu_frequency(long frequency)
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
This may take up to 10ms! */
timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
DCR = (DCR & ~0x01ff) | NORMAL_REFRESH_TIMER; /* Refresh timer */
DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_NORMAL;
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
@ -627,6 +627,7 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_DEFAULT;
IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */