mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-07 13:45:03 -05:00
Clean up PP502x CPU clock setup code and use the full 80MHz when boosted.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14004 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
5c1d259fe2
commit
8d3ac97aff
4 changed files with 96 additions and 95 deletions
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@ -135,6 +135,7 @@
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#define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020))
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#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034))
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#define PLL_STATUS (*(volatile unsigned long *)(0x6000603c))
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#define CLCD_CLOCK_SRC (*(volatile unsigned long *)(0x600060a0))
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/* Processors Control */
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#define CPU_CTL (*(volatile unsigned long *)(0x60007000))
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@ -254,6 +255,8 @@
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#define PP_VER1 (*(volatile unsigned long *)(0x70000000))
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#define PP_VER2 (*(volatile unsigned long *)(0x70000004))
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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/* some timing that needs to be handled during clock setup */
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#define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
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#define INIT_USB 0x80000000
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@ -26,20 +26,6 @@
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have conflicts with another system-target.h elsewhere so include a
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subheader from here. */
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/* TODO: Implement set_irq_level and check CPU frequencies */
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#if CONFIG_CPU != S3C2440 && CONFIG_CPU != PNX0101
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/* TODO: Finish targeting this stuff */
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#define CPUFREQ_DEFAULT_MULT 4
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL_MULT 5
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX_MULT 13
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#define CPUFREQ_MAX 78000000
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#endif
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static inline uint16_t swap16(uint16_t value)
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/*
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result[15..8] = value[ 7..0];
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@ -114,12 +114,11 @@ void irq(void)
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#endif
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#endif /* BOOTLOADER */
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/* TODO: The following two function have been lifted straight from IPL, and
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hence have a lot of numeric addresses used straight. I'd like to use
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/* TODO: The following function has been lifted straight from IPL, and
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hence has a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations and/or
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some other CPU frequency scaling. */
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to extend the funtions to do alternate cache configurations. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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@ -144,93 +143,98 @@ static void ipod_init_cache(void)
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for (i = 0x10000000; i < 0x10002000; i += 16)
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inb(i);
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}
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#endif
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/* Not all iPod targets support CPU freq. boosting yet */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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#else
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static void pp_set_cpu_frequency(long frequency)
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#endif
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{
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unsigned long postmult, pll_control;
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unsigned long unknown1, unknown2;
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unsigned long clcd_clock_src;
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bool use_pll = true;
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# if NUM_CORES > 1
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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/* Using mutex or spinlock isn't safe here. */
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while (test_and_set(&boostctrl_mtx.locked, 1)) ;
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# endif
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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#endif
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#ifdef SANSA_E200
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i2s_scale_attn_level(CPUFREQ_DEFAULT);
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#endif
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unknown2 = inl(0x600060a0);
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cpu_frequency = frequency;
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clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
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outl(inl(0x70000020) | (1<<30), 0x70000020); /* Enable PLL power */
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CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf000000f) | 0x10000002;
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/* set clock source 1 to 24MHz and select it */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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/* Set clock source #1 to 24MHz and select it */
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outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
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switch (frequency)
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{
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#if CONFIG_CPU == PP5020
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case CPUFREQ_MAX:
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DEV_TIMING1 = 0x00000808;
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PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
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PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */
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PLL_CONTROL = 0x8a020a03; /* repeat setup */
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udelay(500); /* wait for relock */
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break;
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outl(inl(0x600060a0) & ~0xc0000000, 0x600060a0);
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case CPUFREQ_NORMAL:
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
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udelay(500); /* wait for relock */
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break;
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unknown1 = (138 * postmult + 255) >> 8;
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if (unknown1 > 15)
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unknown1 = 15;
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outl((unknown1 << 8) | unknown1, 0x70000034);
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default:
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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use_pll = false;
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cpu_frequency = CPUFREQ_DEFAULT;
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break;
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/* PLL frequency = (24/4)*postmult */
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pll_control = 0x8a020000 | 4 | (postmult << 8);
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outl(pll_control, 0x60006034);
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# if CONFIG_CPU == PP5020
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outl(0xd19b, 0x6000603c); /* magic sequence */
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outl(pll_control, 0x60006034);
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udelay(500); /* wait for relock */
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# else /* PP5022, PP5024 */
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udelay(250);
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while (!(inl(0x6000603c) & 0x80000000)); /* wait for relock */
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# endif
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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/* Note: The PP5022 PLL must be run at >= 96MHz
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* Bits 20..21 select the post divider (1/2/4/8).
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* PP5026 is similar to PP5022 except it doesn't
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* have this limitation (and the post divider?) */
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case CPUFREQ_MAX:
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DEV_TIMING1 = 0x00000808;
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PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */
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udelay(250);
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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break;
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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case CPUFREQ_NORMAL:
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */
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udelay(250);
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while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
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break;
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inl(0x600060a0); /* sync pipeline (?) */
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outl(unknown2, 0x600060a0);
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default:
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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use_pll = false;
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cpu_frequency = CPUFREQ_DEFAULT;
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break;
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#endif
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}
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if (use_pll) /* set clock source 2 to PLL and select it */
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CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf00000f0) | 0x20000070;
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CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */
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CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
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#ifdef SANSA_E200
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i2s_scale_attn_level(frequency);
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#endif
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# if NUM_CORES > 1
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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boostctrl_mtx.locked = 0;
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# endif
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}
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#elif !defined(BOOTLOADER)
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void ipod_set_cpu_frequency(void)
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{
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/* For e200, just use clocking set up by OF loader for now */
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#ifndef SANSA_E200
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
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/* Clock frequency = (24/8)*25 = 75MHz */
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outl(0x8a020000 | 8 | (25 << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(500);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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#endif /* SANSA_E200 */
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}
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#endif
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}
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#endif /* !BOOTLOADER */
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void system_init(void)
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{
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@ -273,29 +277,20 @@ void system_init(void)
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#ifdef SANSA_E200
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/* outl(0x00000000, 0x6000b000); */
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outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
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}
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#endif
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ipod_init_cache();
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#else /* !sansa E200 */
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DEV_INIT |= 1 << 30; /* enable PLL power */
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# if NUM_CORES > 1 && defined(HAVE_ADJUSTABLE_CPU_FREQ)
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#if NUM_CORES > 1
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spinlock_init(&boostctrl_mtx);
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# endif
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
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ipod_set_cpu_frequency();
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#endif
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#else
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pp_set_cpu_frequency(CPUFREQ_MAX);
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#endif
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}
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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else
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{
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ipod_set_cpu_frequency();
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}
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#endif
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ipod_init_cache();
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#endif /* SANSA_E200 */
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#endif /* BOOTLOADER */
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}
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@ -22,6 +22,23 @@
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#include "system-arm.h"
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/* TODO: This header is actually portalplayer specific, and should be
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* moved into an appropriate subdir (or even split in 2). */
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#if CONFIG_CPU == PP5002
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#define CPUFREQ_DEFAULT_MULT 4
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL_MULT 5
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX_MULT 13
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#define CPUFREQ_MAX 78000000
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#else /* PP5022, PP5024 */
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#define CPUFREQ_DEFAULT 24000000
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#define CPUFREQ_NORMAL 30000000
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#define CPUFREQ_MAX 80000000
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#endif
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#define inl(a) (*(volatile unsigned long *) (a))
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#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
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#define inb(a) (*(volatile unsigned char *) (a))
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