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rk27xx: only list PLL settings for the rates a target has

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set_codec_freq()'s table of codec PLL settings names every rate from 8 to
96 kHz by its HW_FREQ_ index, which exists only for rates in the target's
HW_SAMPR_CAPS. Every CODEC_SLAVE target so far has all of them; a codec
without 96 kHz at 256 fs - the WM8750 - leaves HW_FREQ_96 undefined and
the table no longer builds.

Wrap each entry in HW_HAVE_xx_(), as the codec drivers' tables do. For
the existing targets the table is unchanged.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Change-Id: Ifab688ffa6f83c5319d686fcf40fc2b887c75d24
This commit is contained in:
Marcin Bukat 2026-09-25 15:43:35 +02:00
parent 98f162b212
commit 8a53c15d1c
1 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

20
firmware/target/arm/rk27xx/pcm-rk27xx.c
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@ -190,16 +190,16 @@ static void set_codec_freq(unsigned int freq)
/* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */
static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] =
{
[HW_FREQ_96] = {24, 255, 4, 1},
[HW_FREQ_48] = {24, 127, 4, 1},
[HW_FREQ_44] = {24, 293, 4, 4},
[HW_FREQ_32] = {24, 127, 4, 2},
[HW_FREQ_24] = {24, 127, 4, 3},
[HW_FREQ_22] = {24, 146, 4, 4},
[HW_FREQ_16] = {24, 127, 5, 4},
[HW_FREQ_12] = {24, 127, 4, 7},
[HW_FREQ_11] = {24, 146, 4, 9},
[HW_FREQ_8] = {24, 127, 5, 9},
HW_HAVE_96_([HW_FREQ_96] = {24, 255, 4, 1},)
HW_HAVE_48_([HW_FREQ_48] = {24, 127, 4, 1},)
HW_HAVE_44_([HW_FREQ_44] = {24, 293, 4, 4},)
HW_HAVE_32_([HW_FREQ_32] = {24, 127, 4, 2},)
HW_HAVE_24_([HW_FREQ_24] = {24, 127, 4, 3},)
HW_HAVE_22_([HW_FREQ_22] = {24, 146, 4, 4},)
HW_HAVE_16_([HW_FREQ_16] = {24, 127, 5, 4},)
HW_HAVE_12_([HW_FREQ_12] = {24, 127, 4, 7},)
HW_HAVE_11_([HW_FREQ_11] = {24, 146, 4, 9},)
HW_HAVE_8_([HW_FREQ_8] = {24, 127, 5, 9},)
};
/* select divider output from codec pll */
SCU_DIVCON1 &= ~((1<<9) | (0xF<<5));