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https://github.com/Rockbox/rockbox.git
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x1000: Extend CPM registers for dual boot
Change-Id: I283834a653506fd95ff8b56897e5f3afaf375cf5
This commit is contained in:
Aidan MacDonald
parent
2d6ddd0c5b
commit
89f4064743
2 changed files with 177 additions and 0 deletions
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@ -233,6 +233,44 @@
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#define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e)
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#define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e)
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#define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG
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#define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG
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#define REG_CPM_MACCDR jz_reg(CPM_MACCDR)
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#define JA_CPM_MACCDR (0xb0000000 + 0x54)
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#define JT_CPM_MACCDR JIO_32_RW
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#define JN_CPM_MACCDR CPM_MACCDR
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#define JI_CPM_MACCDR
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#define BP_CPM_MACCDR_CLKDIV 0
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#define BM_CPM_MACCDR_CLKDIV 0xff
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#define BF_CPM_MACCDR_CLKDIV(v) (((v) & 0xff) << 0)
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#define BFM_CPM_MACCDR_CLKDIV(v) BM_CPM_MACCDR_CLKDIV
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#define BF_CPM_MACCDR_CLKDIV_V(e) BF_CPM_MACCDR_CLKDIV(BV_CPM_MACCDR_CLKDIV__##e)
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#define BFM_CPM_MACCDR_CLKDIV_V(v) BM_CPM_MACCDR_CLKDIV
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#define BP_CPM_MACCDR_CLKSRC 31
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#define BM_CPM_MACCDR_CLKSRC 0x80000000
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#define BV_CPM_MACCDR_CLKSRC__SCLK_A 0x0
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#define BV_CPM_MACCDR_CLKSRC__MPLL 0x1
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#define BF_CPM_MACCDR_CLKSRC(v) (((v) & 0x1) << 31)
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#define BFM_CPM_MACCDR_CLKSRC(v) BM_CPM_MACCDR_CLKSRC
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#define BF_CPM_MACCDR_CLKSRC_V(e) BF_CPM_MACCDR_CLKSRC(BV_CPM_MACCDR_CLKSRC__##e)
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#define BFM_CPM_MACCDR_CLKSRC_V(v) BM_CPM_MACCDR_CLKSRC
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#define BP_CPM_MACCDR_CE 29
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#define BM_CPM_MACCDR_CE 0x20000000
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#define BF_CPM_MACCDR_CE(v) (((v) & 0x1) << 29)
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#define BFM_CPM_MACCDR_CE(v) BM_CPM_MACCDR_CE
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#define BF_CPM_MACCDR_CE_V(e) BF_CPM_MACCDR_CE(BV_CPM_MACCDR_CE__##e)
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#define BFM_CPM_MACCDR_CE_V(v) BM_CPM_MACCDR_CE
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#define BP_CPM_MACCDR_BUSY 28
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#define BM_CPM_MACCDR_BUSY 0x10000000
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#define BF_CPM_MACCDR_BUSY(v) (((v) & 0x1) << 28)
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#define BFM_CPM_MACCDR_BUSY(v) BM_CPM_MACCDR_BUSY
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#define BF_CPM_MACCDR_BUSY_V(e) BF_CPM_MACCDR_BUSY(BV_CPM_MACCDR_BUSY__##e)
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#define BFM_CPM_MACCDR_BUSY_V(v) BM_CPM_MACCDR_BUSY
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#define BP_CPM_MACCDR_STOP 27
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#define BM_CPM_MACCDR_STOP 0x8000000
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#define BF_CPM_MACCDR_STOP(v) (((v) & 0x1) << 27)
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#define BFM_CPM_MACCDR_STOP(v) BM_CPM_MACCDR_STOP
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#define BF_CPM_MACCDR_STOP_V(e) BF_CPM_MACCDR_STOP(BV_CPM_MACCDR_STOP__##e)
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#define BFM_CPM_MACCDR_STOP_V(v) BM_CPM_MACCDR_STOP
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#define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR)
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#define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR)
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#define JA_CPM_I2SCDR (0xb0000000 + 0x60)
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#define JA_CPM_I2SCDR (0xb0000000 + 0x60)
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#define JT_CPM_I2SCDR JIO_32_RW
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#define JT_CPM_I2SCDR JIO_32_RW
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@ -492,6 +530,108 @@
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#define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e)
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#define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e)
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#define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP
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#define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP
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#define REG_CPM_CIMCDR jz_reg(CPM_CIMCDR)
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#define JA_CPM_CIMCDR (0xb0000000 + 0x7c)
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#define JT_CPM_CIMCDR JIO_32_RW
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#define JN_CPM_CIMCDR CPM_CIMCDR
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#define JI_CPM_CIMCDR
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#define BP_CPM_CIMCDR_CLKDIV 0
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#define BM_CPM_CIMCDR_CLKDIV 0xff
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#define BF_CPM_CIMCDR_CLKDIV(v) (((v) & 0xff) << 0)
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#define BFM_CPM_CIMCDR_CLKDIV(v) BM_CPM_CIMCDR_CLKDIV
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#define BF_CPM_CIMCDR_CLKDIV_V(e) BF_CPM_CIMCDR_CLKDIV(BV_CPM_CIMCDR_CLKDIV__##e)
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#define BFM_CPM_CIMCDR_CLKDIV_V(v) BM_CPM_CIMCDR_CLKDIV
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#define BP_CPM_CIMCDR_CLKSRC 31
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#define BM_CPM_CIMCDR_CLKSRC 0x80000000
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#define BV_CPM_CIMCDR_CLKSRC__SCLK_A 0x1
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#define BV_CPM_CIMCDR_CLKSRC__MPLL 0x1
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#define BF_CPM_CIMCDR_CLKSRC(v) (((v) & 0x1) << 31)
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#define BFM_CPM_CIMCDR_CLKSRC(v) BM_CPM_CIMCDR_CLKSRC
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#define BF_CPM_CIMCDR_CLKSRC_V(e) BF_CPM_CIMCDR_CLKSRC(BV_CPM_CIMCDR_CLKSRC__##e)
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#define BFM_CPM_CIMCDR_CLKSRC_V(v) BM_CPM_CIMCDR_CLKSRC
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#define BP_CPM_CIMCDR_CE 29
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#define BM_CPM_CIMCDR_CE 0x20000000
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#define BF_CPM_CIMCDR_CE(v) (((v) & 0x1) << 29)
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#define BFM_CPM_CIMCDR_CE(v) BM_CPM_CIMCDR_CE
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#define BF_CPM_CIMCDR_CE_V(e) BF_CPM_CIMCDR_CE(BV_CPM_CIMCDR_CE__##e)
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#define BFM_CPM_CIMCDR_CE_V(v) BM_CPM_CIMCDR_CE
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#define BP_CPM_CIMCDR_BUSY 28
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#define BM_CPM_CIMCDR_BUSY 0x10000000
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#define BF_CPM_CIMCDR_BUSY(v) (((v) & 0x1) << 28)
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#define BFM_CPM_CIMCDR_BUSY(v) BM_CPM_CIMCDR_BUSY
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#define BF_CPM_CIMCDR_BUSY_V(e) BF_CPM_CIMCDR_BUSY(BV_CPM_CIMCDR_BUSY__##e)
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#define BFM_CPM_CIMCDR_BUSY_V(v) BM_CPM_CIMCDR_BUSY
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#define BP_CPM_CIMCDR_STOP 27
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#define BM_CPM_CIMCDR_STOP 0x8000000
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#define BF_CPM_CIMCDR_STOP(v) (((v) & 0x1) << 27)
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#define BFM_CPM_CIMCDR_STOP(v) BM_CPM_CIMCDR_STOP
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#define BF_CPM_CIMCDR_STOP_V(e) BF_CPM_CIMCDR_STOP(BV_CPM_CIMCDR_STOP__##e)
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#define BFM_CPM_CIMCDR_STOP_V(v) BM_CPM_CIMCDR_STOP
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#define REG_CPM_PCMCDR jz_reg(CPM_PCMCDR)
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#define JA_CPM_PCMCDR (0xb0000000 + 0x84)
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#define JT_CPM_PCMCDR JIO_32_RW
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#define JN_CPM_PCMCDR CPM_PCMCDR
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#define JI_CPM_PCMCDR
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#define BP_CPM_PCMCDR_DIV_M 13
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#define BM_CPM_PCMCDR_DIV_M 0x3fe000
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#define BF_CPM_PCMCDR_DIV_M(v) (((v) & 0x1ff) << 13)
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#define BFM_CPM_PCMCDR_DIV_M(v) BM_CPM_PCMCDR_DIV_M
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#define BF_CPM_PCMCDR_DIV_M_V(e) BF_CPM_PCMCDR_DIV_M(BV_CPM_PCMCDR_DIV_M__##e)
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#define BFM_CPM_PCMCDR_DIV_M_V(v) BM_CPM_PCMCDR_DIV_M
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#define BP_CPM_PCMCDR_DIV_N 0
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#define BM_CPM_PCMCDR_DIV_N 0x1fff
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#define BF_CPM_PCMCDR_DIV_N(v) (((v) & 0x1fff) << 0)
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#define BFM_CPM_PCMCDR_DIV_N(v) BM_CPM_PCMCDR_DIV_N
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#define BF_CPM_PCMCDR_DIV_N_V(e) BF_CPM_PCMCDR_DIV_N(BV_CPM_PCMCDR_DIV_N__##e)
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#define BFM_CPM_PCMCDR_DIV_N_V(v) BM_CPM_PCMCDR_DIV_N
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#define BP_CPM_PCMCDR_PCS 31
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#define BM_CPM_PCMCDR_PCS 0x80000000
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#define BV_CPM_PCMCDR_PCS__SCLK_A 0x0
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#define BV_CPM_PCMCDR_PCS__MPLL 0x1
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#define BF_CPM_PCMCDR_PCS(v) (((v) & 0x1) << 31)
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#define BFM_CPM_PCMCDR_PCS(v) BM_CPM_PCMCDR_PCS
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#define BF_CPM_PCMCDR_PCS_V(e) BF_CPM_PCMCDR_PCS(BV_CPM_PCMCDR_PCS__##e)
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#define BFM_CPM_PCMCDR_PCS_V(v) BM_CPM_PCMCDR_PCS
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#define BP_CPM_PCMCDR_CS 30
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#define BM_CPM_PCMCDR_CS 0x40000000
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#define BV_CPM_PCMCDR_CS__EXCLK 0x0
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#define BV_CPM_PCMCDR_CS__PLL 0x1
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#define BF_CPM_PCMCDR_CS(v) (((v) & 0x1) << 30)
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#define BFM_CPM_PCMCDR_CS(v) BM_CPM_PCMCDR_CS
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#define BF_CPM_PCMCDR_CS_V(e) BF_CPM_PCMCDR_CS(BV_CPM_PCMCDR_CS__##e)
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#define BFM_CPM_PCMCDR_CS_V(v) BM_CPM_PCMCDR_CS
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#define BP_CPM_PCMCDR_CE 29
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#define BM_CPM_PCMCDR_CE 0x20000000
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#define BF_CPM_PCMCDR_CE(v) (((v) & 0x1) << 29)
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#define BFM_CPM_PCMCDR_CE(v) BM_CPM_PCMCDR_CE
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#define BF_CPM_PCMCDR_CE_V(e) BF_CPM_PCMCDR_CE(BV_CPM_PCMCDR_CE__##e)
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#define BFM_CPM_PCMCDR_CE_V(v) BM_CPM_PCMCDR_CE
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#define REG_CPM_PCMCDR1 jz_reg(CPM_PCMCDR1)
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#define JA_CPM_PCMCDR1 (0xb0000000 + 0xe0)
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#define JT_CPM_PCMCDR1 JIO_32_RW
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#define JN_CPM_PCMCDR1 CPM_PCMCDR1
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#define JI_CPM_PCMCDR1
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#define BP_CPM_PCMCDR1_DIV_D 0
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#define BM_CPM_PCMCDR1_DIV_D 0x1fff
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#define BF_CPM_PCMCDR1_DIV_D(v) (((v) & 0x1fff) << 0)
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#define BFM_CPM_PCMCDR1_DIV_D(v) BM_CPM_PCMCDR1_DIV_D
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#define BF_CPM_PCMCDR1_DIV_D_V(e) BF_CPM_PCMCDR1_DIV_D(BV_CPM_PCMCDR1_DIV_D__##e)
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#define BFM_CPM_PCMCDR1_DIV_D_V(v) BM_CPM_PCMCDR1_DIV_D
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#define BP_CPM_PCMCDR1_N_EN 31
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#define BM_CPM_PCMCDR1_N_EN 0x80000000
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#define BF_CPM_PCMCDR1_N_EN(v) (((v) & 0x1) << 31)
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#define BFM_CPM_PCMCDR1_N_EN(v) BM_CPM_PCMCDR1_N_EN
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#define BF_CPM_PCMCDR1_N_EN_V(e) BF_CPM_PCMCDR1_N_EN(BV_CPM_PCMCDR1_N_EN__##e)
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#define BFM_CPM_PCMCDR1_N_EN_V(v) BM_CPM_PCMCDR1_N_EN
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#define BP_CPM_PCMCDR1_D_EN 30
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#define BM_CPM_PCMCDR1_D_EN 0x40000000
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#define BF_CPM_PCMCDR1_D_EN(v) (((v) & 0x1) << 30)
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#define BFM_CPM_PCMCDR1_D_EN(v) BM_CPM_PCMCDR1_D_EN
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#define BF_CPM_PCMCDR1_D_EN_V(e) BF_CPM_PCMCDR1_D_EN(BV_CPM_PCMCDR1_D_EN__##e)
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#define BFM_CPM_PCMCDR1_D_EN_V(v) BM_CPM_PCMCDR1_D_EN
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#define REG_CPM_INTR jz_reg(CPM_INTR)
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#define REG_CPM_INTR jz_reg(CPM_INTR)
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#define JA_CPM_INTR (0xb0000000 + 0xb0)
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#define JA_CPM_INTR (0xb0000000 + 0xb0)
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#define JT_CPM_INTR JIO_32_RW
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#define JT_CPM_INTR JIO_32_RW
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@ -509,6 +509,14 @@ node CPM {
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fld 3 0 CLKDIV
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fld 3 0 CLKDIV
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}
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}
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reg MACCDR 0x54 {
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bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; }
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bit 29 CE
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bit 28 BUSY
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bit 27 STOP
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fld 7 0 CLKDIV
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}
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reg I2SCDR 0x60 {
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reg I2SCDR 0x60 {
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bit 31 PCS { enum SCLK_A 0; enum MPLL 1; }
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bit 31 PCS { enum SCLK_A 0; enum MPLL 1; }
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bit 30 CS { enum EXCLK 0; enum PLL 1; }
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bit 30 CS { enum EXCLK 0; enum PLL 1; }
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@ -564,6 +572,35 @@ node CPM {
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fld 7 0 CLKDIV
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fld 7 0 CLKDIV
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}
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}
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reg CIMCDR 0x7c {
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bit 31 CLKSRC { enum SCLK_A 1; enum MPLL 1 }
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bit 29 CE
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bit 28 BUSY
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bit 27 STOP
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fld 7 0 CLKDIV
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}
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reg PCMCDR 0x84 {
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# Hardware manual says this is the correct definition, but based
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# on Ingenic's sources, the format is actually like I2SCDR.
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#fld 31 30 CLKSRC { enum SCLK_A 0; enum EXCLK 1; enum MPLL 2 }
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# Note this format hasn't been verified to work because none of
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# the X1000 targets are using a PCM interface.
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bit 31 PCS { enum SCLK_A 0; enum MPLL 1; }
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bit 30 CS { enum EXCLK 0; enum PLL 1; }
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bit 29 CE
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fld 21 13 DIV_M
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fld 12 0 DIV_N
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}
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reg PCMCDR1 0xe0 {
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bit 31 N_EN
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bit 30 D_EN
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fld 12 0 DIV_D
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}
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reg INTR 0xb0 {
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reg INTR 0xb0 {
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bit 1 VBUS
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bit 1 VBUS
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bit 0 ADEV
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bit 0 ADEV
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