mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-08 20:55:17 -05:00
iPod Classic: rework on external interrupts
Change-Id: I5be450adeb12b16070d9bfa31503e2ef350b2981
This commit is contained in:
Cástor Muñoz
parent
3f17745930
commit
88caf222ed
3 changed files with 180 additions and 172 deletions
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@ -23,11 +23,30 @@
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#include "config.h"
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#include "system.h"
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#include "gpio-s5l8702.h"
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#include "panic.h"
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#include "gpio-s5l8702.h"
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int rec_hw_ver;
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static uint32_t gpio_data[] =
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{
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0x5322222F, 0xEEEEEE00, 0x2332EEEE, 0x3333E222,
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0x33333333, 0x33333333, 0x3F000E33, 0xEEEEEEEE,
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0xEEEEEEEE, 0xEEEEEEEE, 0xE0EEEEEE, 0xEE00EE0E,
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0xEEEE0EEE, 0xEEEEEEEE, 0xEE2222EE, 0xEEEE0EEE
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};
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void INIT_ATTR gpio_preinit(void)
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{
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for (int i = 0; i < 16; i++) {
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PCON(i) = gpio_data[i];
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PUNB(i) = 0;
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PUNC(i) = 0;
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}
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}
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void INIT_ATTR gpio_init(void)
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{
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/* Capture hardware versions:
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@ -44,9 +63,8 @@ void INIT_ATTR gpio_init(void)
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*/
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GPIOCMD = 0xe0700;
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rec_hw_ver = (PDAT(14) & (1 << 7)) ? 0 : 1;
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GPIOCMD = 0xe070e; /* restore default configuration */
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/* default GPIO configuration */
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GPIOCMD = 0xe070e;
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if (rec_hw_ver == 0) {
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GPIOCMD = 0xe060e;
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}
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@ -56,31 +74,9 @@ void INIT_ATTR gpio_init(void)
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GPIOCMD = 0xe0600;
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PUNB(14) |= (1 << 6);
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}
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/* TODO: initialize GPIO ports for minimum power consumption */
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}
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/*
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* XXX: disabled, not used and never tested!
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*/
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#if 0
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/* handlers list */
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#define GPIOIC_MAX_HANDLERS 2
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#define FLAG_TYPE_LEVEL (1 << 0)
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#define FLAG_AUTOFLIP (1 << 1)
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struct gpio_handler {
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int gpio_n;
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void (*isr)(void);
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int flags;
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};
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static struct gpio_handler l_handlers[GPIOIC_MAX_HANDLERS] IDATA_ATTR;
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static int n_handlers = 0;
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/* API */
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uint32_t gpio_group_get(int group)
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{
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uint32_t pcon = PCON(group);
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@ -103,131 +99,128 @@ void gpio_group_set(int group, uint32_t mask, uint32_t cfg)
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{
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PCON(group) = (PCON(group) & ~mask) | (cfg & mask);
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}
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#endif
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void gpio_int_register(int gpio_n, void *isr, int type, int level, int autoflip)
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/*
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* eINT API
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*/
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#ifndef EINT_MAX_HANDLERS
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#define EINT_MAX_HANDLERS 1
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#endif
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static struct eint_handler* l_handlers[EINT_MAX_HANDLERS] IDATA_ATTR;
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void INIT_ATTR eint_init(void)
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{
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if (n_handlers >= GPIOIC_MAX_HANDLERS)
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panicf("gpio_int_register(): too many handlers!");
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int group = IC_GROUP(gpio_n);
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int index = IC_IDX(gpio_n);
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int flags = disable_irq_save();
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/* fill handler struct */
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struct gpio_handler *handler = &l_handlers[n_handlers++];
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handler->gpio_n = gpio_n;
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handler->isr = isr;
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handler->flags = (type ? FLAG_TYPE_LEVEL : 0)
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| (autoflip ? FLAG_AUTOFLIP : 0);
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/* configure */
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GPIOIC_INTTYPE(group) |=
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(type ? GPIOIC_INTTYPE_LEVEL : GPIOIC_INTTYPE_EDGE) << index;
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GPIOIC_INTLEVEL(group) |=
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(level ? GPIOIC_INTLEVEL_HIGH : GPIOIC_INTLEVEL_LOW) << index;
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restore_irq(flags);
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/* XXX: valid only for gpio_n = 0..127 (IRQ_EXT0..IRQ_EXT3) */
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VIC0INTENABLE = 1 << (IRQ_EXT0 + (gpio_n >> 5));
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/* disable external interrupts */
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for (int i = 0; i < EIC_N_GROUPS; i++)
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EIC_INTEN(i) = 0;
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}
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void gpio_int_enable(int gpio_n)
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{
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int group = IC_GROUP(gpio_n);
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uint32_t bit_mask = 1 << IC_IDX(gpio_n);
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int flags = disable_irq_save();
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GPIOIC_INTSTAT(group) = bit_mask; /* clear */
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GPIOIC_INTEN(group) |= bit_mask; /* enable */
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restore_irq(flags);
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}
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void gpio_int_disable(int gpio_n)
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{
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int group = IC_GROUP(gpio_n);
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uint32_t bit_mask = 1 << IC_IDX(gpio_n);
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int flags = disable_irq_save();
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GPIOIC_INTEN(group) &= ~bit_mask; /* disable */
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GPIOIC_INTSTAT(group) = bit_mask; /* clear */
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restore_irq(flags);
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}
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/* ISR */
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void ICODE_ATTR gpio_handler(int group)
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void eint_register(struct eint_handler *h)
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{
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int i;
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struct gpio_handler *handler;
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uint32_t ints, bit_mask;
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int flags = disable_irq_save();
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ints = GPIOIC_INTSTAT(group) & GPIOIC_INTEN(group);
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for (i = 0; i < EINT_MAX_HANDLERS; i++) {
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if (!l_handlers[i]) {
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int group = EIC_GROUP(h->gpio_n);
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int index = EIC_INDEX(h->gpio_n);
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for (i = 0; i < n_handlers; i++) {
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handler = &l_handlers[i];
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EIC_INTTYPE(group) |= (h->type << index);
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EIC_INTLEVEL(group) |= (h->level << index);
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EIC_INTSTAT(group) = (1 << index); /* clear */
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EIC_INTEN(group) |= (1 << index); /* enable */
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if (IC_GROUP(handler->gpio_n) != group)
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/* XXX: valid only for gpio_n = 0..127 (IRQ_EXT0..IRQ_EXT3) */
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VIC0INTENABLE = 1 << (IRQ_EXT0 + (h->gpio_n >> 5));
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l_handlers[i] = h;
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break;
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}
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}
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restore_irq(flags);
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if (i == EINT_MAX_HANDLERS)
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panicf("%s(): too many handlers!", __func__);
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}
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void eint_unregister(struct eint_handler *h)
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{
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int flags = disable_irq_save();
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for (int i = 0; i < EINT_MAX_HANDLERS; i++) {
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if (l_handlers[i] == h) {
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int group = EIC_GROUP(h->gpio_n);
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int index = EIC_INDEX(h->gpio_n);
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EIC_INTEN(group) &= ~(1 << index); /* disable */
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/* XXX: valid only for gpio_n = 0..127 (IRQ_EXT0..IRQ_EXT3) */
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if (EIC_INTEN(group) == 0)
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VIC0INTENCLEAR = 1 << (IRQ_EXT0 + (h->gpio_n >> 5));
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l_handlers[i] = NULL;
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break;
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}
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}
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restore_irq(flags);
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}
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/* ISR */
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void ICODE_ATTR eint_handler(int group)
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{
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int i;
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uint32_t ints;
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ints = EIC_INTSTAT(group) & EIC_INTEN(group);
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for (i = 0; i < EINT_MAX_HANDLERS; i++) {
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struct eint_handler *h = l_handlers[i];
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if (!h || (EIC_GROUP(h->gpio_n) != group))
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continue;
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bit_mask = 1 << IC_IDX(handler->gpio_n);
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uint32_t bit = 1 << EIC_INDEX(h->gpio_n);
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if (ints & bit_mask) {
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if ((handler->flags & FLAG_TYPE_LEVEL) == 0)
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GPIOIC_INTSTAT(group) = bit_mask; /* clear */
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if (ints & bit) {
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/* Clear INTTYPE_EDGE interrupt, to clear INTTYPE_LEVEL
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interrupts the source (line level) must be "cleared" */
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if (h->type == EIC_INTTYPE_EDGE)
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EIC_INTSTAT(group) = bit; /* clear */
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if (handler->flags & FLAG_AUTOFLIP)
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GPIOIC_INTLEVEL(group) ^= bit_mask; /* swap level */
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if (h->autoflip)
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EIC_INTLEVEL(group) ^= bit; /* swap level */
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if (handler->isr)
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handler->isr(); /* exec GPIO handler */
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GPIOIC_INTSTAT(group) = bit_mask; /* clear */
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if (h->isr)
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h->isr(h); /* exec GPIO handler */
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}
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}
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}
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void ICODE_ATTR INT_EXT0(void)
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{
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gpio_handler(6);
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eint_handler(6);
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}
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void ICODE_ATTR INT_EXT1(void)
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{
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gpio_handler(5);
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eint_handler(5);
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}
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void ICODE_ATTR INT_EXT2(void)
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{
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gpio_handler(4);
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eint_handler(4);
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}
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void ICODE_ATTR INT_EXT3(void)
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{
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gpio_handler(3);
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eint_handler(3);
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}
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void ICODE_ATTR INT_EXT6(void)
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{
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gpio_handler(0);
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}
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#endif
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static uint32_t gpio_data[16] =
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{
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0x5322222F, 0xEEEEEE00, 0x2332EEEE, 0x3333E222,
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0x33333333, 0x33333333, 0x3F000E33, 0xEEEEEEEE,
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0xEEEEEEEE, 0xEEEEEEEE, 0xE0EEEEEE, 0xEE00EE0E,
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0xEEEE0EEE, 0xEEEEEEEE, 0xEE2222EE, 0xEEEE0EEE
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};
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void gpio_preinit(void)
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{
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for (int i = 0; i < 16; i++) {
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PCON(i) = gpio_data[i];
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PUNB(i) = 0;
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PUNC(i) = 0;
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}
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eint_handler(0);
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}
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@ -23,6 +23,69 @@
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#define __GPIO_S5L8702_H__
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#include <stdint.h>
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#define REG32_PTR_T volatile uint32_t *
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/*
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* s5l8702 External (GPIO) Interrupt Controller
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*
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* 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
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* to groups 6..3 in reverse order.
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* On group 3, last four bits are dissbled (GPIO 124..127).
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* All bits in groups 1 and 2 are disabled (not used).
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* On group 0, all bits are masked except bits 0 and 2:
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* bit 0: if unmasked, EINT6 is generated when ALVTCNT
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* reachs ALVTEND.
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* bit 2: if unmasked, EINT6 is generated when USB cable
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* is plugged and/or(TBC) unplugged.
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*
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* IC_GROUP0..6 are connected to EINT6..0 of the VIC.
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*/
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#define EIC_N_GROUPS 7
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/* get EIC group and bit for a given GPIO port */
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#define EIC_GROUP(n) (6 - (n >> 5))
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#define EIC_INDEX(n) ((0x18 - (n & 0x18)) | (n & 0x7))
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/* SoC EINTs uses these 'gpio' numbers */
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#define GPIO_EINT_USB 0xd8
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#define GPIO_EINT_ALIVE 0xda
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/* probably a part of the system controller */
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#define EIC_BASE 0x39a00000
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#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
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#define EIC_INTSTAT(g) (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
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#define EIC_INTEN(g) (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
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#define EIC_INTTYPE(g) (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
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#define EIC_INTLEVEL_LOW 0
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#define EIC_INTLEVEL_HIGH 1
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#define EIC_INTTYPE_EDGE 0
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#define EIC_INTTYPE_LEVEL 1
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struct eint_handler {
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uint8_t gpio_n;
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uint8_t type; /* EIC_INTTYPE_ */
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uint8_t level; /* EIC_INTLEVEL_ */
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uint8_t autoflip;
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void (*isr)(struct eint_handler*);
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};
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void eint_register(struct eint_handler *h);
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void eint_unregister(struct eint_handler *h);
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void eint_init(void);
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void gpio_init(void);
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/* get/set configuration for GPIO groups (0..15) */
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uint32_t gpio_group_get(int group);
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void gpio_group_set(int group, uint32_t mask, uint32_t cfg);
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void gpio_preinit(void);
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/* This is very preliminary work in progress, ATM this region is called
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* system 'alive' because it seems there are similiarities when mixing
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* concepts from:
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@ -47,9 +110,6 @@
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* +-->| 1/UNKDIV |--> Unknown
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* |___________|
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*/
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#define REG32_PTR_T volatile uint32_t *
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#define SYSALV_BASE 0x39a00000
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#define ALVCON (*((REG32_PTR_T)(SYSALV_BASE + 0x0)))
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@ -81,67 +141,21 @@
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/*
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* System Alive timer
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*/
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/* ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
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*
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* ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
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* is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
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* and ALVUNK4[0] are set, optionally an interrupt is generated (see
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* GPIO_IC below). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
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* and ALVUNK4[0] and initializes ALVTCNT to zero.
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*/
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#define ALVTCOM (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
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#define ALVTCOM (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
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#define ALVTCOM_RUN_BIT (1 << 0) /* 0 -> Stop, 1 -> Start */
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#define ALVTCOM_RST_BIT (1 << 1) /* 1 -> Reset */
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#define ALVTEND (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
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#define ALVTDIV (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
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#define ALVTEND (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
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#define ALVTDIV (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
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#define ALVTCNT (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
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#define ALVTSTAT (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
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/*
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* s5l8702 GPIO Interrupt Controller
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*/
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#define GPIOIC_BASE 0x39a00000 /* probably a part of the system controller */
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#define GPIOIC_INTLEVEL(g) (*((REG32_PTR_T)(GPIOIC_BASE + 0x80 + 4*(g))))
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#define GPIOIC_INTSTAT(g) (*((REG32_PTR_T)(GPIOIC_BASE + 0xA0 + 4*(g))))
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#define GPIOIC_INTEN(g) (*((REG32_PTR_T)(GPIOIC_BASE + 0xC0 + 4*(g))))
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#define GPIOIC_INTTYPE(g) (*((REG32_PTR_T)(GPIOIC_BASE + 0xE0 + 4*(g))))
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#define GPIOIC_INTLEVEL_LOW 0
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#define GPIOIC_INTLEVEL_HIGH 1
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#define GPIOIC_INTTYPE_EDGE 0
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#define GPIOIC_INTTYPE_LEVEL 1
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/* 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
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* to groups 6..3 in reverse order.
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* On group 3, last four bits are dissbled (GPIO 124..127).
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* All bits in groups 1 and 2 are disabled (not used).
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* On group 0, all bits are masked except bits 0 and 2:
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* bit 0: if unmasked, EINT6 is generated when ALVTCNT
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* reachs ALVTEND.
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* bit 2: if unmasked, EINT6 is generated when USB cable
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* is plugged and/or(TBC) unplugged.
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*
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* IC_GROUP0..6 are connected to EINT6..0 of the VIC.
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*/
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/* get GPIOIC group and bit for a given GPIO port */
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#define IC_GROUP(n) (6 - (n >> 5))
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#define IC_IDX(n) ((0x18 - (n & 0x18)) | (n & 0x7))
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void gpio_init(void);
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void gpio_int_register(int gpio_n, void *isr,
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int type, int level, int autoflip);
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void gpio_int_enable(int gpio_n);
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void gpio_int_disable(int gpio_n);
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/* get/set configuration for GPIO groups (0..15) */
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uint32_t gpio_group_get(int group);
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void gpio_group_set(int group, uint32_t mask, uint32_t cfg);
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void gpio_preinit(void);
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#define ALVTCNT (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
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#define ALVTSTAT (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
|
||||
|
||||
#endif /* __GPIO_S5L8702_H__ */
|
||||
|
|
|
|||
|
|
@ -206,6 +206,7 @@ void system_init(void)
|
|||
pmu_preinit();
|
||||
#endif
|
||||
gpio_init();
|
||||
eint_init();
|
||||
pmu_init();
|
||||
dma_init();
|
||||
#ifdef HAVE_SERIAL
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue