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ipod6g: bootloader v1
- dual boot - USB mode - battery trap Change-Id: I8586cfeb21ee63f45ab965430725225fdfc4212d
This commit is contained in:
Cástor Muñoz
parent
0d0b163dd1
commit
882921efb6
7 changed files with 582 additions and 32 deletions
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@ -1,5 +1,6 @@
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#define ASM
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#include "config.h"
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#include "cpu.h"
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ENTRY(start)
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#ifdef ROCKBOX_LITTLE_ENDIAN
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@ -10,13 +11,11 @@ OUTPUT_FORMAT(elf32-bigarm)
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OUTPUT_ARCH(arm)
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STARTUP(target/arm/s5l8702/crt0.o)
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#define MAX_LOADSIZE 8M /* reserved for loading Rockbox binary */
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#ifdef IPOD_NANO2G
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#define DRAMORIG 0x08000000 + ((MEMORYSIZE - 1) * 0x100000)
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#define DRAMSIZE 0x00100000
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#else
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#define DRAMORIG 0x08000000
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#define DRAMSIZE (DRAM_SIZE - TTB_SIZE)
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#endif
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#define IRAMORIG 0x22000000
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#define IRAMSIZE 256K
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@ -26,17 +25,47 @@ MEMORY
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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}
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#define LOAD_AREA IRAM
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#define VECT_AREA IRAM
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#define BSS_AREA DRAM
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#elif defined(IPOD_6G)
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MEMORY
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{
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DRAM : ORIGIN = DRAM_ORIG, LENGTH = DRAM_SIZE
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IRAM : ORIGIN = IRAM_ORIG, LENGTH = IRAM_SIZE
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/* s5l8702 maps address 0 to ROM, IRAM or DRAM */
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VECT_AREA : ORIGIN = 0, LENGTH = 1K
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/* IRAM region where loaded IM3 body will be moved and executed,
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preserving the loaded IM3 header (0x800 bytes) at IRAM1_ORIG */
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MOVE_AREA : ORIGIN = IRAM1_ORIG + 0x800,
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LENGTH = IRAM1_SIZE - 0x800
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/* DRAM region for BSS */
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BSS_AREA : ORIGIN = DRAM_ORIG + MAX_LOADSIZE,
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LENGTH = DRAM_SIZE - MAX_LOADSIZE - TTB_SIZE
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}
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#define LOAD_AREA MOVE_AREA
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#else
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#error No target defined!
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#endif
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SECTIONS
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{
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_dfuloadaddr = IRAM0_ORIG ;
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_movestart = LOADADDR(.text) ;
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_moveend = LOADADDR(.data) + SIZEOF(.data) ;
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#ifdef NEEDS_INTVECT_COPYING
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.intvect : {
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_intvectstart = . ;
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*(.intvect)
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_intvectend = _newstart ;
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} >IRAM AT> LOAD_AREA
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_intvectend = _newstart ;
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} >VECT_AREA AT> LOAD_AREA
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_intvectcopy = LOADADDR(.intvect) ;
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#endif
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@ -61,10 +90,9 @@ SECTIONS
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*(.idata*)
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*(.data*)
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*(.ncdata*);
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. = ALIGN(0x4);
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. = ALIGN(0x20); /* align move size */
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_dataend = . ;
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} > IRAM AT> LOAD_AREA
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_datacopy = LOADADDR(.data) ;
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} > LOAD_AREA
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.stack (NOLOAD) :
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{
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@ -80,7 +108,7 @@ SECTIONS
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_fiqstackbegin = .;
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. += 0x400;
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_fiqstackend = .;
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} > IRAM
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} > LOAD_AREA
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.bss (NOLOAD) : {
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_edata = .;
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@ -88,7 +116,7 @@ SECTIONS
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*(.ibss*);
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*(.ncbss*);
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*(COMMON);
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. = ALIGN(0x4);
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. = ALIGN(0x20); /* align bzero size */
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_end = .;
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} > IRAM
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} > BSS_AREA
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}
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@ -46,17 +46,20 @@ newstart2:
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifdef BOOTLOADER
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/* Relocate ourself to IRAM - we have been loaded to DRAM */
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mov r0, #0x08000000 /* source (DRAM) */
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mov r1, #0x22000000 /* dest (IRAM) */
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ldr r2, =_dataend
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/* Relocate ourself to IRAM1 - we have been loaded to IRAM0 */
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ldr r0, =_dfuloadaddr
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ldr r1, =_movestart
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ldr r2, =_moveend
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1:
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cmp r2, r1
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ldrhi r3, [r0], #4
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strhi r3, [r1], #4
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bhi 1b
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ldmia r0!, {r3-r10}
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stmia r1!, {r3-r10}
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cmp r1, r2
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blt 1b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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.section .init.text,"ax",%progbits
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.global start_loc
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start_loc:
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#endif
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@ -66,11 +69,11 @@ start_loc:
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mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
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.cleancache:
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mrc p15, 0, r15,c7,c10,3
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mrc p15, 0, r15, c7, c10, 3 /* test and clean dcache */
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bne .cleancache
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mov r0, #0
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mcr p15, 0, r0,c7,c10,4
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mcr p15, 0, r0,c7,c5,0
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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/* reset VIC controller */
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ldr r1, =0x38e00000
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@ -86,7 +89,15 @@ start_loc:
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str r0, [r1,#0x14]
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str r0, [r2,#0x14]
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#if !defined(BOOTLOADER)
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#if defined(BOOTLOADER)
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/* SPI speed is limited when icache is not active. Not worth
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* activating dcache, it is almost useless on pre-init stage
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* and the TLB needs 16Kb in detriment of the bootloader.
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*/
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #1<<12 /* enable icache */
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mcr p15, 0, r0, c1, c0, 0
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#else
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bl memory_init
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/* Copy interrupt vectors to iram */
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@ -98,7 +109,6 @@ start_loc:
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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#endif
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/* Initialise bss section to zero */
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ldr r2, =_edata
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@ -109,7 +119,6 @@ start_loc:
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strhi r4, [r2], #4
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bhi 1b
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#ifndef BOOTLOADER
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/* Copy icode and data to ram */
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ldr r2, =_iramstart
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ldr r3, =_iramend
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@ -159,3 +168,33 @@ start_loc:
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bhi 1b
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b main
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#ifdef BOOTLOADER
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/* Initialise bss section to zero */
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.global bss_init
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.type bss_init, %function
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bss_init:
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stmfd sp!, {r4-r9,lr}
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ldr r0, =_edata
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ldr r1, =_end
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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b 2f
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.align 5 /* cache line size */
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1:
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stmia r0!, {r2-r9}
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2:
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cmp r0, r1
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blt 1b
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ldmpc regs=r4-r9
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.ltorg
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#endif
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