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Resurrect the ARM7 16-bit packed vector addition/subtraction for ARMv5, giving a nice speedup for the higher compression levels (tested on Cowon D2).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19260 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
d158a6d0c9
commit
88270f7622
1 changed files with 164 additions and 76 deletions
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@ -24,92 +24,180 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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*/
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/* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned, otherwise it will result either in a data abort, or
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* incorrect results (if ARM aligncheck is disabled). */
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static inline void vector_add(int16_t* v1, int16_t* v2)
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{
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#if ORDER > 32
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int order = (ORDER >> 5);
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while (order--)
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#endif
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{
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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#if ORDER > 16
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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*v1++ += *v2++;
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int cnt = ORDER>>4;
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#endif
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}
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#define ADDHALFREGS(sum, s1) /* Adds register */ \
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"mov " #s1 ", " #s1 ", ror #16 \n" /* halves straight. */ \
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"add r8 , " #s1 ", " #sum ", lsl #16 \n" /* Clobbers 's1' */ \
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"add " #sum ", " #s1 ", " #sum ", lsr #16 \n" /* and r8. */ \
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"mov " #sum ", " #sum ", lsl #16 \n" \
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"orr " #sum ", " #sum ", r8 , lsr #16 \n"
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#define ADDHALFXREGS(sum, s1, s2) /* Adds register */ \
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"add " #s1 ", " #s1 ", " #sum ", lsl #16 \n" /* halves across. */ \
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"add " #sum ", " #s2 ", " #sum ", lsr #16 \n" /* Clobbers 's1'. */ \
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"mov " #sum ", " #sum ", lsl #16 \n" \
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"orr " #sum ", " #sum ", " #s1 ", lsr #16 \n"
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asm volatile (
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"tst %[v2], #2 \n"
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"beq 20f \n"
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"10: \n"
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"ldrh r4, [%[v2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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ADDHALFXREGS(r0, r4, r5)
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ADDHALFXREGS(r1, r5, r6)
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ADDHALFXREGS(r2, r6, r7)
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ADDHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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"mov r4, r8 \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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ADDHALFXREGS(r0, r4, r5)
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ADDHALFXREGS(r1, r5, r6)
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ADDHALFXREGS(r2, r6, r7)
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ADDHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"mov r4, r8 \n"
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"b 99f \n"
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"20: \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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ADDHALFREGS(r0, r4)
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ADDHALFREGS(r1, r5)
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ADDHALFREGS(r2, r6)
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ADDHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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ADDHALFREGS(r0, r4)
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ADDHALFREGS(r1, r5)
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ADDHALFREGS(r2, r6)
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ADDHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"99: \n"
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: /* outputs */
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#if ORDER > 16
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[v2] "+r"(v2)
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: /* inputs */
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: /* clobbers */
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"r0", "r1", "r2", "r3", "r4",
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"r5", "r6", "r7", "r8", "memory"
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);
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}
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/* This version fetches data as 32 bit words, and *requires* v1 to be
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* 32 bit aligned, otherwise it will result either in a data abort, or
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* incorrect results (if ARM aligncheck is disabled). */
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static inline void vector_sub(int16_t* v1, int16_t* v2)
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{
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#if ORDER > 32
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int order = (ORDER >> 5);
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while (order--)
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#endif
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{
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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#if ORDER > 16
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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*v1++ -= *v2++;
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int cnt = ORDER>>4;
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#endif
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}
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#define SUBHALFREGS(dif, s1) /* Subtracts register */ \
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"sub r8 , " #dif ", " #s1 "\n" /* halves straight. */ \
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"and r8 , r8 , r9 \n" /* Needs r9 = 0x0000ffff, */ \
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"mov " #dif ", " #dif ", lsr #16 \n" /* clobbers r8. */ \
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"sub " #dif ", " #dif ", " #s1 ", lsr #16 \n" \
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"orr " #dif ", r8 , " #dif ", lsl #16 \n"
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#define SUBHALFXREGS(dif, s1, s2) /* Subtracts register */ \
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"sub " #s1 ", " #dif ", " #s1 ", lsr #16 \n" /* halves across. */ \
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"and " #s1 ", " #s1 ", r9 \n" /* Needs r9 = 0x0000ffff, */ \
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"rsb " #dif ", " #s2 ", " #dif ", lsr #16 \n" /* clobbers 's1'. */ \
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"orr " #dif ", " #s1 ", " #dif ", lsl #16 \n"
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asm volatile (
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"mov r9, #0xff \n"
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"orr r9, r9, #0xff00 \n"
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"tst %[v2], #2 \n"
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"beq 20f \n"
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"10: \n"
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"ldrh r4, [%[v2]], #2 \n"
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"mov r4, r4, lsl #16 \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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SUBHALFXREGS(r0, r4, r5)
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SUBHALFXREGS(r1, r5, r6)
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SUBHALFXREGS(r2, r6, r7)
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SUBHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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"mov r4, r8 \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r5-r8} \n"
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SUBHALFXREGS(r0, r4, r5)
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SUBHALFXREGS(r1, r5, r6)
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SUBHALFXREGS(r2, r6, r7)
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SUBHALFXREGS(r3, r7, r8)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"mov r4, r8 \n"
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"b 99f \n"
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"20: \n"
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"1: \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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SUBHALFREGS(r0, r4)
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SUBHALFREGS(r1, r5)
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SUBHALFREGS(r2, r6)
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SUBHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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"ldmia %[v1], {r0-r3} \n"
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"ldmia %[v2]!, {r4-r7} \n"
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SUBHALFREGS(r0, r4)
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SUBHALFREGS(r1, r5)
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SUBHALFREGS(r2, r6)
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SUBHALFREGS(r3, r7)
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"stmia %[v1]!, {r0-r3} \n"
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#if ORDER > 16
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"subs %[cnt], %[cnt], #1 \n"
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"bne 1b \n"
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#endif
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"99: \n"
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: /* outputs */
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#if ORDER > 16
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[v2] "+r"(v2)
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: /* inputs */
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: /* clobbers */
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"r0", "r1", "r2", "r3", "r4", "r5",
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"r6", "r7", "r8", "r9", "memory"
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);
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}
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/* This version fetches data as 32 bit words, and *requires* v1 to be
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