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Using ARM Unified Assembler Language

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Change-Id: Iae32a8ba8eff6087330e458fafc912a12fee4509
This commit is contained in:
Chris Chua 2023-03-19 06:22:08 +11:00 • committed by Aidan MacDonald
parent a64cad847e
commit 86429dbf1e
23 changed files with 139 additions and 127 deletions
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2
lib/arm_support/support-arm.S
View file

@ -227,7 +227,7 @@
/* Test whether divisor is 2^N */
cmp \inv, #1<<31
/* Load approximate reciprocal */
ldrhib \inv, [\neg, #.L_udiv_est_table-.-64]
ldrbhi \inv, [\neg, #.L_udiv_est_table-.-64]
bls 20f
subs \bits, \bits, #7
rsb \neg, \divisor, #0

2
lib/rbcodec/codecs/demac/libdemac/udiv32_arm.S
View file

@ -225,7 +225,7 @@ udiv32_arm:
mov \inv, \divisor, lsl \bits
add \neg, pc, \inv, lsr #25
cmp \inv, #1<<31
ldrhib \inv, [\neg, #.L_udiv_est_table-.-64]
ldrbhi \inv, [\neg, #.L_udiv_est_table-.-64]
bls 20f
subs \bits, \bits, #7
rsb \neg, \divisor, #0

23
lib/rbcodec/codecs/demac/libdemac/vector_math16_armv6.h
View file

@ -45,6 +45,7 @@ static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
#endif
asm volatile (
".syntax unified \n"
#if ORDER > 32
"mov %[res], #0 \n"
#endif
@ -117,7 +118,7 @@ static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
"smladx %[res], r1, r2, %[res] \n"
#if ORDER > 32
"subs %[cnt], %[cnt], #1 \n"
"ldmneia %[f2]!, {r2,r4} \n"
"ldmiane %[f2]!, {r2,r4} \n"
"sadd16 r0, r0, r7 \n"
"sadd16 r1, r1, r5 \n"
"strd r0, [%[v1]], #8 \n"
@ -172,8 +173,8 @@ static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
"smlad %[res], r3, r5, %[res] \n"
#if ORDER > 32
"subs %[cnt], %[cnt], #1 \n"
"ldrned r4, [%[f2]], #8 \n"
"ldrned r0, [%[v1], #8] \n"
"ldrdne r4, [%[f2]], #8 \n"
"ldrdne r0, [%[v1], #8] \n"
"sadd16 r2, r2, r6 \n"
"sadd16 r3, r3, r7 \n"
"strd r2, [%[v1]], #8 \n"
@ -214,6 +215,7 @@ static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
#endif
asm volatile (
".syntax unified \n"
#if ORDER > 32
"mov %[res], #0 \n"
#endif
@ -286,7 +288,7 @@ static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
"smladx %[res], r1, r2, %[res] \n"
#if ORDER > 32
"subs %[cnt], %[cnt], #1 \n"
"ldmneia %[f2]!, {r2,r4} \n"
"ldmiane %[f2]!, {r2,r4} \n"
"ssub16 r0, r0, r7 \n"
"ssub16 r1, r1, r5 \n"
"strd r0, [%[v1]], #8 \n"
@ -341,8 +343,8 @@ static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
"smlad %[res], r3, r5, %[res] \n"
#if ORDER > 32
"subs %[cnt], %[cnt], #1 \n"
"ldrned r4, [%[f2]], #8 \n"
"ldrned r0, [%[v1], #8] \n"
"ldrdne r4, [%[f2]], #8 \n"
"ldrdne r0, [%[v1], #8] \n"
"ssub16 r2, r2, r6 \n"
"ssub16 r3, r3, r7 \n"
"strd r2, [%[v1]], #8 \n"
@ -381,6 +383,7 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
#endif
asm volatile (
".syntax unified \n"
#if ORDER > 32
"mov %[res], #0 \n"
#endif
@ -421,10 +424,10 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
"pkhtb r1, r7, r4 \n"
#if ORDER > 32
"subs %[cnt], %[cnt], #1 \n"
"ldrned r6, [%[v2]], #8 \n"
"ldrdne r6, [%[v2]], #8 \n"
"smladx %[res], r2, r1, %[res] \n"
"pkhtb r2, r4, r5 \n"
"ldrned r0, [%[v1]], #8 \n"
"ldrdne r0, [%[v1]], #8 \n"
"smladx %[res], r3, r2, %[res] \n"
"bne 1b \n"
#else
@ -461,9 +464,9 @@ static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
"ldrd r4, [%[v2]], #8 \n"
"smlad %[res], r1, r6, %[res] \n"
"subs %[cnt], %[cnt], #1 \n"
"ldrned r0, [%[v1]], #8 \n"
"ldrdne r0, [%[v1]], #8 \n"
"smlad %[res], r2, r7, %[res] \n"
"ldrned r6, [%[v2]], #8 \n"
"ldrdne r6, [%[v2]], #8 \n"
"smlad %[res], r3, r4, %[res] \n"
"bne 1b \n"
#else

4
lib/rbcodec/codecs/libtta/filter_arm.S
View file

@ -165,8 +165,8 @@ hybrid_filter:
sub r10, r11, r10
@ set to the memory: *pA, *(pA-1), *(pA-2), *(pA-3), *pM, *(pM-1), *(pM-2), *(pM-3)
stmneda r2, {r10, r11, r12, lr}
stmneda r3, {r5, r6, r7, r8}
stmdane r2, {r10, r11, r12, lr}
stmdane r3, {r5, r6, r7, r8}
ldmpc cond=ne regs=r4-r12 @ hybrid_filter end (when fs->index != 0)
.hf_memshl:

6
lib/rbcodec/dsp/dsp_arm.S
View file

@ -323,7 +323,7 @@ resample_hermite:
add r6, r6, r0, lsl #2 @ r6 = &s[pos]
cmp r0, #3 @ pos >= 3? history not needed
ldmgedb r6, { r1-r3 } @ x3..x1 = s[pos-3]..s[pos-1]
ldmdbge r6, { r1-r3 } @ x3..x1 = s[pos-3]..s[pos-1]
bge .hrs_loadhist_done @
add r10, r0, r0, lsl #1 @ branch pc + pos*12
add pc, pc, r10, lsl #2 @
@ -496,7 +496,7 @@ resample_hermite:
ldmfd sp!, { r10, r12 } @ recover ch, h
subs r10, r10, #1 @ --ch
stmia r12!, { r1-r3 } @ h[0..2] = x3..x1
ldmgtia sp, { r0-r2 } @ load data, src, dst
ldmiagt sp, { r0-r2 } @ load data, src, dst
bgt .hrs_channel_loop
ldmfd sp!, { r1-r3 } @ pop data, src, dst
@ -614,7 +614,7 @@ filter_process:
ldr r0, [sp] @ r0 = history[channels-ch-1]
subs r3, r3, #1 @ all channels processed?
stmia r0!, { r9-r12 } @ save back history, history++
ldmhsib sp, { r1-r2 } @ r1 = buf, r2 = count
ldmibhs sp, { r1-r2 } @ r1 = buf, r2 = count
strhs r3, [sp, #12] @ store ch
strhs r0, [sp] @ store history[channels-ch-1]
bhs .fp_channelloop

5
lib/rbcodec/dsp/dsp_arm_v6.S
View file

@ -18,6 +18,7 @@
* KIND, either express or implied.
*
****************************************************************************/
#include "rbcodecconfig.h"
/****************************************************************************
* void sample_output_mono(struct sample_io_data *this,
@ -56,7 +57,7 @@ sample_output_mono:
stmia r3!, { r12, r14 } @ store So0, So1
bgt 1b @
@
ldmltfd sp!, { r4, pc } @ if count was even, we're done
ldmfdlt sp!, { r4, pc } @ if count was even, we're done
@
2: @
ldr r12, [r2] @ round, scale, saturate
@ -113,7 +114,7 @@ sample_output_stereo:
stmia r3!, { r6, r7 } @ store So0, So1
bgt 1b @
@
ldmltfd sp!, { r4-r7, pc } @ if count was even, we're done
ldmfdlt sp!, { r4-r7, pc } @ if count was even, we're done
@
2: @
ldr r6, [r2] @ r6 = Li

4
lib/unwarminder/safe_read.S
View file

@ -45,7 +45,7 @@ safe_read8_faulty_addr:
@ if(value != NULL)
cmp r1, #0
@ *value = r0
strneb r0, [r1]
strbne r0, [r1]
@ return true;
mov r0, #1
bx lr
@ -72,7 +72,7 @@ safe_read16_faulty_addr:
@ if(value != NULL)
cmp r1, #0
@ *value = r0
strneh r0, [r1]
strhne r0, [r1]
@ return true;
mov r0, #1
bx lr