mirror of
https://github.com/Rockbox/rockbox.git
synced 2026-10-10 08:03:04 -04:00
stm32h743: implement timer API
Change-Id: Idcac3ab528e154097fb76fcfda78540ef02494df
This commit is contained in:
Aidan MacDonald
Solomon Peachy
parent
c187b4c674
commit
862370982c
11 changed files with 458 additions and 21 deletions
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@ -1970,6 +1970,7 @@ target/arm/stm32/echoplayer/pcm-echoplayer.c
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target/arm/stm32/echoplayer/power-echoplayer.c
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target/arm/stm32/echoplayer/sdmmc-echoplayer.c
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target/arm/stm32/echoplayer/system-echoplayer.c
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target/arm/stm32/echoplayer/timer-echoplayer.c
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target/arm/stm32/echoplayer/usb-echoplayer.c
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#endif
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@ -15,7 +15,7 @@
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#define CPU_FREQ 480000000
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#ifndef SIMULATOR
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#define TIMER_FREQ STM32_HSE_FREQ
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#define TIMER_FREQ (CPU_FREQ / 2)
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#endif
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/* Kernel defines */
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@ -1757,3 +1757,283 @@ block ADC {
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ADC1 @ 0x40022000 : ADC
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ADC2 @ 0x40022100 : ADC
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ADC3 @ 0x58026000 : ADC
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block TIM {
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CR1 @ 0x00 : reg {
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-- 11 UIFREMAP
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09 08 CKD
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-- 07 ARPE
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06 05 CMS
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-- 04 DIR
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-- 03 OPM
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-- 02 URS
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-- 01 UDIS
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-- 00 CEN
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}
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CR2 @ 0x04 : reg {
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23 20 MMS2
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-- 18 OIS6
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-- 16 OIS5
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-- 14 OIS4
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-- 13 OIS3N
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-- 12 OIS3
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-- 11 OIS2N
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-- 10 OIS2
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-- 09 OIS1N
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-- 08 OIS1
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-- 07 TI1S
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06 04 MMS
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-- 03 CCDS
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-- 02 CCUS
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-- 00 CCPC
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}
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SMCR @ 0x08 : reg {
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21 20 TS_4_3
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-- 16 SMS3
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-- 15 ETP
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-- 14 ECE
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13 12 ETPS
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11 08 ETF
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-- 07 MSM
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06 04 TS
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02 00 SMS
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}
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DIER @ 0x0c : reg {
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-- 14 TDE
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-- 13 COMDE
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-- 12 CC4DE
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-- 11 CC3DE
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-- 10 CC2DE
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-- 09 CC1DE
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-- 08 UDE
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-- 07 BIE
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-- 06 TIE
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-- 05 COMIE
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-- 04 CC4IE
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-- 03 CC3IE
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-- 02 CC2IE
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-- 01 CC1IE
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-- 00 UIE
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}
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SR @ 0x10 : reg {
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-- 17 CC6IF
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-- 16 CC5IF
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-- 13 SBIF
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-- 12 CC4OF
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-- 11 CC3OF
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-- 10 CC2OF
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-- 09 CC1OF
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-- 08 B2IF
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-- 07 BIF
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-- 06 TIF
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-- 05 COMIF
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-- 04 CC4IF
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-- 03 CC3IF
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-- 02 CC2IF
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-- 01 CC1IF
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-- 00 UIF
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}
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EGR @ 0x14 : reg {
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-- 08 B2G
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-- 07 BG
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-- 06 TG
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-- 05 COMG
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-- 04 CC4G
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-- 03 CC3G
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-- 02 CC2G
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-- 01 CC1G
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-- 00 UG
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}
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CCMR1 @ 0x18 : reg {
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09 08 CC2S
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01 00 CC1S
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}
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CCMR1_IN @ 0x18 : reg {
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15 12 IC2F
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11 10 IC2PSC
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09 08 CC2S
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07 04 IC1F
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03 02 IC1PSC
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01 00 CC1S
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}
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CCMR1_OUT @ 0x18 : reg {
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-- 24 OC2M3
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-- 16 OC1M3
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-- 15 OC2CE
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14 12 OC2M
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-- 11 OC2PE
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-- 10 OC2FE
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09 08 CC2S
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-- 07 OC1CE
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06 04 OC1M
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-- 03 OC1PE
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-- 02 OC1FE
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01 00 CC1S
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}
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CCMR2 @ 0x1c : reg {
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09 08 CC4S
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01 00 CC3S
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}
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CCMR2_IN @ 0x1c : reg {
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15 12 IC4F
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11 10 IC4PSC
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09 08 CC4S
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07 04 IC3F
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03 02 IC3PSC
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01 00 CC3S
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}
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CCMR2_OUT @ 0x1c : reg {
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-- 24 OC4M3
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-- 16 OC3M3
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-- 15 OC4CE
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14 12 OC4M
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-- 11 OC4PE
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-- 10 OC4FE
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09 08 CC4S
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-- 07 OC3CE
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06 04 OC3M
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-- 03 OC3PE
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-- 02 OC3FE
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01 00 CC3S
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}
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CCER @ 0x20 : reg {
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-- 21 CC6P
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-- 20 CC6E
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-- 17 CC5P
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-- 16 CC5E
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-- 15 CC4NP
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-- 14 CC4NE
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-- 13 CC4P
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-- 12 CC4E
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-- 11 CC3NP
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-- 10 CC3NE
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-- 09 CC3P
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-- 08 CC3E
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-- 07 CC2NP
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-- 06 CC2NE
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-- 05 CC2P
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-- 04 CC2E
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-- 03 CC1NP
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-- 02 CC1NE
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-- 01 CC1P
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-- 00 CC1E
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}
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CNT @ 0x24 : reg {
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-- 31 UIFCPY
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15 00 CNT
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}
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CNT32 @ 0x24 : reg {
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-- 31 UIFCPY
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30 00 CNT
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}
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PSC @ 0x28 : reg
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ARR @ 0x2c : reg
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RCR @ 0x30 : reg
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CCR1 @ 0x34 : reg
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CCR2 @ 0x38 : reg
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CCR3 @ 0x3c : reg
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CCR4 @ 0x40 : reg
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BDTR @ 0x44 : reg {
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-- 25 BK2P
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-- 24 BK2E
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23 20 BK2F
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19 16 BKF
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-- 15 MOE
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-- 14 AOE
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-- 13 BKP
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-- 12 BKE
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-- 11 OSSR
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-- 10 OSSI
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09 08 LOCK
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07 00 DTG
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}
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DCR @ 0x48 : reg {
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12 08 DBL
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04 00 DBA
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}
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DMAR @ 0x4c : reg
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CCMR3_OUT @ 0x54 : reg {
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-- 24 OC6M3
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-- 16 OC5M3
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-- 15 OC6CE
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14 12 OC6M
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-- 11 OC6PE
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-- 10 OC6FE
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-- 07 OC5CE
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06 04 OC5M
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-- 03 OC5PE
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-- 02 OC5FE
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}
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CCR5 @ 0x58 : reg {
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-- 31 GC5C3
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-- 30 GC5C2
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-- 29 GC5C1
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15 00 CCR5
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}
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CCR6 @ 0x5c : reg
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AF1 @ 0x60 : reg {
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17 14 ETRSEL
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-- 11 BKCMP2P
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-- 10 BKCMP1P
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-- 09 BKINP
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-- 08 BKDFxBKxE // differs for TIM1/TIM8
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-- 02 BKCMP2E
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-- 01 BKCMP1E
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-- 00 BKINE
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}
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AF2 @ 0x64 : reg {
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-- 11 BK2CMP2P
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-- 10 BK2CMP1P
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-- 09 BK2INP
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-- 08 BK2DFxBKxE // differs for TIM1/TIM8
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-- 02 BK2CMP2E
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-- 01 BK2CMP1E
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-- 00 BK2INE
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}
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TISEL @ 0x68 : reg {
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27 24 TI4SEL
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19 16 TI3SEL
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11 08 TI2SEL
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03 00 TI1SEL
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}
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}
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TIM17 @ 0x40014800 : TIM
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TIM16 @ 0x40014400 : TIM
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TIM15 @ 0x40014000 : TIM
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TIM8 @ 0x40010400 : TIM
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TIM1 @ 0x40010000 : TIM
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TIM14 @ 0x40002000 : TIM
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TIM13 @ 0x40001c00 : TIM
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TIM12 @ 0x40001800 : TIM
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TIM7 @ 0x40001400 : TIM
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TIM6 @ 0x40001000 : TIM
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TIM5 @ 0x40000c00 : TIM
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TIM4 @ 0x40000800 : TIM
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TIM3 @ 0x40000400 : TIM
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TIM2 @ 0x40000000 : TIM
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@ -211,3 +211,11 @@ const struct stm32_clock i2c1_ker_clock = {
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.lpen_reg = ITA_RCC_APB1LLPENR,
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.lpen_bit = BM_RCC_APB1LENR_I2C1EN,
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};
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const struct stm32_clock tim7_ker_clock = {
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.frequency = TIMER_FREQ,
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.en_reg = ITA_RCC_APB1LENR,
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.en_bit = BM_RCC_APB1LENR_TIM7EN,
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.lpen_reg = ITA_RCC_APB1LLPENR,
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.lpen_bit = BM_RCC_APB1LENR_TIM7EN,
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};
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@ -28,5 +28,6 @@ extern const struct stm32_clock sdmmc1_ker_clock;
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extern const struct stm32_clock ltdc_ker_clock;
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extern const struct stm32_clock spi5_ker_clock;
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extern const struct stm32_clock i2c1_ker_clock;
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extern const struct stm32_clock tim7_ker_clock;
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#endif /* __CLOCK_ECHOPLAYER_H__ */
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@ -19,13 +19,16 @@
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****************************************************************************/
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#include "system.h"
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#include "button.h"
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#include "nvic-arm.h"
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#include "gpio-stm32h7.h"
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#include "timer-stm32h7.h"
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#include "clock-echoplayer.h"
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#include "system-echoplayer.h"
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#include "regs/stm32h743/fmc.h"
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#include "regs/stm32h743/pwr.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/rtc.h"
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#include "regs/stm32h743/tim.h"
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#include "regs/cortex-m/cm_scb.h"
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#ifdef BOOTLOADER
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@ -251,6 +254,9 @@ void system_init(void)
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/* Disable RTC_OUT pin */
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echoplayer_set_rtcout_mode(ECHOPLAYER_RTCOUT_DISABLED);
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/* Setup for timer API */
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stm32h7_timer_init(ITA_TIM7, NVIC_IRQN_TIM7, &tim7_ker_clock);
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}
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void system_exception_wait(void)
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25
firmware/target/arm/stm32/echoplayer/timer-echoplayer.c
Normal file
25
firmware/target/arm/stm32/echoplayer/timer-echoplayer.c
Normal file
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@ -0,0 +1,25 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2026 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "timer-stm32h7.h"
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void tim7_irq_handler(void)
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{
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stm32h7_timer_irq();
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}
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@ -68,6 +68,22 @@ void spi3_irq_handler(void) ATTR_IRQ_HANDLER;
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void spi4_irq_handler(void) ATTR_IRQ_HANDLER;
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void spi5_irq_handler(void) ATTR_IRQ_HANDLER;
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void spi6_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim1_brk_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim1_cc_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim1_trg_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim1_up_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim2_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim3_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim4_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim6_dac_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim7_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim8_brk_tim12_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim8_cc_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim8_trg_tim14_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim8_up_tim13_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim15_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim16_irq_handler(void) ATTR_IRQ_HANDLER;
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void tim17_irq_handler(void) ATTR_IRQ_HANDLER;
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void exti0_irq_handler(void) ATTR_IRQ_HANDLER;
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void exti1_irq_handler(void) ATTR_IRQ_HANDLER;
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void exti2_irq_handler(void) ATTR_IRQ_HANDLER;
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@ -18,19 +18,88 @@
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*
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****************************************************************************/
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#include "timer.h"
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#include "nvic-arm.h"
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#include "clock-stm32h7.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/tim.h"
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static uint32_t tim_reg;
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static int tim_irq;
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static const struct stm32_clock *tim_clk;
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void stm32h7_timer_init(uint32_t instance,
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int irq,
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const struct stm32_clock *clock)
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{
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tim_reg = instance;
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tim_irq = irq;
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tim_clk = clock;
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}
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void stm32h7_timer_irq(void)
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{
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reg_assignlf(tim_reg, TIM_SR, UIF(0));
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if (pfn_timer)
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pfn_timer();
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}
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bool timer_set(long cycles, bool start)
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{
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(void)cycles;
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(void)start;
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if (cycles <= 0)
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return false;
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/* Calculate timer interval */
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uint32_t counter = cycles;
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uint32_t prescaler = 1;
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while (counter > 0xFFFF && prescaler < 0x10000)
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{
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counter >>= 1;
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prescaler <<= 1;
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}
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/* Duration too long */
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if (counter >= 0xFFFF)
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return false;
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/* Unregister old function */
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if (start && pfn_unregister)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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/* Set up timer */
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stm32_clock_enable(tim_clk);
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reg_writef(RCC_APB1LENR, TIM7EN(1));
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reg_assignlf(tim_reg, TIM_CR1, URS(1));
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reg_assignlf(tim_reg, TIM_EGR, UG(1));
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reg_assignlf(tim_reg, TIM_DIER, UIE(1));
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reg_assignlf(tim_reg, TIM_SR, UIF(1));
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reg_varl(tim_reg, TIM_CNT) = 0;
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reg_varl(tim_reg, TIM_ARR) = counter;
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reg_varl(tim_reg, TIM_PSC) = prescaler - 1;
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if (start)
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return timer_start();
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return true;
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}
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bool timer_start(void)
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{
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return false;
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stm32_clock_enable(tim_clk);
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nvic_enable_irq(tim_irq);
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reg_writef(RCC_APB1LENR, TIM7EN(1));
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reg_writelf(tim_reg, TIM_CR1, URS(0), CEN(1));
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return true;
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}
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void timer_stop(void)
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{
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nvic_disable_irq(tim_irq);
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reg_writelf(tim_reg, TIM_CR1, CEN(0));
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stm32_clock_disable(tim_clk);
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||||
}
|
||||
|
|
|
|||
31
firmware/target/arm/stm32/timer-stm32h7.h
Normal file
31
firmware/target/arm/stm32/timer-stm32h7.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
*
|
||||
* Copyright (C) 2026 Aidan MacDonald
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef __TIMER_STM32H7_H__
|
||||
#define __TIMER_STM32H7_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct stm32_clock;
|
||||
|
||||
void stm32h7_timer_init(uint32_t instance, int irq,
|
||||
const struct stm32_clock *clock);
|
||||
void stm32h7_timer_irq(void);
|
||||
|
||||
#endif /* __TIMER_STM32H7_H__ */
|
||||
|
|
@ -50,13 +50,13 @@ __vectors_platform:
|
|||
.word UIE /* [ 21] */
|
||||
.word UIE /* [ 22] */
|
||||
.word exti9_5_irq_handler /* [ 23] EXTI5 to EXTI9 */
|
||||
.word UIE /* [ 24] */
|
||||
.word UIE /* [ 25] */
|
||||
.word UIE /* [ 26] */
|
||||
.word UIE /* [ 27] */
|
||||
.word UIE /* [ 28] */
|
||||
.word UIE /* [ 29] */
|
||||
.word UIE /* [ 30] */
|
||||
.word tim1_brk_irq_handler /* [ 24] TIM1_BRK */
|
||||
.word tim1_up_irq_handler /* [ 25] TIM1_UP */
|
||||
.word tim1_trg_irq_handler /* [ 26] TIM1_TRG_COM */
|
||||
.word tim1_cc_irq_handler /* [ 27] TIM1_CC */
|
||||
.word tim2_irq_handler /* [ 28] TIM2 */
|
||||
.word tim3_irq_handler /* [ 29] TIM3 */
|
||||
.word tim4_irq_handler /* [ 30] TIM4 */
|
||||
.word i2c1_irq_handler /* [ 31] I2C1 event */
|
||||
.word i2c1_irq_handler /* [ 32] I2C1 error */
|
||||
.word i2c2_irq_handler /* [ 33] I2C2 event */
|
||||
|
|
@ -69,10 +69,10 @@ __vectors_platform:
|
|||
.word exti15_10_irq_handler /* [ 40] EXTI10 to EXTI15 */
|
||||
.word UIE /* [ 41] */
|
||||
.word UIE /* [ 42] */
|
||||
.word UIE /* [ 43] */
|
||||
.word UIE /* [ 44] */
|
||||
.word UIE /* [ 45] */
|
||||
.word UIE /* [ 46] */
|
||||
.word tim8_brk_tim12_irq_handler /* [ 43] TIM8_BRK / TIM12 */
|
||||
.word tim8_up_tim13_irq_handler /* [ 44] TIM8_UP / TIM13 */
|
||||
.word tim8_trg_tim14_irq_handler /* [ 45] TIM8_TRG_COM / TIM14 */
|
||||
.word tim8_cc_irq_handler /* [ 46] TIM8_CC */
|
||||
.word dma1_ch7_irq_handler /* [ 47] DMA1 Stream7 */
|
||||
.word UIE /* [ 48] */
|
||||
.word sdmmc1_irq_handler /* [ 49] SDMMC1 */
|
||||
|
|
@ -80,8 +80,8 @@ __vectors_platform:
|
|||
.word spi3_irq_handler /* [ 51] SPI3 */
|
||||
.word UIE /* [ 52] */
|
||||
.word UIE /* [ 53] */
|
||||
.word UIE /* [ 54] */
|
||||
.word UIE /* [ 55] */
|
||||
.word tim6_dac_irq_handler /* [ 54] TIM6 / DAC */
|
||||
.word tim7_irq_handler /* [ 55] TIM7 */
|
||||
.word dma2_ch0_irq_handler /* [ 56] DMA2 Stream0 */
|
||||
.word dma2_ch1_irq_handler /* [ 57] DMA2 Stream1 */
|
||||
.word dma2_ch2_irq_handler /* [ 58] DMA2 Stream2 */
|
||||
|
|
@ -142,9 +142,9 @@ __vectors_platform:
|
|||
.word UIE /* [113] */
|
||||
.word sai3_irq_handler /* [114] SAI3 */
|
||||
.word UIE /* [115] */
|
||||
.word UIE /* [116] */
|
||||
.word UIE /* [117] */
|
||||
.word UIE /* [118] */
|
||||
.word tim15_irq_handler /* [116] TIM15 */
|
||||
.word tim16_irq_handler /* [117] TIM16 */
|
||||
.word tim17_irq_handler /* [118] TIM17 */
|
||||
.word UIE /* [119] */
|
||||
.word UIE /* [120] */
|
||||
.word UIE /* [121] */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue