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imx233: rewrite dma using new register headers
Change-Id: If73b84d9c9f4a152a54fb9d2dbec895e72d2e753
This commit is contained in:
Amaury Pouly
parent
852a82b90a
commit
8390eb931e
5 changed files with 140 additions and 226 deletions
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@ -25,91 +25,29 @@
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#include "system.h"
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#include "system-target.h"
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/********
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* APHB *
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********/
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#include "regs/regs-apbh.h"
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#include "regs/regs-apbx.h"
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#define HW_APBH_BASE 0x80004000
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/************
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* CHANNELS *
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************/
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/* APHB channels */
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#define HW_APBH_SSP(ssp) ssp
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#define HW_APBH_NAND(dev) (4 + (ssp))
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#define APBH_DMA_CHANNEL(i) i
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#define APBX_DMA_CHANNEL(i) ((i) | 0x10)
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#define APB_IS_APBX_CHANNEL(x) ((x) & 0x10)
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#define APB_GET_DMA_CHANNEL(x) ((x) & 0xf)
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#define HW_APBH_CTRL0 (*(volatile uint32_t *)(HW_APBH_BASE + 0x0))
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#define HW_APBH_CTRL0__FREEZE_CHANNEL(i) (1 << (i))
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#define HW_APBH_CTRL0__CLKGATE_CHANNEL(i) (1 << ((i) + 8))
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#define HW_APBH_CTRL0__RESET_CHANNEL(i) (1 << ((i) + 16))
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#define HW_APBH_CTRL0__APB_BURST4_EN (1 << 28)
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#define HW_APBH_CTRL0__APB_BURST8_EN (1 << 29)
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// NOTE: although undocumented, the iMX233 channel 0 is actually the LCDIF one
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#define APB_LCDIF APBH_DMA_CHANNEL(0)
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#define HW_APBH_CTRL1 (*(volatile uint32_t *)(HW_APBH_BASE + 0x10))
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#define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i))
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#define HW_APBH_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16))
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#define APB_SSP(ssp) APBH_DMA_CHANNEL(ssp)
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#define APB_GPMI(dev) APBH_DMA_CHANNEL(4 + (dev))
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#define HW_APBH_CTRL2 (*(volatile uint32_t *)(HW_APBH_BASE + 0x20))
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#define HW_APBH_CTRL2__CHx_ERROR_IRQ(i) (1 << (i))
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#define HW_APBH_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16))
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#define HW_APBH_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x40 + 0x70 * (i)))
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#define HW_APBH_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x50 + 0x70 * (i)))
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#define HW_APBH_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x60 + 0x70 * (i)))
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#define HW_APBH_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x70 + 0x70 * (i)))
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#define HW_APBH_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x80 + 0x70 * (i)))
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#define HW_APBH_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0x90 + 0x70 * (i)))
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#define HW_APBH_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBH_BASE + 0xa0 + 0x70 * (i)))
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#define HW_APBH_CHx_DEBUG2__AHB_BYTES_BP 0
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#define HW_APBH_CHx_DEBUG2__AHB_BYTES_BM 0xffff
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#define HW_APBH_CHx_DEBUG2__APB_BYTES_BP 16
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#define HW_APBH_CHx_DEBUG2__APB_BYTES_BM 0xffff0000
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/********
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* APHX *
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********/
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/* APHX channels */
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#define HW_APBX_AUDIO_ADC 0
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#define HW_APBX_AUDIO_DAC 1
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#define HW_APBX_I2C 3
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#define HW_APBX_BASE 0x80024000
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#define HW_APBX_CTRL0 (*(volatile uint32_t *)(HW_APBX_BASE + 0x0))
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#define HW_APBX_CTRL1 (*(volatile uint32_t *)(HW_APBX_BASE + 0x10))
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#define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ(i) (1 << (i))
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#define HW_APBX_CTRL1__CHx_CMDCMPLT_IRQ_EN(i) (1 << ((i) + 16))
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#define HW_APBX_CTRL2 (*(volatile uint32_t *)(HW_APBX_BASE + 0x20))
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#define HW_APBX_CTRL2__CHx_ERROR_IRQ(i) (1 << (i))
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#define HW_APBX_CTRL2__CHx_ERROR_STATUS(i) (1 << ((i) + 16))
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#define HW_APBX_CHANNEL_CTRL (*(volatile uint32_t *)(HW_APBX_BASE + 0x30))
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#define HW_APBX_CHANNEL_CTRL__FREEZE_CHANNEL(i) (1 << (i))
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#define HW_APBX_CHANNEL_CTRL__RESET_CHANNEL(i) (1 << ((i) + 16))
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#define HW_APBX_CHx_CURCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x100 + (i) * 0x70))
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#define HW_APBX_CHx_NXTCMDAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x110 + (i) * 0x70))
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#define HW_APBX_CHx_CMD(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x120 + (i) * 0x70))
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#define HW_APBX_CHx_BAR(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x130 + (i) * 0x70))
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#define HW_APBX_CHx_SEMA(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x140 + (i) * 0x70))
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#define HW_APBX_CHx_DEBUG1(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x150 + (i) * 0x70))
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#define HW_APBX_CHx_DEBUG2(i) (*(volatile uint32_t *)(HW_APBX_BASE + 0x160 + (i) * 0x70))
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#define HW_APBX_CHx_DEBUG2__AHB_BYTES_BP 0
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#define HW_APBX_CHx_DEBUG2__AHB_BYTES_BM 0xffff
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#define HW_APBX_CHx_DEBUG2__APB_BYTES_BP 16
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#define HW_APBX_CHx_DEBUG2__APB_BYTES_BM 0xffff0000
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#define APB_AUDIO_ADC APBX_DMA_CHANNEL(0)
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#define APB_AUDIO_DAC APBX_DMA_CHANNEL(1)
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#define APB_I2C APBX_DMA_CHANNEL(3)
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// NOTE: although undocumented, the IMX233 channel 5 is actually the DRI one
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#define APB_DRI APBX_DMA_CHANNEL(5)
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/**********
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* COMMON *
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@ -154,43 +92,49 @@ struct imx233_dma_info_t
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int nr_unaligned;
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};
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#define APBH_DMA_CHANNEL(i) i
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#define APBX_DMA_CHANNEL(i) ((i) | 0x10)
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#define APB_IS_APBX_CHANNEL(x) ((x) & 0x10)
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#define APB_GET_DMA_CHANNEL(x) ((x) & 0xf)
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#define APB_SSP(ssp) APBH_DMA_CHANNEL(HW_APBH_SSP(ssp))
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#define APB_AUDIO_ADC APBX_DMA_CHANNEL(HW_APBX_AUDIO_ADC)
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#define APB_AUDIO_DAC APBX_DMA_CHANNEL(HW_APBX_AUDIO_DAC)
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#define APB_I2C APBX_DMA_CHANNEL(HW_APBX_I2C)
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#define APB_NAND(dev) APBH_DMA_CHANNEL(HW_APBH_NAND(dev))
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#define HW_APB_CHx_CMD__COMMAND_BM 0x3
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#define HW_APB_CHx_CMD__COMMAND_BP 0
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#define HW_APB_CHx_CMD__COMMAND__NO_XFER 0
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#define HW_APB_CHx_CMD__COMMAND__WRITE 1
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#define HW_APB_CHx_CMD__COMMAND__READ 2
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#define HW_APB_CHx_CMD__COMMAND__SENSE 3
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#define HW_APB_CHx_CMD__CHAIN (1 << 2)
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#define HW_APB_CHx_CMD__IRQONCMPLT (1 << 3)
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#define BM_APB_CHx_CMD_COMMAND 0x3
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#define BP_APB_CHx_CMD_COMMAND 0
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#define BF_APB_CHx_CMD_COMMAND(v) ((v) & 0x3)
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#define BF_APB_CHx_CMD_COMMAND_V(v) BF_APB_CHx_CMD_COMMAND(BV_APB_CHx_CMD_COMMAND__##v)
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#define BV_APB_CHx_CMD_COMMAND__NO_XFER 0
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#define BV_APB_CHx_CMD_COMMAND__WRITE 1
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#define BV_APB_CHx_CMD_COMMAND__READ 2
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#define BV_APB_CHx_CMD_COMMAND__SENSE 3
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#define BM_APB_CHx_CMD_CHAIN (1 << 2)
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#define BP_APB_CHx_CMD_CHAIN 2
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#define BF_APB_CHx_CMD_CHAIN(v) (((v) & 1) << 2)
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#define BM_APB_CHx_CMD_IRQONCMPLT (1 << 3)
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#define BP_APB_CHx_CMD_IRQONCMPLT 3
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#define BF_APB_CHx_CMD_IRQONCMPLT(v) (((v) & 1) << 3)
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/* those two are only available on APHB */
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#define HW_APBH_CHx_CMD__NANDLOCK (1 << 4)
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#define HW_APBH_CHx_CMD__NANDWAIT4READY (1 << 5)
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#define HW_APB_CHx_CMD__SEMAPHORE (1 << 6)
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#define HW_APB_CHx_CMD__WAIT4ENDCMD (1 << 7)
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/* An errata advise not to use it */
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#define HW_APB_CHx_CMD__HALTONTERMINATE (1 << 8)
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#define HW_APB_CHx_CMD__CMDWORDS_BM 0xf000
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#define HW_APB_CHx_CMD__CMDWORDS_BP 12
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#define HW_APB_CHx_CMD__XFER_COUNT_BM 0xffff0000
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#define HW_APB_CHx_CMD__XFER_COUNT_BP 16
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/* For software use */
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#define HW_APB_CHx_CMD__UNUSED_BP 8
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#define HW_APB_CHx_CMD__UNUSED_BM (0xf << 8)
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#define HW_APB_CHx_CMD__UNUSED_MAGIC (0xa << 8)
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#define BM_APBH_CHx_CMD_NANDLOCK (1 << 4)
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#define BP_APBH_CHx_CMD_NANDLOCK 4
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#define BF_APBH_CHx_CMD_NANDLOCK(v) (((v) & 1) << 4)
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#define BM_APBH_CHx_CMD_NANDWAIT4READY (1 << 5)
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#define BP_APBH_CHx_CMD_NANDWAIT4READY 5
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#define BF_APBH_CHx_CMD_NANDWAIT4READY(v) (((v) & 1) << 5)
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#define HW_APB_CHx_SEMA__PHORE_BM 0xff0000
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#define HW_APB_CHx_SEMA__PHORE_BP 16
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#define BM_APB_CHx_CMD_SEMAPHORE (1 << 6)
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#define BP_APB_CHx_CMD_SEMAPHORE 6
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#define BF_APB_CHx_CMD_SEMAPHORE(v) (((v) & 1) << 6)
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#define BM_APB_CHx_CMD_WAIT4ENDCMD (1 << 7)
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#define BP_APB_CHx_CMD_WAIT4ENDCMD 7
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#define BF_APB_CHx_CMD_WAIT4ENDCMD(v) (((v) & 1) << 7)
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/** WARNING: An errata advise not to use it */
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#define BM_APB_CHx_CMD_HALTONTERMINATE (1 << 8)
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#define BP_APB_CHx_CMD_HALTONTERMINATE 8
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#define BF_APB_CHx_CMD_HALTONTERMINATE(v) (((v) & 1) << 8)
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#define BM_APB_CHx_CMD_CMDWORDS 0xf000
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#define BP_APB_CHx_CMD_CMDWORDS 12
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#define BF_APB_CHx_CMD_CMDWORDS(v) (((v) & 0xf) << 12)
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#define BM_APB_CHx_CMD_XFER_COUNT 0xffff0000
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#define BP_APB_CHx_CMD_XFER_COUNT 16
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#define BF_APB_CHx_CMD_XFER_COUNT(v) (((v) & 0xffff) << 16)
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/* For software use */
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#define BP_APB_CHx_CMD_UNUSED 8
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#define BM_APB_CHx_CMD_UNUSED (0xf << 8)
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#define BF_APB_CHx_CMD_UNUSED(v) (((v) & 0xf) << 8)
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#define BV_APB_CHx_CMD_UNUSED__MAGIC 0xa
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/* A single descriptor cannot transfer more than 2^16 bytes but because of the
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* weird 0=64KiB, it's safer to restrict to 2^15 */
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