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Dual core support for PP502x players (iPod G4 and later, iriver h10, Sansa - iPod G3 will be coming soon.) This allows threads to be run on either core provided that all communications between the cores is done using uncached memory. There should be no significant change in battery life from doing this. Documentation (on the RockboxKernel wiki page) will follow shortly.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12601 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Daniel Ankers
parent
74e572c9d6
commit
82f9056988
38 changed files with 379 additions and 211 deletions
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@ -612,12 +612,22 @@ extern void ipod_mini_button_int(void);
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void irq(void)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & GPIO_MASK)
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ipod_mini_button_int();
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}
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}
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#elif (defined IRIVER_H10) || (defined IRIVER_H10_5GB) || defined(ELIO_TPJ1022) \
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|| (defined SANSA_E200)
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@ -626,22 +636,40 @@ void irq(void)
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/* TODO: Even if it isn't in the target tree, this should be the default case */
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void irq(void)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#else
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extern void ipod_4g_button_int(void);
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void irq(void)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (CPU_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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else if (COP_HI_INT_STAT & I2C_MASK)
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ipod_4g_button_int();
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}
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}
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#endif
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#endif /* BOOTLOADER */
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@ -694,43 +722,47 @@ void set_cpu_frequency(long frequency)
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{
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unsigned long postmult;
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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if (CURRENT_CORE == CPU)
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{
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Enable PLL? */
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outl(inl(0x70000020) | (1<<30), 0x70000020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Select 24MHz crystal as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
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/* Clock frequency = (24/8)*postmult */
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outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
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/* Clock frequency = (24/8)*postmult */
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outl(0xaa020000 | 8 | (postmult << 8), 0x60006034);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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/* Select PLL as clock source? */
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outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
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#if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB)
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/* We don't know why the timer interrupt gets disabled on the PP5020
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based ipods, but without the following line, the 4Gs will freeze
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when CPU frequency changing is enabled.
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/* We don't know why the timer interrupt gets disabled on the PP5020
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based ipods, but without the following line, the 4Gs will freeze
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when CPU frequency changing is enabled.
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Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
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elsewhere to enable interrupts) doesn't work, we need "|=".
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Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used
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elsewhere to enable interrupts) doesn't work, we need "|=".
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It's not needed on the PP5021 and PP5022 ipods.
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*/
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It's not needed on the PP5021 and PP5022 ipods.
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*/
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/* unmask interrupt source */
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CPU_INT_EN |= TIMER1_MASK;
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/* unmask interrupt source */
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CPU_INT_EN |= TIMER1_MASK;
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COP_INT_EN |= TIMER1_MASK;
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#endif
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}
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}
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#elif !defined(BOOTLOADER)
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void ipod_set_cpu_frequency(void)
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@ -754,24 +786,33 @@ void ipod_set_cpu_frequency(void)
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void system_init(void)
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{
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#ifndef BOOTLOADER
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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if (CURRENT_CORE == CPU)
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{
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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/* The hw revision is written to the last 4 bytes of SDRAM by the
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bootloader - we save it before Rockbox overwrites it. */
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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/* The hw revision is written to the last 4 bytes of SDRAM by the
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bootloader - we save it before Rockbox overwrites it. */
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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/* disable all irqs */
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outl(-1, 0x60001138);
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outl(-1, 0x60001128);
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outl(-1, 0x6000111c);
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/* disable all irqs */
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outl(-1, 0x60001138);
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outl(-1, 0x60001128);
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outl(-1, 0x6000111c);
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outl(-1, 0x60001038);
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outl(-1, 0x60001028);
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outl(-1, 0x6000101c);
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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ipod_set_cpu_frequency();
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outl(-1, 0x60001038);
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outl(-1, 0x60001028);
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outl(-1, 0x6000101c);
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES == 1)
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ipod_set_cpu_frequency();
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#endif
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}
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#if (!defined HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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else
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{
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ipod_set_cpu_frequency();
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}
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#endif
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ipod_init_cache();
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#endif
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@ -796,10 +837,18 @@ extern void TIMER2(void);
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void irq(void)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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} else {
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif
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@ -848,29 +897,32 @@ void set_cpu_frequency(long frequency)
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{
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unsigned long postmult;
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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if (CURRENT_CORE == CPU)
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{
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if (frequency == CPUFREQ_NORMAL)
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postmult = CPUFREQ_NORMAL_MULT;
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else if (frequency == CPUFREQ_MAX)
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postmult = CPUFREQ_MAX_MULT;
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else
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postmult = CPUFREQ_DEFAULT_MULT;
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cpu_frequency = frequency;
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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outl(0x02, 0xcf005008);
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outl(0x55, 0xcf00500c);
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outl(0x6000, 0xcf005010);
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/* Clock frequency = (24/8)*postmult */
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outl(8, 0xcf005018);
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outl(postmult, 0xcf00501c);
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/* Clock frequency = (24/8)*postmult */
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outl(8, 0xcf005018);
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outl(postmult, 0xcf00501c);
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outl(0xe000, 0xcf005010);
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outl(0xe000, 0xcf005010);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Wait for PLL relock? */
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udelay(2000);
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/* Select PLL as clock source? */
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outl(0xa8, 0xcf00500c);
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/* Select PLL as clock source? */
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outl(0xa8, 0xcf00500c);
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}
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}
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#elif !defined(BOOTLOADER)
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static void ipod_set_cpu_speed(void)
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@ -901,17 +953,20 @@ static void ipod_set_cpu_speed(void)
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void system_init(void)
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{
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#ifndef BOOTLOADER
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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if (CURRENT_CORE == CPU)
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{
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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outl(-1, 0xcf00101c);
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outl(-1, 0xcf001028);
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outl(-1, 0xcf001038);
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ipod_hw_rev = (*((volatile unsigned long*)(0x01fffffc)));
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outl(-1, 0xcf00101c);
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outl(-1, 0xcf001028);
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outl(-1, 0xcf001038);
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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ipod_set_cpu_speed();
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ipod_set_cpu_speed();
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#endif
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}
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ipod_init_cache();
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#endif
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}
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