mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-10-13 18:17:39 -04:00
Unify S5L87xx register definitions
This is a preparation for merging both files to a new header named s5l87xx.h. Also removed unused register types. Change-Id: I6aa231064d6a7c734aa297e68b899d6988a88bdc
This commit is contained in:
Vencislav Atanasov
parent
0624e265ab
commit
7fcc6a34a5
2 changed files with 338 additions and 341 deletions
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@ -26,7 +26,6 @@
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#include <stdint.h>
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#endif
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#define REG8_PTR_T volatile uint8_t *
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#define REG16_PTR_T volatile uint16_t *
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#define REG32_PTR_T volatile uint32_t *
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@ -781,26 +780,26 @@
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#define HASHDATAIN ((REG32_PTR_T)(0x3C600040))
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/* Clickwheel controller - S5L8701 only */
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#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
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#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
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#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
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#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
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#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
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#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
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#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
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#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
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#define WHEEL00 (*((REG32_PTR_T)(0x3C200000)))
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#define WHEEL04 (*((REG32_PTR_T)(0x3C200004)))
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#define WHEEL08 (*((REG32_PTR_T)(0x3C200008)))
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#define WHEEL0C (*((REG32_PTR_T)(0x3C20000C)))
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#define WHEEL10 (*((REG32_PTR_T)(0x3C200010)))
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#define WHEELINT (*((REG32_PTR_T)(0x3C200014)))
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#define WHEELRX (*((REG32_PTR_T)(0x3C200018)))
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#define WHEELTX (*((REG32_PTR_T)(0x3C20001C)))
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/* Synopsys OTG - S5L8701 only */
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#define OTGBASE 0x38800000
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#define PHYBASE 0x3C400000
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/* OTG PHY control registers */
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#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
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#define OPHYPWR (*((REG32_PTR_T)(PHYBASE + 0x000)))
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#define OPHYCLK (*((REG32_PTR_T)(PHYBASE + 0x004)))
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#define ORSTCON (*((REG32_PTR_T)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((REG32_PTR_T)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((REG32_PTR_T)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((REG32_PTR_T)(PHYBASE + 0x044)))
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/* 7 available EPs (0b00000000011101010000000001101011), 6 used */
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#define USB_NUM_ENDPOINTS 6
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@ -26,8 +26,6 @@
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#include <stdint.h>
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#endif
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#define REG8_PTR_T volatile uint8_t *
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#define REG16_PTR_T volatile uint16_t *
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#define REG32_PTR_T volatile uint32_t *
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#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
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@ -48,49 +46,49 @@
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/////SYSTEM CONTROLLER/////
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#define CLKCON0 (*((volatile uint32_t*)(0x3C500000)))
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#define CLKCON1 (*((volatile uint32_t*)(0x3C500004)))
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#define CLKCON2 (*((volatile uint32_t*)(0x3C500008)))
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#define CLKCON3 (*((volatile uint32_t*)(0x3C50000C)))
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#define CLKCON4 (*((volatile uint32_t*)(0x3C500010)))
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#define CLKCON5 (*((volatile uint32_t*)(0x3C500014)))
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#define PLL0PMS (*((volatile uint32_t*)(0x3C500020)))
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#define PLL1PMS (*((volatile uint32_t*)(0x3C500024)))
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#define PLL2PMS (*((volatile uint32_t*)(0x3C500028)))
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#define PLL0LCNT (*((volatile uint32_t*)(0x3C500030)))
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#define PLL1LCNT (*((volatile uint32_t*)(0x3C500034)))
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#define PLL2LCNT (*((volatile uint32_t*)(0x3C500038)))
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#define PLLLOCK (*((volatile uint32_t*)(0x3C500040)))
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#define PLLMODE (*((volatile uint32_t*)(0x3C500044)))
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#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
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#define CLKCON0 (*((REG32_PTR_T)(0x3C500000)))
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#define CLKCON1 (*((REG32_PTR_T)(0x3C500004)))
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#define CLKCON2 (*((REG32_PTR_T)(0x3C500008)))
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#define CLKCON3 (*((REG32_PTR_T)(0x3C50000C)))
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#define CLKCON4 (*((REG32_PTR_T)(0x3C500010)))
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#define CLKCON5 (*((REG32_PTR_T)(0x3C500014)))
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#define PLL0PMS (*((REG32_PTR_T)(0x3C500020)))
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#define PLL1PMS (*((REG32_PTR_T)(0x3C500024)))
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#define PLL2PMS (*((REG32_PTR_T)(0x3C500028)))
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#define PLL0LCNT (*((REG32_PTR_T)(0x3C500030)))
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#define PLL1LCNT (*((REG32_PTR_T)(0x3C500034)))
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#define PLL2LCNT (*((REG32_PTR_T)(0x3C500038)))
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#define PLLLOCK (*((REG32_PTR_T)(0x3C500040)))
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#define PLLMODE (*((REG32_PTR_T)(0x3C500044)))
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#define PWRCON(i) (*((REG32_PTR_T)(0x3C500000 \
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+ ((i) == 4 ? 0x6C : \
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((i) == 3 ? 0x68 : \
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((i) == 2 ? 0x58 : \
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((i) == 1 ? 0x4C : \
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0x48)))))))
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/* SW Reset Control Register */
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#define SWRCON (*((volatile uint32_t*)(0x3C500050)))
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#define SWRCON (*((REG32_PTR_T)(0x3C500050)))
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/* Reset Status Register */
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#define RSTSR (*((volatile uint32_t*)(0x3C500054)))
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#define RSTSR (*((REG32_PTR_T)(0x3C500054)))
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#define RSTSR_WDR_BIT (1 << 2)
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#define RSTSR_SWR_BIT (1 << 1)
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#define RSTSR_HWR_BIT (1 << 0)
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/////WATCHDOG/////
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#define WDTCON (*((volatile uint32_t*)(0x3C800000)))
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#define WDTCNT (*((volatile uint32_t*)(0x3C800004)))
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#define WDTCON (*((REG32_PTR_T)(0x3C800000)))
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#define WDTCNT (*((REG32_PTR_T)(0x3C800004)))
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/////MEMCONTROLLER/////
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#define MIU_BASE (0x38100000)
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#define MIU_REG(off) (*((uint32_t volatile*)(MIU_BASE + (off))))
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#define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off))))
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/* following registers are similar to s5l8700x */
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#define MIUCON (*((uint32_t volatile*)(0x38100000)))
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#define MIUCOM (*((uint32_t volatile*)(0x38100004)))
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#define MIUAREF (*((uint32_t volatile*)(0x38100008)))
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#define MIUMRS (*((uint32_t volatile*)(0x3810000C)))
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#define MIUSDPARA (*((uint32_t volatile*)(0x38100010)))
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#define MIUCON (*((REG32_PTR_T)(0x38100000)))
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#define MIUCOM (*((REG32_PTR_T)(0x38100004)))
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#define MIUAREF (*((REG32_PTR_T)(0x38100008)))
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#define MIUMRS (*((REG32_PTR_T)(0x3810000C)))
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#define MIUSDPARA (*((REG32_PTR_T)(0x38100010)))
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/////TIMER/////
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@ -122,55 +120,55 @@
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*/
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#define TIMER_FREQ 12000000 /* ECLK */
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#define TACON (*((uint32_t volatile*)(0x3C700000)))
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#define TACMD (*((uint32_t volatile*)(0x3C700004)))
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#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
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#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
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#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
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#define TACNT (*((uint32_t volatile*)(0x3C700014)))
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#define TBCON (*((uint32_t volatile*)(0x3C700020)))
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#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
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#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
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#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
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#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
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#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
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#define TCCON (*((uint32_t volatile*)(0x3C700040)))
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#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
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#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
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#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
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#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
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#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
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#define TDCON (*((uint32_t volatile*)(0x3C700060)))
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#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
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#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
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#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
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#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
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#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
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#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
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#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
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#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
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#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
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#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
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#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
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#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
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#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
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#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
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#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
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#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
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#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
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#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
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#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
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#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
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#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
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#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
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#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
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#define THCON (*((uint32_t volatile*)(0x3C700100)))
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#define THCMD (*((uint32_t volatile*)(0x3C700104)))
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#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
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#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
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#define THPRE (*((uint32_t volatile*)(0x3C700110)))
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#define THCNT (*((uint32_t volatile*)(0x3C700114)))
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#define TSTAT (*((uint32_t volatile*)(0x3C700118)))
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#define TACON (*((REG32_PTR_T)(0x3C700000)))
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#define TACMD (*((REG32_PTR_T)(0x3C700004)))
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#define TADATA0 (*((REG32_PTR_T)(0x3C700008)))
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#define TADATA1 (*((REG32_PTR_T)(0x3C70000C)))
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#define TAPRE (*((REG32_PTR_T)(0x3C700010)))
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#define TACNT (*((REG32_PTR_T)(0x3C700014)))
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#define TBCON (*((REG32_PTR_T)(0x3C700020)))
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#define TBCMD (*((REG32_PTR_T)(0x3C700024)))
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#define TBDATA0 (*((REG32_PTR_T)(0x3C700028)))
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#define TBDATA1 (*((REG32_PTR_T)(0x3C70002C)))
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#define TBPRE (*((REG32_PTR_T)(0x3C700030)))
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#define TBCNT (*((REG32_PTR_T)(0x3C700034)))
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#define TCCON (*((REG32_PTR_T)(0x3C700040)))
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#define TCCMD (*((REG32_PTR_T)(0x3C700044)))
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#define TCDATA0 (*((REG32_PTR_T)(0x3C700048)))
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#define TCDATA1 (*((REG32_PTR_T)(0x3C70004C)))
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#define TCPRE (*((REG32_PTR_T)(0x3C700050)))
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#define TCCNT (*((REG32_PTR_T)(0x3C700054)))
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#define TDCON (*((REG32_PTR_T)(0x3C700060)))
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#define TDCMD (*((REG32_PTR_T)(0x3C700064)))
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#define TDDATA0 (*((REG32_PTR_T)(0x3C700068)))
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#define TDDATA1 (*((REG32_PTR_T)(0x3C70006C)))
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#define TDPRE (*((REG32_PTR_T)(0x3C700070)))
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#define TDCNT (*((REG32_PTR_T)(0x3C700074)))
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#define TECON (*((REG32_PTR_T)(0x3C7000A0)))
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#define TECMD (*((REG32_PTR_T)(0x3C7000A4)))
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#define TEDATA0 (*((REG32_PTR_T)(0x3C7000A8)))
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#define TEDATA1 (*((REG32_PTR_T)(0x3C7000AC)))
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#define TEPRE (*((REG32_PTR_T)(0x3C7000B0)))
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#define TECNT (*((REG32_PTR_T)(0x3C7000B4)))
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#define TFCON (*((REG32_PTR_T)(0x3C7000C0)))
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#define TFCMD (*((REG32_PTR_T)(0x3C7000C4)))
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#define TFDATA0 (*((REG32_PTR_T)(0x3C7000C8)))
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#define TFDATA1 (*((REG32_PTR_T)(0x3C7000CC)))
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#define TFPRE (*((REG32_PTR_T)(0x3C7000D0)))
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#define TFCNT (*((REG32_PTR_T)(0x3C7000D4)))
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#define TGCON (*((REG32_PTR_T)(0x3C7000E0)))
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#define TGCMD (*((REG32_PTR_T)(0x3C7000E4)))
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#define TGDATA0 (*((REG32_PTR_T)(0x3C7000E8)))
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#define TGDATA1 (*((REG32_PTR_T)(0x3C7000EC)))
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#define TGPRE (*((REG32_PTR_T)(0x3C7000F0)))
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#define TGCNT (*((REG32_PTR_T)(0x3C7000F4)))
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#define THCON (*((REG32_PTR_T)(0x3C700100)))
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#define THCMD (*((REG32_PTR_T)(0x3C700104)))
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#define THDATA0 (*((REG32_PTR_T)(0x3C700108)))
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#define THDATA1 (*((REG32_PTR_T)(0x3C70010C)))
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#define THPRE (*((REG32_PTR_T)(0x3C700110)))
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#define THCNT (*((REG32_PTR_T)(0x3C700114)))
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#define TSTAT (*((REG32_PTR_T)(0x3C700118)))
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#define USEC_TIMER TECNT
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#define PHYBASE 0x3C400000
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/* OTG PHY control registers */
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#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
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#define OPHYPWR (*((REG32_PTR_T)(PHYBASE + 0x000)))
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#define OPHYCLK (*((REG32_PTR_T)(PHYBASE + 0x004)))
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#define ORSTCON (*((REG32_PTR_T)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((REG32_PTR_T)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((REG32_PTR_T)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((REG32_PTR_T)(PHYBASE + 0x044)))
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/* 9 available EPs (0b00000001111101010000000111101011), 6 used */
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#define USB_NUM_ENDPOINTS 6
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@ -212,42 +210,42 @@
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starts when it is written as "1".
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*/
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#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
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#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
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#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
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#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
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#define IICUNK10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus))))
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#define IICUNK14(bus) (*((uint32_t volatile*)(0x3C600014 + 0x300000 * (bus))))
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#define IICUNK18(bus) (*((uint32_t volatile*)(0x3C600018 + 0x300000 * (bus))))
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#define IICSTA2(bus) (*((uint32_t volatile*)(0x3C600020 + 0x300000 * (bus))))
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#define IICCON(bus) (*((REG32_PTR_T)(0x3C600000 + 0x300000 * (bus))))
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#define IICSTAT(bus) (*((REG32_PTR_T)(0x3C600004 + 0x300000 * (bus))))
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#define IICADD(bus) (*((REG32_PTR_T)(0x3C600008 + 0x300000 * (bus))))
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#define IICDS(bus) (*((REG32_PTR_T)(0x3C60000C + 0x300000 * (bus))))
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#define IICUNK10(bus) (*((REG32_PTR_T)(0x3C600010 + 0x300000 * (bus))))
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#define IICUNK14(bus) (*((REG32_PTR_T)(0x3C600014 + 0x300000 * (bus))))
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#define IICUNK18(bus) (*((REG32_PTR_T)(0x3C600018 + 0x300000 * (bus))))
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#define IICSTA2(bus) (*((REG32_PTR_T)(0x3C600020 + 0x300000 * (bus))))
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/////INTERRUPT CONTROLLERS/////
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#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
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#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
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#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
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#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
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#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
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#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
|
||||
#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
|
||||
#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
|
||||
#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
|
||||
#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
|
||||
#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
|
||||
#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
|
||||
#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
|
||||
#define VICIRQSTATUS(v) (*((REG32_PTR_T)(0x38E00000 + 0x1000 * (v))))
|
||||
#define VICFIQSTATUS(v) (*((REG32_PTR_T)(0x38E00004 + 0x1000 * (v))))
|
||||
#define VICRAWINTR(v) (*((REG32_PTR_T)(0x38E00008 + 0x1000 * (v))))
|
||||
#define VICINTSELECT(v) (*((REG32_PTR_T)(0x38E0000C + 0x1000 * (v))))
|
||||
#define VICINTENABLE(v) (*((REG32_PTR_T)(0x38E00010 + 0x1000 * (v))))
|
||||
#define VICINTENCLEAR(v) (*((REG32_PTR_T)(0x38E00014 + 0x1000 * (v))))
|
||||
#define VICSOFTINT(v) (*((REG32_PTR_T)(0x38E00018 + 0x1000 * (v))))
|
||||
#define VICSOFTINTCLEAR(v) (*((REG32_PTR_T)(0x38E0001C + 0x1000 * (v))))
|
||||
#define VICPROTECTION(v) (*((REG32_PTR_T)(0x38E00020 + 0x1000 * (v))))
|
||||
#define VICSWPRIORITYMASK(v) (*((REG32_PTR_T)(0x38E00024 + 0x1000 * (v))))
|
||||
#define VICPRIORITYDAISY(v) (*((REG32_PTR_T)(0x38E00028 + 0x1000 * (v))))
|
||||
#define VICVECTADDR(v, i) (*((REG32_PTR_T)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
|
||||
#define VICVECTPRIORITY(v, i) (*((REG32_PTR_T)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
|
||||
#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
|
||||
#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
|
||||
#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
|
||||
#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
|
||||
#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
|
||||
#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
|
||||
#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
|
||||
#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
|
||||
#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
|
||||
#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
|
||||
#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
|
||||
#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
|
||||
#define VIC0IRQSTATUS (*((REG32_PTR_T)(0x38E00000)))
|
||||
#define VIC0FIQSTATUS (*((REG32_PTR_T)(0x38E00004)))
|
||||
#define VIC0RAWINTR (*((REG32_PTR_T)(0x38E00008)))
|
||||
#define VIC0INTSELECT (*((REG32_PTR_T)(0x38E0000C)))
|
||||
#define VIC0INTENABLE (*((REG32_PTR_T)(0x38E00010)))
|
||||
#define VIC0INTENCLEAR (*((REG32_PTR_T)(0x38E00014)))
|
||||
#define VIC0SOFTINT (*((REG32_PTR_T)(0x38E00018)))
|
||||
#define VIC0SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0001C)))
|
||||
#define VIC0PROTECTION (*((REG32_PTR_T)(0x38E00020)))
|
||||
#define VIC0SWPRIORITYMASK (*((REG32_PTR_T)(0x38E00024)))
|
||||
#define VIC0PRIORITYDAISY (*((REG32_PTR_T)(0x38E00028)))
|
||||
#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
|
||||
#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
|
||||
#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
|
||||
|
|
@ -281,51 +279,51 @@
|
|||
#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
|
||||
#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
|
||||
#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
|
||||
#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
|
||||
#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
|
||||
#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
|
||||
#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
|
||||
#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
|
||||
#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
|
||||
#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
|
||||
#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
|
||||
#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
|
||||
#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
|
||||
#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
|
||||
#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
|
||||
#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
|
||||
#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
|
||||
#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
|
||||
#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
|
||||
#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
|
||||
#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
|
||||
#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
|
||||
#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
|
||||
#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
|
||||
#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
|
||||
#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
|
||||
#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
|
||||
#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
|
||||
#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
|
||||
#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
|
||||
#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
|
||||
#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
|
||||
#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
|
||||
#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
|
||||
#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
|
||||
#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
|
||||
#define VIC0VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E00200 + 4 * (i))))
|
||||
#define VIC0VECTPRIORITY0 (*((REG32_PTR_T)(0x38E00200)))
|
||||
#define VIC0VECTPRIORITY1 (*((REG32_PTR_T)(0x38E00204)))
|
||||
#define VIC0VECTPRIORITY2 (*((REG32_PTR_T)(0x38E00208)))
|
||||
#define VIC0VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0020C)))
|
||||
#define VIC0VECTPRIORITY4 (*((REG32_PTR_T)(0x38E00210)))
|
||||
#define VIC0VECTPRIORITY5 (*((REG32_PTR_T)(0x38E00214)))
|
||||
#define VIC0VECTPRIORITY6 (*((REG32_PTR_T)(0x38E00218)))
|
||||
#define VIC0VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0021C)))
|
||||
#define VIC0VECTPRIORITY8 (*((REG32_PTR_T)(0x38E00220)))
|
||||
#define VIC0VECTPRIORITY9 (*((REG32_PTR_T)(0x38E00224)))
|
||||
#define VIC0VECTPRIORITY10 (*((REG32_PTR_T)(0x38E00228)))
|
||||
#define VIC0VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0022C)))
|
||||
#define VIC0VECTPRIORITY12 (*((REG32_PTR_T)(0x38E00230)))
|
||||
#define VIC0VECTPRIORITY13 (*((REG32_PTR_T)(0x38E00234)))
|
||||
#define VIC0VECTPRIORITY14 (*((REG32_PTR_T)(0x38E00238)))
|
||||
#define VIC0VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0023C)))
|
||||
#define VIC0VECTPRIORITY16 (*((REG32_PTR_T)(0x38E00240)))
|
||||
#define VIC0VECTPRIORITY17 (*((REG32_PTR_T)(0x38E00244)))
|
||||
#define VIC0VECTPRIORITY18 (*((REG32_PTR_T)(0x38E00248)))
|
||||
#define VIC0VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0024C)))
|
||||
#define VIC0VECTPRIORITY20 (*((REG32_PTR_T)(0x38E00250)))
|
||||
#define VIC0VECTPRIORITY21 (*((REG32_PTR_T)(0x38E00254)))
|
||||
#define VIC0VECTPRIORITY22 (*((REG32_PTR_T)(0x38E00258)))
|
||||
#define VIC0VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0025C)))
|
||||
#define VIC0VECTPRIORITY24 (*((REG32_PTR_T)(0x38E00260)))
|
||||
#define VIC0VECTPRIORITY25 (*((REG32_PTR_T)(0x38E00264)))
|
||||
#define VIC0VECTPRIORITY26 (*((REG32_PTR_T)(0x38E00268)))
|
||||
#define VIC0VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0026C)))
|
||||
#define VIC0VECTPRIORITY28 (*((REG32_PTR_T)(0x38E00270)))
|
||||
#define VIC0VECTPRIORITY29 (*((REG32_PTR_T)(0x38E00274)))
|
||||
#define VIC0VECTPRIORITY30 (*((REG32_PTR_T)(0x38E00278)))
|
||||
#define VIC0VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0027C)))
|
||||
#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
|
||||
#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
|
||||
#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
|
||||
#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
|
||||
#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
|
||||
#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
|
||||
#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
|
||||
#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
|
||||
#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
|
||||
#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
|
||||
#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
|
||||
#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
|
||||
#define VIC1IRQSTATUS (*((REG32_PTR_T)(0x38E01000)))
|
||||
#define VIC1FIQSTATUS (*((REG32_PTR_T)(0x38E01004)))
|
||||
#define VIC1RAWINTR (*((REG32_PTR_T)(0x38E01008)))
|
||||
#define VIC1INTSELECT (*((REG32_PTR_T)(0x38E0100C)))
|
||||
#define VIC1INTENABLE (*((REG32_PTR_T)(0x38E01010)))
|
||||
#define VIC1INTENCLEAR (*((REG32_PTR_T)(0x38E01014)))
|
||||
#define VIC1SOFTINT (*((REG32_PTR_T)(0x38E01018)))
|
||||
#define VIC1SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0101C)))
|
||||
#define VIC1PROTECTION (*((REG32_PTR_T)(0x38E01020)))
|
||||
#define VIC1SWPRIORITYMASK (*((REG32_PTR_T)(0x38E01024)))
|
||||
#define VIC1PRIORITYDAISY (*((REG32_PTR_T)(0x38E01028)))
|
||||
#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
|
||||
#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
|
||||
#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
|
||||
|
|
@ -359,81 +357,81 @@
|
|||
#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
|
||||
#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
|
||||
#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
|
||||
#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
|
||||
#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
|
||||
#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
|
||||
#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
|
||||
#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
|
||||
#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
|
||||
#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
|
||||
#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
|
||||
#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
|
||||
#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
|
||||
#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
|
||||
#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
|
||||
#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
|
||||
#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
|
||||
#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
|
||||
#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
|
||||
#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
|
||||
#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
|
||||
#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
|
||||
#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
|
||||
#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
|
||||
#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
|
||||
#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
|
||||
#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
|
||||
#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
|
||||
#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
|
||||
#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
|
||||
#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
|
||||
#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
|
||||
#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
|
||||
#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
|
||||
#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
|
||||
#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
|
||||
#define VIC1VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E01200 + 4 * (i))))
|
||||
#define VIC1VECTPRIORITY0 (*((REG32_PTR_T)(0x38E01200)))
|
||||
#define VIC1VECTPRIORITY1 (*((REG32_PTR_T)(0x38E01204)))
|
||||
#define VIC1VECTPRIORITY2 (*((REG32_PTR_T)(0x38E01208)))
|
||||
#define VIC1VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0120C)))
|
||||
#define VIC1VECTPRIORITY4 (*((REG32_PTR_T)(0x38E01210)))
|
||||
#define VIC1VECTPRIORITY5 (*((REG32_PTR_T)(0x38E01214)))
|
||||
#define VIC1VECTPRIORITY6 (*((REG32_PTR_T)(0x38E01218)))
|
||||
#define VIC1VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0121C)))
|
||||
#define VIC1VECTPRIORITY8 (*((REG32_PTR_T)(0x38E01220)))
|
||||
#define VIC1VECTPRIORITY9 (*((REG32_PTR_T)(0x38E01224)))
|
||||
#define VIC1VECTPRIORITY10 (*((REG32_PTR_T)(0x38E01228)))
|
||||
#define VIC1VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0122C)))
|
||||
#define VIC1VECTPRIORITY12 (*((REG32_PTR_T)(0x38E01230)))
|
||||
#define VIC1VECTPRIORITY13 (*((REG32_PTR_T)(0x38E01234)))
|
||||
#define VIC1VECTPRIORITY14 (*((REG32_PTR_T)(0x38E01238)))
|
||||
#define VIC1VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0123C)))
|
||||
#define VIC1VECTPRIORITY16 (*((REG32_PTR_T)(0x38E01240)))
|
||||
#define VIC1VECTPRIORITY17 (*((REG32_PTR_T)(0x38E01244)))
|
||||
#define VIC1VECTPRIORITY18 (*((REG32_PTR_T)(0x38E01248)))
|
||||
#define VIC1VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0124C)))
|
||||
#define VIC1VECTPRIORITY20 (*((REG32_PTR_T)(0x38E01250)))
|
||||
#define VIC1VECTPRIORITY21 (*((REG32_PTR_T)(0x38E01254)))
|
||||
#define VIC1VECTPRIORITY22 (*((REG32_PTR_T)(0x38E01258)))
|
||||
#define VIC1VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0125C)))
|
||||
#define VIC1VECTPRIORITY24 (*((REG32_PTR_T)(0x38E01260)))
|
||||
#define VIC1VECTPRIORITY25 (*((REG32_PTR_T)(0x38E01264)))
|
||||
#define VIC1VECTPRIORITY26 (*((REG32_PTR_T)(0x38E01268)))
|
||||
#define VIC1VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0126C)))
|
||||
#define VIC1VECTPRIORITY28 (*((REG32_PTR_T)(0x38E01270)))
|
||||
#define VIC1VECTPRIORITY29 (*((REG32_PTR_T)(0x38E01274)))
|
||||
#define VIC1VECTPRIORITY30 (*((REG32_PTR_T)(0x38E01278)))
|
||||
#define VIC1VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0127C)))
|
||||
#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
|
||||
|
||||
|
||||
/////GPIO/////
|
||||
#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
|
||||
#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
|
||||
#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
|
||||
#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
|
||||
#define PUNC(i) (*((uint32_t volatile*)(0x3cf00010 + ((i) << 5))))
|
||||
#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
|
||||
#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
|
||||
#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
|
||||
#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
|
||||
#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
|
||||
#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
|
||||
#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
|
||||
#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
|
||||
#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
|
||||
#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
|
||||
#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
|
||||
#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
|
||||
#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
|
||||
#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
|
||||
#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
|
||||
#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
|
||||
#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
|
||||
#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
|
||||
#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
|
||||
#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
|
||||
#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
|
||||
#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
|
||||
#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
|
||||
#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
|
||||
#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
|
||||
#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
|
||||
#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
|
||||
#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
|
||||
#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
|
||||
#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
|
||||
#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
|
||||
#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
|
||||
#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
|
||||
#define PCON(i) (*((REG32_PTR_T)(0x3cf00000 + ((i) << 5))))
|
||||
#define PDAT(i) (*((REG32_PTR_T)(0x3cf00004 + ((i) << 5))))
|
||||
#define PUNA(i) (*((REG32_PTR_T)(0x3cf00008 + ((i) << 5))))
|
||||
#define PUNB(i) (*((REG32_PTR_T)(0x3cf0000c + ((i) << 5))))
|
||||
#define PUNC(i) (*((REG32_PTR_T)(0x3cf00010 + ((i) << 5))))
|
||||
#define PCON0 (*((REG32_PTR_T)(0x3cf00000)))
|
||||
#define PDAT0 (*((REG32_PTR_T)(0x3cf00004)))
|
||||
#define PCON1 (*((REG32_PTR_T)(0x3cf00020)))
|
||||
#define PDAT1 (*((REG32_PTR_T)(0x3cf00024)))
|
||||
#define PCON2 (*((REG32_PTR_T)(0x3cf00040)))
|
||||
#define PDAT2 (*((REG32_PTR_T)(0x3cf00044)))
|
||||
#define PCON3 (*((REG32_PTR_T)(0x3cf00060)))
|
||||
#define PDAT3 (*((REG32_PTR_T)(0x3cf00064)))
|
||||
#define PCON4 (*((REG32_PTR_T)(0x3cf00080)))
|
||||
#define PDAT4 (*((REG32_PTR_T)(0x3cf00084)))
|
||||
#define PCON5 (*((REG32_PTR_T)(0x3cf000a0)))
|
||||
#define PDAT5 (*((REG32_PTR_T)(0x3cf000a4)))
|
||||
#define PCON6 (*((REG32_PTR_T)(0x3cf000c0)))
|
||||
#define PDAT6 (*((REG32_PTR_T)(0x3cf000c4)))
|
||||
#define PCON7 (*((REG32_PTR_T)(0x3cf000e0)))
|
||||
#define PDAT7 (*((REG32_PTR_T)(0x3cf000e4)))
|
||||
#define PCON8 (*((REG32_PTR_T)(0x3cf00100)))
|
||||
#define PDAT8 (*((REG32_PTR_T)(0x3cf00104)))
|
||||
#define PCON9 (*((REG32_PTR_T)(0x3cf00120)))
|
||||
#define PDAT9 (*((REG32_PTR_T)(0x3cf00124)))
|
||||
#define PCONA (*((REG32_PTR_T)(0x3cf00140)))
|
||||
#define PDATA (*((REG32_PTR_T)(0x3cf00144)))
|
||||
#define PCONB (*((REG32_PTR_T)(0x3cf00160)))
|
||||
#define PDATB (*((REG32_PTR_T)(0x3cf00164)))
|
||||
#define PCONC (*((REG32_PTR_T)(0x3cf00180)))
|
||||
#define PDATC (*((REG32_PTR_T)(0x3cf00184)))
|
||||
#define PCOND (*((REG32_PTR_T)(0x3cf001a0)))
|
||||
#define PDATD (*((REG32_PTR_T)(0x3cf001a4)))
|
||||
#define PCONE (*((REG32_PTR_T)(0x3cf001c0)))
|
||||
#define PDATE (*((REG32_PTR_T)(0x3cf001c4)))
|
||||
#define PCONF (*((REG32_PTR_T)(0x3cf001e0)))
|
||||
#define PDATF (*((REG32_PTR_T)(0x3cf001e4)))
|
||||
#define GPIOCMD (*((REG32_PTR_T)(0x3cf00200)))
|
||||
|
||||
|
||||
/////SPI/////
|
||||
|
|
@ -446,111 +444,111 @@
|
|||
#define SPIDMA(i) ((i) == 2 ? 0xd : \
|
||||
(i) == 1 ? 0xf : \
|
||||
0x5)
|
||||
#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
|
||||
#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
|
||||
#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
|
||||
#define SPIPIN(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
|
||||
#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
|
||||
#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
|
||||
#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
|
||||
#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
|
||||
#define SPIDD(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) /* TBC */
|
||||
#define SPICTRL(i) (*((REG32_PTR_T)(SPIBASE(i))))
|
||||
#define SPISETUP(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x4)))
|
||||
#define SPISTATUS(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x8)))
|
||||
#define SPIPIN(i) (*((REG32_PTR_T)(SPIBASE(i) + 0xc)))
|
||||
#define SPITXDATA(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x10)))
|
||||
#define SPIRXDATA(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x20)))
|
||||
#define SPICLKDIV(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x30)))
|
||||
#define SPIRXLIMIT(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x34)))
|
||||
#define SPIDD(i) (*((REG32_PTR_T)(SPIBASE(i) + 0x38))) /* TBC */
|
||||
|
||||
|
||||
/////AES/////
|
||||
#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
|
||||
#define AESGO (*((uint32_t volatile*)(0x38c00004)))
|
||||
#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
|
||||
#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
|
||||
#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
|
||||
#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
|
||||
#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
|
||||
#define AESCONTROL (*((REG32_PTR_T)(0x38c00000)))
|
||||
#define AESGO (*((REG32_PTR_T)(0x38c00004)))
|
||||
#define AESUNKREG0 (*((REG32_PTR_T)(0x38c00008)))
|
||||
#define AESSTATUS (*((REG32_PTR_T)(0x38c0000c)))
|
||||
#define AESUNKREG1 (*((REG32_PTR_T)(0x38c00010)))
|
||||
#define AESKEYLEN (*((REG32_PTR_T)(0x38c00014)))
|
||||
#define AESOUTSIZE (*((REG32_PTR_T)(0x38c00018)))
|
||||
#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
|
||||
#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
|
||||
#define AESINSIZE (*((REG32_PTR_T)(0x38c00024)))
|
||||
#define AESINADDR (*((const void* volatile*)(0x38c00028)))
|
||||
#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
|
||||
#define AESAUXSIZE (*((REG32_PTR_T)(0x38c0002c)))
|
||||
#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
|
||||
#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
|
||||
#define AESKEY ((uint32_t volatile*)(0x38c0004c))
|
||||
#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
|
||||
#define AESIV ((uint32_t volatile*)(0x38c00074))
|
||||
#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
|
||||
#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
|
||||
#define AESSIZE3 (*((REG32_PTR_T)(0x38c00034)))
|
||||
#define AESKEY ((REG32_PTR_T)(0x38c0004c))
|
||||
#define AESTYPE (*((REG32_PTR_T)(0x38c0006c)))
|
||||
#define AESIV ((REG32_PTR_T)(0x38c00074))
|
||||
#define AESTYPE2 (*((REG32_PTR_T)(0x38c00088)))
|
||||
#define AESUNKREG2 (*((REG32_PTR_T)(0x38c0008c)))
|
||||
|
||||
|
||||
/////SHA1/////
|
||||
#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
|
||||
#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
|
||||
#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
|
||||
#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
|
||||
#define SHA1CONFIG (*((REG32_PTR_T)(0x38000000)))
|
||||
#define SHA1RESET (*((REG32_PTR_T)(0x38000004)))
|
||||
#define SHA1RESULT ((REG32_PTR_T)(0x38000020))
|
||||
#define SHA1DATAIN ((REG32_PTR_T)(0x38000040))
|
||||
|
||||
|
||||
/////LCD/////
|
||||
#define LCD_BASE (0x38300000)
|
||||
#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
|
||||
#define LCD_WCMD (*((uint32_t volatile*)(0x38300004)))
|
||||
#define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
|
||||
#define LCD_PHTIME (*((uint32_t volatile*)(0x38300020)))
|
||||
#define LCD_WDATA (*((uint32_t volatile*)(0x38300040)))
|
||||
#define LCD_CONFIG (*((REG32_PTR_T)(0x38300000)))
|
||||
#define LCD_WCMD (*((REG32_PTR_T)(0x38300004)))
|
||||
#define LCD_STATUS (*((REG32_PTR_T)(0x3830001c)))
|
||||
#define LCD_PHTIME (*((REG32_PTR_T)(0x38300020)))
|
||||
#define LCD_WDATA (*((REG32_PTR_T)(0x38300040)))
|
||||
|
||||
|
||||
/////ATA/////
|
||||
#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
|
||||
#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
|
||||
#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
|
||||
#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
|
||||
#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
|
||||
#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
|
||||
#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
|
||||
#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
|
||||
#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
|
||||
#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
|
||||
#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
|
||||
#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
|
||||
#define ATA_CONTROL (*((REG32_PTR_T)(0x38700000)))
|
||||
#define ATA_STATUS (*((REG32_PTR_T)(0x38700004)))
|
||||
#define ATA_COMMAND (*((REG32_PTR_T)(0x38700008)))
|
||||
#define ATA_SWRST (*((REG32_PTR_T)(0x3870000c)))
|
||||
#define ATA_IRQ (*((REG32_PTR_T)(0x38700010)))
|
||||
#define ATA_IRQ_MASK (*((REG32_PTR_T)(0x38700014)))
|
||||
#define ATA_CFG (*((REG32_PTR_T)(0x38700018)))
|
||||
#define ATA_MDMA_TIME (*((REG32_PTR_T)(0x38700028)))
|
||||
#define ATA_PIO_TIME (*((REG32_PTR_T)(0x3870002c)))
|
||||
#define ATA_UDMA_TIME (*((REG32_PTR_T)(0x38700030)))
|
||||
#define ATA_XFR_NUM (*((REG32_PTR_T)(0x38700034)))
|
||||
#define ATA_XFR_CNT (*((REG32_PTR_T)(0x38700038)))
|
||||
#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
|
||||
#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
|
||||
#define ATA_TBUF_SIZE (*((REG32_PTR_T)(0x38700040)))
|
||||
#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
|
||||
#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
|
||||
#define ATA_SBUF_SIZE (*((REG32_PTR_T)(0x38700048)))
|
||||
#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
|
||||
#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
|
||||
#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
|
||||
#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
|
||||
#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
|
||||
#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
|
||||
#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
|
||||
#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
|
||||
#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
|
||||
#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
|
||||
#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
|
||||
#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
|
||||
#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
|
||||
#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
|
||||
#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
|
||||
#define ATA_PIO_DTR (*((REG32_PTR_T)(0x38700054)))
|
||||
#define ATA_PIO_FED (*((REG32_PTR_T)(0x38700058)))
|
||||
#define ATA_PIO_SCR (*((REG32_PTR_T)(0x3870005c)))
|
||||
#define ATA_PIO_LLR (*((REG32_PTR_T)(0x38700060)))
|
||||
#define ATA_PIO_LMR (*((REG32_PTR_T)(0x38700064)))
|
||||
#define ATA_PIO_LHR (*((REG32_PTR_T)(0x38700068)))
|
||||
#define ATA_PIO_DVR (*((REG32_PTR_T)(0x3870006c)))
|
||||
#define ATA_PIO_CSD (*((REG32_PTR_T)(0x38700070)))
|
||||
#define ATA_PIO_DAD (*((REG32_PTR_T)(0x38700074)))
|
||||
#define ATA_PIO_READY (*((REG32_PTR_T)(0x38700078)))
|
||||
#define ATA_PIO_RDATA (*((REG32_PTR_T)(0x3870007c)))
|
||||
#define ATA_BUS_FIFO_STATUS (*((REG32_PTR_T)(0x38700080)))
|
||||
#define ATA_FIFO_STATUS (*((REG32_PTR_T)(0x38700084)))
|
||||
#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
|
||||
|
||||
|
||||
/////SDCI/////
|
||||
#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
|
||||
#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
|
||||
#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
|
||||
#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
|
||||
#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
|
||||
#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
|
||||
#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
|
||||
#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
|
||||
#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
|
||||
#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
|
||||
#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
|
||||
#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
|
||||
#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
|
||||
#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
|
||||
#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
|
||||
#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
|
||||
#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
|
||||
#define SDCI_CTRL (*((REG32_PTR_T)(0x38b00000)))
|
||||
#define SDCI_DCTRL (*((REG32_PTR_T)(0x38b00004)))
|
||||
#define SDCI_CMD (*((REG32_PTR_T)(0x38b00008)))
|
||||
#define SDCI_ARGU (*((REG32_PTR_T)(0x38b0000c)))
|
||||
#define SDCI_STATE (*((REG32_PTR_T)(0x38b00010)))
|
||||
#define SDCI_STAC (*((REG32_PTR_T)(0x38b00014)))
|
||||
#define SDCI_DSTA (*((REG32_PTR_T)(0x38b00018)))
|
||||
#define SDCI_FSTA (*((REG32_PTR_T)(0x38b0001c)))
|
||||
#define SDCI_RESP0 (*((REG32_PTR_T)(0x38b00020)))
|
||||
#define SDCI_RESP1 (*((REG32_PTR_T)(0x38b00024)))
|
||||
#define SDCI_RESP2 (*((REG32_PTR_T)(0x38b00028)))
|
||||
#define SDCI_RESP3 (*((REG32_PTR_T)(0x38b0002c)))
|
||||
#define SDCI_CDIV (*((REG32_PTR_T)(0x38b00030)))
|
||||
#define SDCI_SDIO_CSR (*((REG32_PTR_T)(0x38b00034)))
|
||||
#define SDCI_IRQ (*((REG32_PTR_T)(0x38b00038)))
|
||||
#define SDCI_IRQ_MASK (*((REG32_PTR_T)(0x38b0003c)))
|
||||
#define SDCI_DATA (*((REG32_PTR_T)(0x38b00040)))
|
||||
#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
|
||||
#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
|
||||
#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
|
||||
#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
|
||||
#define SDCI_DMASIZE (*((REG32_PTR_T)(0x38b00048)))
|
||||
#define SDCI_DMACOUNT (*((REG32_PTR_T)(0x38b0004c)))
|
||||
#define SDCI_RESET (*((REG32_PTR_T)(0x38b0006c)))
|
||||
|
||||
#define SDCI_CTRL_SDCIEN BIT(0)
|
||||
#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
|
||||
|
|
@ -714,14 +712,14 @@
|
|||
|
||||
|
||||
/////CLICKWHEEL/////
|
||||
#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
|
||||
#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
|
||||
#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
|
||||
#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
|
||||
#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
|
||||
#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
|
||||
#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
|
||||
#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
|
||||
#define WHEEL00 (*((REG32_PTR_T)(0x3C200000)))
|
||||
#define WHEEL04 (*((REG32_PTR_T)(0x3C200004)))
|
||||
#define WHEEL08 (*((REG32_PTR_T)(0x3C200008)))
|
||||
#define WHEEL0C (*((REG32_PTR_T)(0x3C20000C)))
|
||||
#define WHEEL10 (*((REG32_PTR_T)(0x3C200010)))
|
||||
#define WHEELINT (*((REG32_PTR_T)(0x3C200014)))
|
||||
#define WHEELRX (*((REG32_PTR_T)(0x3C200018)))
|
||||
#define WHEELTX (*((REG32_PTR_T)(0x3C20001C)))
|
||||
|
||||
|
||||
/////I2S/////
|
||||
|
|
@ -729,15 +727,15 @@
|
|||
(i) == 1 ? CLOCKGATE_I2S1 : \
|
||||
CLOCKGATE_I2S0)
|
||||
|
||||
#define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000)))
|
||||
#define I2STXCON (*((volatile uint32_t*)(0x3CA00004)))
|
||||
#define I2STXCOM (*((volatile uint32_t*)(0x3CA00008)))
|
||||
#define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010)))
|
||||
#define I2SRXCON (*((volatile uint32_t*)(0x3CA00030)))
|
||||
#define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034)))
|
||||
#define I2SRXDB (*((volatile uint32_t*)(0x3CA00038)))
|
||||
#define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C)))
|
||||
#define I2SCLKDIV (*((volatile uint32_t*)(0x3CA00040)))
|
||||
#define I2SCLKCON (*((REG32_PTR_T)(0x3CA00000)))
|
||||
#define I2STXCON (*((REG32_PTR_T)(0x3CA00004)))
|
||||
#define I2STXCOM (*((REG32_PTR_T)(0x3CA00008)))
|
||||
#define I2STXDB0 (*((REG32_PTR_T)(0x3CA00010)))
|
||||
#define I2SRXCON (*((REG32_PTR_T)(0x3CA00030)))
|
||||
#define I2SRXCOM (*((REG32_PTR_T)(0x3CA00034)))
|
||||
#define I2SRXDB (*((REG32_PTR_T)(0x3CA00038)))
|
||||
#define I2SSTATUS (*((REG32_PTR_T)(0x3CA0003C)))
|
||||
#define I2SCLKDIV (*((REG32_PTR_T)(0x3CA00040)))
|
||||
|
||||
|
||||
/////UART/////
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue