len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-09 05:05:20 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

Ingenic targets:

Browse source 
* Get audio working (only noise atm)
 * Clean up some stuff in USB


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19329 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2008-12-04 19:44:03 +00:00
parent c848d2dd99
commit 7ea9e31658
3 changed files with 48 additions and 45 deletions
Download patch file Download diff file Expand all files Collapse all files

57
firmware/target/mips/ingenic_jz47xx/codec-jz4740.c
View file

@ -32,50 +32,52 @@ static int IS_WRITE_PCM;
static void i2s_codec_set_samplerate(unsigned short rate); static void i2s_codec_set_samplerate(unsigned short rate);
static void i2s_codec_clear(void) static void i2s_codec_reset(void)
{ {
REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
udelay(10);
REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP );
} }
static void i2s_codec_init(void) static void i2s_codec_init(void)
{ {
__aic_enable(); __aic_enable();
__aic_select_i2s();
__i2s_internal_codec(); __i2s_internal_codec();
__i2s_as_slave();
__i2s_select_i2s();
__aic_select_i2s();
__i2s_set_oss_sample_size(16); __aic_disable_byteswap();
__aic_disable_unsignadj();
__aic_disable_mono2stereo();
REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | i2s_codec_reset();
ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); /* reset */
udelay(10);
REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL |
ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP |
ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
//REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6));
REG_ICDC_CDCCR1 &= 0xfffffffc; //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
| ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6));
REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
mdelay(15); mdelay(15);
REG_ICDC_CDCCR1 &= 0xffecffff; REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVR | ICDC_CDCCR1_VRCGL | ICDC_CDCCR1_VRCGH);
REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG); REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG);
mdelay(600); mdelay(600);
REG_ICDC_CDCCR1 &= 0xfff7ecff; REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_HPCG | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP);
mdelay(2); mdelay(2);
/* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */ /* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */
REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~((1 << 29) | (1 << 28) | (1 << 26) | (1 << 27) | (1 << 14))) | ((1 << 24) | (1 << 25)); REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC |
ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_EDAC
| ICDC_CDCCR1_SW2ON);
REG_ICDC_CDCCR2 = ((REG_ICDC_CDCCR2 & ~(0x3)) | 3); REG_ICDC_CDCCR2 |= 3;
i2s_codec_set_samplerate(44100);
HP_on_off_flag = 0; /* HP is off */ HP_on_off_flag = 0; /* HP is off */
} }
@ -296,7 +298,6 @@ void audiohw_mute(bool mute)
void audiohw_preinit(void) void audiohw_preinit(void)
{ {
i2s_codec_init();
} }
void audiohw_postinit(void) void audiohw_postinit(void)
@ -306,5 +307,5 @@ void audiohw_postinit(void)
void audiohw_init(void) void audiohw_init(void)
{ {
i2s_codec_init();
} }

25
firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
View file

@ -35,6 +35,11 @@
void pcm_postinit(void) void pcm_postinit(void)
{ {
audiohw_postinit(); audiohw_postinit();
/* playback sample:16 bits, burst:16 bytes */
__i2s_set_transmit_trigger(4);
__i2s_set_oss_sample_size(16);
pcm_apply_settings(); pcm_apply_settings();
} }
@ -53,11 +58,6 @@ void pcm_play_dma_init(void)
audiohw_init(); audiohw_init();
} }
void pcm_apply_settings(void)
{
/* TODO */
}
void pcm_set_frequency(unsigned int frequency) void pcm_set_frequency(unsigned int frequency)
{ {
(void) frequency; (void) frequency;
@ -71,10 +71,8 @@ void pcm_set_frequency(unsigned int frequency)
static void play_start_pcm(void) static void play_start_pcm(void)
{ {
pcm_apply_settings(); __i2s_enable_transmit_dma();
__i2s_enable_replay();
__aic_enable_transmit_dma();
__aic_enable_replay();
REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN; REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
} }
@ -83,18 +81,18 @@ static void play_stop_pcm(void)
{ {
REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN; REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) | DMAC_DCCSR_HLT) & ~DMAC_DCCSR_EN;
__aic_disable_transmit_dma(); __i2s_disable_transmit_dma();
__aic_disable_replay(); __i2s_disable_replay();
} }
void pcm_play_dma_start(const void *addr, size_t size) void pcm_play_dma_start(const void *addr, size_t size)
{ {
REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = 0; REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES;
REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr); REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr);
REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);
REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size; REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size;
REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT; REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = ( DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32 REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = ( DMAC_DCMD_SAI| DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32
| DMAC_DCMD_TIE); | DMAC_DCMD_TIE);
play_start_pcm(); play_start_pcm();
@ -134,7 +132,6 @@ void pcm_play_dma_pause(bool pause)
play_stop_pcm(); play_stop_pcm();
else else
play_start_pcm(); play_start_pcm();
} }
#ifdef HAVE_RECORDING #ifdef HAVE_RECORDING

11
firmware/target/mips/ingenic_jz47xx/usb-jz4740.c
View file

@ -28,8 +28,11 @@
#include "jz4740.h" #include "jz4740.h"
#include "thread.h" #include "thread.h"
//#define DEBUGF printf #if 1
#define DEBUGF printf
#else
#define DEBUGF(...) #define DEBUGF(...)
#endif
#define USB_EP0_IDLE 0 #define USB_EP0_IDLE 0
#define USB_EP0_RX 1 #define USB_EP0_RX 1
@ -86,7 +89,7 @@ static void readFIFO(struct usb_endpoint *ep, unsigned int size)
register unsigned char *ptr = (unsigned char*)EP_PTR(ep); register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
register unsigned int *ptr32 = (unsigned int*)ptr; register unsigned int *ptr32 = (unsigned int*)ptr;
register unsigned int s = size / 4; register unsigned int s = size >> 2;
register unsigned int x; register unsigned int x;
if(size > 0) if(size > 0)
@ -333,7 +336,7 @@ void usb_drv_stall(int endpoint, bool stall, bool in)
select_endpoint(endpoint); select_endpoint(endpoint);
if(endpoint == 0) if(endpoint == EP_CONTROL)
{ {
if(stall) if(stall)
REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL; REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL;
@ -458,6 +461,8 @@ int usb_drv_recv(int endpoint, void* ptr, int length)
void usb_drv_set_test_mode(int mode) void usb_drv_set_test_mode(int mode)
{ {
DEBUGF("usb_drv_set_test_mode(%d)", mode);
switch(mode) switch(mode)
{ {
case 0: case 0: