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iPod Nano 2G NAND: Use the correct bit names for FMCSTAT

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Looks like they were always off-by-one, so the wrong functions have been used to rectify this bug. This is now properly fixed.

No changes to the ipodnano2g binaries (bootloader, rockbox)

Change-Id: I19fe1b89f9e5d722f7e877d60f68fc3275c3642a
This commit is contained in:
Vencislav Atanasov 2025-04-18 16:35:57 +03:00 • committed by Solomon Peachy
parent a0bfcd77c8
commit 7e2019fde9
2 changed files with 21 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

8
firmware/export/s5l87xx.h
View file

@ -931,10 +931,10 @@
#define FMCTRL1_DOWRITEDATA (1 << 2)
#define FMCTRL1_CLEARWFIFO (1 << 6)
#define FMCTRL1_CLEARRFIFO (1 << 7)
#define FMCSTAT_RBB (1 << 0)
#define FMCSTAT_RBBDONE (1 << 1)
#define FMCSTAT_CMDDONE (1 << 2)
#define FMCSTAT_ADDRDONE (1 << 3)
#define FMCSTAT_RBBDONE (1 << 0)
#define FMCSTAT_CMDDONE (1 << 1)
#define FMCSTAT_ADDRDONE (1 << 2)
#define FMCSTAT_TRANSDONE (1 << 3)
#define FMCSTAT_BANK0READY (1 << 4)
#define FMCSTAT_BANK1READY (1 << 5)
#define FMCSTAT_BANK2READY (1 << 6)

25
firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
View file

@ -153,6 +153,15 @@ static uint32_t nand_wait_addrdone(void)
return 0;
}
static uint32_t nand_wait_transdone(void)
{
long timeout = current_tick + HZ / 50;
while (!(FMCSTAT & FMCSTAT_TRANSDONE))
if (nand_timeout(timeout)) return 1;
FMCSTAT = FMCSTAT_TRANSDONE;
return 0;
}
static uint32_t nand_wait_chip_ready(uint32_t bank)
{
long timeout = current_tick + HZ / 50;
@ -171,7 +180,7 @@ static void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
static uint32_t nand_send_cmd(uint32_t cmd)
{
FMCMD = cmd;
return nand_wait_rbbdone();
return nand_wait_cmddone();
}
static uint32_t nand_send_address(uint32_t page, uint32_t offset)
@ -180,7 +189,7 @@ static uint32_t nand_send_address(uint32_t page, uint32_t offset)
FMADDR0 = (page << 16) | offset;
FMADDR1 = (page >> 16) & 0xFF;
FMCTRL1 = FMCTRL1_DOTRANSADDR;
return nand_wait_cmddone();
return nand_wait_addrdone();
}
uint32_t nand_reset(uint32_t bank)
@ -206,7 +215,7 @@ static uint32_t nand_wait_status_ready(uint32_t bank)
if (nand_timeout(timeout)) return 1;
FMDNUM = 0;
FMCTRL1 = FMCTRL1_DOREADDATA;
if (nand_wait_addrdone()) return 1;
if (nand_wait_transdone()) return 1;
if ((FMFIFO & NAND_STATUS_READY)) break;
FMCTRL1 = FMCTRL1_CLEARRFIFO;
}
@ -238,7 +247,7 @@ static uint32_t nand_transfer_data_collect(uint32_t direction)
while ((DMAALLST & DMAALLST_DMABUSY3))
if (nand_timeout(timeout)) return 1;
if (!direction) commit_discard_dcache();
if (nand_wait_addrdone()) return 1;
if (nand_wait_transdone()) return 1;
if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
else FMCTRL1 = FMCTRL1_CLEARRFIFO;
return 0;
@ -308,10 +317,10 @@ static uint32_t nand_get_chip_type(uint32_t bank)
FMANUM = 0;
FMADDR0 = 0;
FMCTRL1 = FMCTRL1_DOTRANSADDR;
if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFC);
if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFC);
FMDNUM = 4;
FMCTRL1 = FMCTRL1_DOREADDATA;
if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFB);
if (nand_wait_transdone()) return nand_unlock(0xFFFFFFFB);
result = FMFIFO;
FMCTRL1 = FMCTRL1_CLEARRFIFO;
return nand_unlock(result);
@ -494,7 +503,7 @@ uint32_t nand_block_erase(uint32_t bank, uint32_t page)
FMANUM = 2;
FMADDR0 = page;
FMCTRL1 = FMCTRL1_DOTRANSADDR;
if (nand_wait_cmddone()) return nand_unlock(1);
if (nand_wait_addrdone()) return nand_unlock(1);
if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
if (nand_wait_status_ready(bank)) return nand_unlock(1);
return nand_unlock(0);
@ -690,7 +699,7 @@ static uint32_t nand_block_erase_fast(uint32_t page)
FMANUM = 2;
FMADDR0 = page;
FMCTRL1 = FMCTRL1_DOTRANSADDR;
if (nand_wait_cmddone())
if (nand_wait_addrdone())
{
rc |= 1 << i;
continue;