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Sansa AMS: Revert 4 bit widebus
For some reason 4 bit widebus is creating issues when writing to the .rockbox directory so revert 4 bit widebus and the revision to the write delay that was added as a fix. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24054 a1c6a512-1295-4272-9138-f99709370657
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1 changed files with 2 additions and 31 deletions
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@ -376,31 +376,6 @@ static int sd_init_card(const int drive)
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return -10;
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return -10;
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mci_delay();
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mci_delay();
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#ifndef BOOTLOADER
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/* Switch to to 4 bit widebus mode */
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if(sd_wait_for_state(drive, SD_TRAN) < 0)
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return -11;
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mci_delay();
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/* CMD55 */
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if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL))
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return -12;
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mci_delay();
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/* ACMD6 */
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if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ARG, NULL))
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return -13;
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mci_delay();
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/* CMD55 */
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if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL))
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return -14;
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mci_delay();
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/* ACMD42 */
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if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ARG, NULL))
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return -15;
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mci_delay();
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/* Now that card is widebus make controller widebus also */
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MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
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#endif
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/*
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/*
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* enable bank switching
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* enable bank switching
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* without issuing this command, we only have access to 1/4 of the blocks
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* without issuing this command, we only have access to 1/4 of the blocks
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@ -775,17 +750,13 @@ static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
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dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
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dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
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(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
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(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
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DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
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DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
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#if defined(HAVE_MULTIDRIVE)
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/*Small delay for writes prevents data crc failures at lower freqs*/
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/*Small delay for writes prevents data crc failures at lower freqs*/
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if(!hs_card)
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if((drive == SD_SLOT_AS3525) && !hs_card)
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{
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{
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int write_delay = 125;
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int write_delay = 125;
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while(write_delay--);
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while(write_delay--);
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}
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}
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#else
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int write_delay = 125;
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while(write_delay--);
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#endif
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}
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}
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else
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else
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dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
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dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
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