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Beginning of an M:Robe 500i port. Currently only in the bootloader stage. Needs another piece of code to start the boot process - will be in the wiki.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14763 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun
parent
a80c0e8b83
commit
7b97fe21c0
34 changed files with 2651 additions and 93 deletions
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@ -33,9 +33,8 @@ start:
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
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#ifndef BOOTLOADER
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#ifndef DEBUG
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#if !defined(BOOTLOADER) || (CONFIG_CPU == DM320)
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#if !defined(DEBUG)
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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@ -52,8 +51,11 @@ start:
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ldr r0, =fiq_handler
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str r0, [r1, #28]
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#endif
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#ifndef STUB
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#endif
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#if !defined(BOOTLOADER)
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#if !defined(STUB)
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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@ -98,6 +100,159 @@ start:
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/* Code for ARM bootloader targets other than iPod go here */
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#if CONFIG_CPU == S3C2440
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/* Proper initialization pulled from 0x5070 */
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/* BWSCON
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* Reserved 0
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* Bank 0:
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* Bus width 10 (16 bit)
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* Bank 1:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 2:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 3:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Use UB/LB 1
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* Bank 4:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Use UB/LB 1
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* Bank 5:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 6:
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* Buswidth 10 (32 bit)
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* Disable wait 0
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* Not using UB/LB 0
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* Bank 7:
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* Buswidth 00 (8 bit)
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* Disable wait 0
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* Not using UB/LB 0
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*/
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ldr r2,=0x01055102
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mov r1, #0x48000000
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str r2, [r1]
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/* BANKCON0
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 2 clocks 10
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* Chip selection hold time: 1 clock 10
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* Access cycle: 8 clocks 101
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* Chip select setup time: 1 clock 01
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* Address setup time: 0 clock 00
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*/
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ldr r2,=0x00000D60
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str r2, [r1, #4]
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/* BANKCON1
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 0 clocks 00
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* Chip selection hold time: 0 clock 00
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* Access cycle: 1 clocks 000
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* Chip select setup time: 0 clocks 00
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* Address setup time: 0 clocks 00
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*/
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ldr r2,=0x00000000
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str r2, [r1, #8]
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/* BANKCON2
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* Pagemode: normal (1 data) 00
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* Pagemode access cycle: 2 clocks 00
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* Address hold: 2 clocks 10
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* Chip selection hold time: 2 clocks 10
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* Access cycle: 14 clocks 111
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* Chip select setup time: 4 clocks 11
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* Address setup time: 0 clocks 00
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*/
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ldr r2,=0x00001FA0
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str r2, [r1, #0xC]
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/* BANKCON3 */
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ldr r2,=0x00001D80
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str r2, [r1, #0x10]
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/* BANKCON4 */
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str r2, [r1, #0x14]
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/* BANKCON5 */
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ldr r2,=0x00000000
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str r2, [r1, #0x18]
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/* BANKCON6/7
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* SCAN: 9 bit 01
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* Trcd: 3 clocks 01
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* Tcah: 0 clock 00
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* Tcoh: 0 clock 00
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* Tacc: 1 clock 000
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* Tcos: 0 clock 00
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* Tacs: 0 clock 00
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* MT: Sync DRAM 11
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*/
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ldr r2,=0x00018005
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str r2, [r1, #0x1C]
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/* BANKCON7 */
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str r2, [r1, #0x20]
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/* REFRESH */
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ldr r2,=0x00980501
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str r2, [r1, #0x24]
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/* BANKSIZE
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* BK76MAP: 32M/32M 000
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* Reserved: 0 0 (was 1)
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* SCLK_EN: always 1 (was 0)
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* SCKE_EN: disable 0
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* Reserved: 0 0
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* BURST_EN: enabled 1
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*/
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ldr r2,=0x00000090
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str r2, [r1, #0x28]
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/* MRSRB6 */
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ldr r2,=0x00000030
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str r2, [r1, #0x2C]
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/* MRSRB7 */
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str r2, [r1, #0x30]
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#if 0
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/* This next part I am not sure of the purpose */
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/* GPACON */
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mov r2,#0x01FFFCFF
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str r2,=0x56000000
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/* GPADAT */
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mov r2,#0x01FFFEFF
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str r2,=0x56000004
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/* MRSRB6 */
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mov r2,#0x00000000
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str r2,=0x4800002C
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/* GPADAT */
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ldr r2,=0x01FFFFFF
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mov r1, #0x56000000
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str r2, [r1, #4]
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/* MRSRB6 */
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mov r2,#0x00000030
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str r2,=0x4800002C
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/* GPACON */
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mov r2,#0x01FFFFFF
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str r2,=0x56000000
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/* End of the unknown */
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#endif
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/* get the high part of our execute address */
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ldr r2, =0xffffff00
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and r4, pc, r2
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@ -116,6 +271,28 @@ start:
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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start_loc:
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bl main
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#else
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/* get the high part of our execute address */
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ldr r2, =0xffffff00
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and r4, pc, r2
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/* Copy bootloader to safe area - 0x01900000 */
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mov r5, #0x00900000
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add r5, r5, #0x01000000
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ldr r6, = _dataend
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sub r0, r6, r5 /* length of loader */
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add r0, r4, r0 /* r0 points to start of loader */
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1:
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cmp r5, r6
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ldrcc r2, [r4], #4
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strcc r2, [r5], #4
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bcc 1b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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start_loc:
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bl main
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#endif
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