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https://github.com/Rockbox/rockbox.git
synced 2025-10-13 18:17:39 -04:00
Removed the Gmini 120 and Gmini SP code. These ports are dead, unfortunately.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11504 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
270cb0b681
commit
780f79e7a4
36 changed files with 46 additions and 1533 deletions
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@ -152,243 +152,7 @@ bool detect_flashed_rockbox(void)
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#endif /* HAVE_FLASHED_ROCKBOX */
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}
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#if CONFIG_CPU == TCC730
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void* volatile interrupt_vector[16] __attribute__ ((section(".idata")));
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static void ddma_wait_idle(void) __attribute__ ((section (".icode")));
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static void ddma_wait_idle(void)
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{
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/* TODO: power saving trick: set the CPU freq to 22MHz
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while doing the busy wait after a disk dma access.
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(Used by Archos) */
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do {
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} while ((DDMACOM & 3) != 0);
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}
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void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num)
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__attribute__ ((section (".icode")));
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void ddma_transfer(int dir, int mem, void* intAddr, long extAddr, int num) {
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int irq = set_irq_level(1);
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ddma_wait_idle();
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long externalAddress = (long) extAddr;
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long internalAddress = ((long) intAddr) & 0xFFFF;
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/* HW wants those two in word units. */
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num /= 2;
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externalAddress /= 2;
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DDMACFG = (dir << 1) | (mem << 2);
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DDMAIADR = internalAddress;
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DDMAEADR = externalAddress;
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DDMANUM = num;
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DDMACOM |= 0x4; /* start */
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ddma_wait_idle(); /* wait for completion */
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set_irq_level(irq);
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}
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static void ddma_wait_idle_noicode(void)
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{
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do {
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} while ((DDMACOM & 3) != 0);
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}
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static void ddma_transfer_noicode(int dir, int mem, long intAddr, long extAddr, int num) {
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int irq = set_irq_level(1);
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ddma_wait_idle_noicode();
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long externalAddress = (long) extAddr;
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long internalAddress = (long) intAddr;
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/* HW wants those two in word units. */
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num /= 2;
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externalAddress /= 2;
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DDMACFG = (dir << 1) | (mem << 2);
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DDMAIADR = internalAddress;
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DDMAEADR = externalAddress;
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DDMANUM = num;
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DDMACOM |= 0x4; /* start */
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ddma_wait_idle_noicode(); /* wait for completion */
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set_irq_level(irq);
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}
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/* Some linker-defined symbols */
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extern int icodecopy;
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extern int icodesize;
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extern int icodestart;
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/* change the a PLL frequency */
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void set_pll_freq(int pll_index, long freq_out) {
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volatile unsigned int* plldata;
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volatile unsigned char* pllcon;
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if (pll_index == 0) {
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plldata = &PLL0DATA;
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pllcon = &PLL0CON;
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} else {
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plldata = &PLL1DATA;
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pllcon = &PLL1CON;
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}
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/* VC0 is 32768 Hz */
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#define VC0FREQ (32768L)
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unsigned m = (freq_out / VC0FREQ) - 2;
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/* TODO: if m is too small here, use the divider bits [0,1] */
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*plldata = m << 2;
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*pllcon |= 0x1; /* activate */
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do {
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} while ((*pllcon & 0x2) == 0); /* wait for stabilization */
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}
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int smsc_version(void) {
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int v;
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int* smsc_ver_addr = (int*)0x4C20;
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__asm__ ("ldc %0, @%1" : "=r"(v) : "a"(smsc_ver_addr));
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v &= 0xFF;
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if (v < 4 || v == 0xFF) {
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return 3;
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}
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return v;
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}
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void smsc_delay() {
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int i;
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/* FIXME: tune the delay.
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Delay doesn't depend on CPU speed in Archos' firmware.
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*/
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for (i = 0; i < 100; i++) {
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}
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}
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static void extra_init(void) {
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/* Power on stuff */
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P1 |= 0x07;
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P1CON |= 0x1f;
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/* P5 conf
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* lines 0, 1 & 4 are digital, other analog. :
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*/
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P5CON = 0xec;
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P6CON = 0x19;
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/* P7 conf
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nothing to do: all are inputs
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(reset value of the register is good)
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*/
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/* SMSC chip config (?) */
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P10CON |= 0x20;
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P6 &= 0xF7;
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P10 &= 0x20;
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smsc_delay();
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if (smsc_version() < 4) {
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P6 |= 0x08;
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P10 |= 0x20;
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}
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}
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void set_cpu_frequency(long frequency) {
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/* Enable SDRAM refresh, at least 15MHz */
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if (frequency < cpu_frequency)
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MIUDCNT = 0x800 | (frequency * 15/1000000L - 1);
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set_pll_freq(0, frequency);
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PLL0CON |= 0x4; /* use as CPU clock */
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cpu_frequency = frequency;
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/* wait states and such not changed by Archos. (!?) */
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/* Enable SDRAM refresh, 15MHz. */
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MIUDCNT = 0x800 | (frequency * 15/1000000L - 1);
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tick_start(1000/HZ);
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/* TODO: when uart is done; sync uart freq */
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}
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/* called by crt0 */
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void system_init(void)
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{
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/* Disable watchdog */
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WDTEN = 0xA5;
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/****************
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* GPIO ports
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*/
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/* keep alive (?) -- clear the bit to prevent crash at start (??) */
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P8 = 0x00;
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P8CON = 0x01;
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/* smsc chip init (?) */
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P10 = 0x20;
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P6 = 0x08;
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P10CON = 0x20;
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P6CON = 0x08;
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/********
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* CPU
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*/
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/* PLL0 (cpu osc. frequency) */
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/* set_cpu_frequency(CPU_FREQ); */
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/*******************
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* configure S(D)RAM
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*/
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/************************
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* Copy .icode section to icram
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*/
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ddma_transfer_noicode(0, 0, 0x40, (long)&icodecopy, (int)&icodesize);
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/***************************
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* Interrupts
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*/
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/* priorities ? */
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/* mask */
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IMR0 = 0;
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IMR1 = 0;
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/* IRQ0 BT INT */
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/* IRQ1 RTC INT */
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/* IRQ2 TA INT */
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/* IRQ3 TAOV INT */
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/* IRQ4 TB INT */
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/* IRQ5 TBOV INT */
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/* IRQ6 TC INT */
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/* IRQ7 TCOV INT */
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/* IRQ8 USB INT */
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/* IRQ9 PPIC INT */
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/* IRQ10 UART_Rx/UART_Err/ UART_tx INT */
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/* IRQ11 IIC INT */
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/* IRQ12 SIO INT */
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/* IRQ13 IIS0 INT */
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/* IRQ14 IIS1 INT */
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/* IRQ15 */
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extra_init();
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}
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void system_reboot (void)
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{
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#elif CONFIG_CPU == SH7034
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#if CONFIG_CPU == SH7034
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#include "led.h"
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#include "system.h"
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#include "rolo.h"
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