len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-08 12:45:26 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

AMSv2: DBOP frequency divided by 2

Browse source 
After setting new PCLK (96 Mhz) we have too high DBOP (96 / 16 = 6 MHz).
According to datasheet DBOP should be maximum 4 MHz.

Change-Id: I1cbec054f41a76a6f18eadccb902c5b174ad6e3a
This commit is contained in:
Mihail Zenkov 2016-03-27 21:06:27 +00:00
parent ee567d8579
commit 77a35363c5
1 changed files with 4 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
firmware/target/arm/as3525/clock-target.h
View file

@ -86,6 +86,8 @@
#define AS3525_DRAM_FREQ 96000000 /* Initial DRAM frequency */
#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */
#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/2) /* DBOP divided from PCLK freq */
#else
/* AS3525v1 */
@ -113,12 +115,11 @@
#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */
#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */
/* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */
#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */
#endif /* CONFIG_CPU == AS3525v2 */
#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */
#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */
/** ****************************************************************************/