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This is a big chunk of code necessary to prepare for Gigabeat F flash loading and and implementation of rolo. There should be no noticible changes for the user. A new bootloader is not needed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17213 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun
parent
68afa9dc34
commit
7510335fc4
8 changed files with 563 additions and 349 deletions
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@ -20,70 +20,111 @@
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#include "mmu-arm.h"
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#include "panic.h"
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#define SECTION_ADDRESS_MASK (-1 << 20)
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#define MB (1 << 20)
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void ttb_init(void) {
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unsigned int* ttbPtr;
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/* must be 16Kb (0x4000) aligned - clear out the TTB */
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for (ttbPtr=TTB_BASE; ttbPtr<(TTB_SIZE+TTB_BASE); ttbPtr++)
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{
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*ttbPtr = 0;
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}
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/* Set the TTB base address */
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asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (TTB_BASE));
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/* Set all domains to manager status */
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asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (0xFFFFFFFF));
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void __attribute__((naked)) ttb_init(void) {
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asm volatile
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(
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"mcr p15, 0, %[ttbB], c2, c0, 0 \n" /* Set the TTB base address */
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"mcr p15, 0, %[ffff], c3, c0, 0 \n" /* Set all domains to manager status */
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"bx lr \n"
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:
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: [ttbB] "r" (TTB_BASE),
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[ffff] "r" (0xFFFFFFFF)
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);
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}
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void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
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unsigned int* ttbPtr;
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int i;
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int section_no;
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void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb, int flags) {
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#if 0 /* This code needs to be fixed and the C needs to be replaced to ensure that stack is not used */
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asm volatile
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(
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/* pa &= (-1 << 20); // align to 1MB */
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"mov r0, r0, lsr #20 \n"
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"mov r0, r0, lsl #20 \n"
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section_no = va >> 20; /* sections are 1Mb size */
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ttbPtr = TTB_BASE + section_no;
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pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
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for(i=0; i<mb; i++, pa += MB) {
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*(ttbPtr + i) =
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pa |
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1 << 10 | /* superuser - r/w, user - no access */
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0 << 5 | /* domain 0th */
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1 << 4 | /* should be "1" */
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cache_flags |
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1 << 1; /* Section signature */
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}
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}
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/* pa |= (flags | 0x412);
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* bit breakdown:
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* 10: superuser - r/w, user - no access
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* 4: should be "1"
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* 3,2: Cache flags (flags (r3))
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* 1: Section signature
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*/
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void enable_mmu(void) {
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int regread;
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asm volatile(
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"MRC p15, 0, %r0, c1, c0, 0\n" /* Read reg1, control register */
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: /* outputs */
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"=r"(regread)
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: /* inputs */
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: /* clobbers */
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"r0"
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"orr r0, r0, r3 \n"
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"orr r0, r0, #0x410 \n"
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"orr r0, r0, #0x2 \n"
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:
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:
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);
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if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
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clean_dcache(); /* If so we need to clean the DCache before invalidating below */
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register int *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */
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asm volatile("mov r0, #0\n"
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"mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
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asm volatile
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(
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/* unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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* sections are 1MB size
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*/
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"mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
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"mov r1, r1, lsr #20 \n"
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"add r1, %[ttbB], r1, lsl #0x2 \n"
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"mrc p15, 0, r0, c1, c0, 0\n"
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"orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
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"orr r0, r0, #1<<2\n" /* enable dcache */
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"orr r0, r0, #1<<12\n" /* enable icache */
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"mcr p15, 0, r0, c1, c0, 0" : : : "r0");
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asm volatile("nop \n nop \n nop \n nop");
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/* Add MB to pa, flags are already present in pa, but addition
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* should not effect them
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*
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* #define MB (1 << 20)
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* for( ; mb>0; mb--, pa += MB)
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* {
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* *(ttbPtr++) = pa;
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* }
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* #undef MB
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*/
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"cmp r2, #0 \n"
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"bxle lr \n"
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"loop: \n"
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"str r0, [r1], #4 \n"
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"add r0, r0, #0x100000 \n"
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"sub r2, r2, #0x01 \n"
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"bne loop \n"
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"bx lr \n"
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:
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: [ttbB] "r" (ttb_base) /* This /HAS/ to be in r3 */
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);
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(void) pa;
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(void) va;
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(void) mb;
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(void) flags;
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#else
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pa &= (-1 << 20);
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pa |= (flags | 0x412);
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unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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#define MB (1 << 20)
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for( ; mb>0; mb--, pa += MB)
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{
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*(ttbPtr++) = pa;
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}
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#undef MB
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#endif
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}
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void __attribute__((naked)) enable_mmu(void) {
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asm volatile(
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c8, c7, 0 \n" /* invalidate TLB */
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"mcr p15, 0, r0, c7, c7,0 \n" /* invalidate both icache and dcache */
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"mrc p15, 0, r0, c1, c0, 0 \n"
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"orr r0, r0, #1 \n" /* enable mmu bit, icache and dcache */
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"orr r0, r0, #1<<2 \n" /* enable dcache */
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"orr r0, r0, #1<<12 \n" /* enable icache */
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"mcr p15, 0, r0, c1, c0, 0 \n"
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"nop \n"
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"nop \n"
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"nop \n"
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"nop \n"
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"bx lr \n"
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:
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:
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: "r0"
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);
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}
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#if CONFIG_CPU == IMX31L
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@ -105,35 +146,36 @@ void invalidate_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
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unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
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asm volatile(
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"inv_start: \n"
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"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"bne inv_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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"inv_start: \n"
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"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"bne inv_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
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: : "r" (addr), "r" (end)
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);
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}
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#endif
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@ -239,41 +281,20 @@ void __attribute__((naked)) clean_dcache(void)
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/* Cleans entire DCache */
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void clean_dcache(void)
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{
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unsigned int index, addr;
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unsigned int index, addr, low;
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for(index = 0; index <= 63; index++) {
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addr = (0 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (1 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (2 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (3 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (4 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (5 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (6 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (7 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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for(index = 0; index <= 63; index++)
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{
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for(low = 0;low <= 7; low++)
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{
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addr = (index << 26) | (low << 5);
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asm volatile
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(
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"mcr p15, 0, %[addr], c7, c10, 2 \n" /* Clean this entry by index */
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:
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: [addr] "r" (addr)
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);
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}
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}
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}
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#endif
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