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Sansa Clip+: use correct SSP settings

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24559 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-02-08 03:36:53 +00:00
parent fbc59e2e28
commit 71e77aaff8
2 changed files with 10 additions and 3 deletions
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7
firmware/target/arm/as3525/clock-target.h
View file

@ -141,6 +141,8 @@
#define AS3525_I2C_FREQ 400000
#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
#define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
#define AS3525_SSP_FREQ 12000000
#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
@ -179,6 +181,11 @@
#error I2C frequency is too low : clock divider will not fit !
#endif
/* AS3525_SSP_FREQ */
#if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
#error SSP frequency is too low : clock divider will not fit !
#endif
/* AS3525_SD_IDENT_FREQ */
#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
#error SD IDENTIFICATION frequency is too low : clock divider will not fit !

6
firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
View file

@ -97,9 +97,9 @@ static void lcd_hw_init(void)
#elif defined(SANSA_CLIPPLUS)
CGU_PERI |= CGU_SSP_CLOCK_ENABLE;
SSP_CPSR; /* No clock prescale */
SSP_CR0 = 0 | 7; /* Motorola SPI frame format, 8 bits */
SSP_CR1 = 1<<1; /* SSP Operation enabled */
SSP_CPSR = AS3525_SSP_PRESCALER; /* OF = 0x10 */
SSP_CR0 = (1<<7) | (1<<6) | 7; /* Motorola SPI frame format, 8 bits */
SSP_CR1 = (1<<3) | (1<<1); /* SSP Operation enabled */
SSP_IMSC = 0; /* No interrupts */
#endif
}