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usb-s3c6400x.[ch], button-clickwheel.c: Move s5l8701-specific parts to where they belong, prepare for s5l8702
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28800 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
8e1021bd4c
commit
70447b529c
4 changed files with 369 additions and 322 deletions
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@ -571,6 +571,8 @@
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#define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */
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#define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */
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#define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */
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#define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */
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#define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */
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#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */
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#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
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@ -686,9 +688,9 @@
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#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */
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/* Hardware AES crypto unit - S5L8701 only */
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#if CONFIG_CPU==S5L8701
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/* Hardware AES crypto unit - S5L8701 only */
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#define ICONSRCPND (*(REG32_PTR_T)(0x39C00000))
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#define ICONINTPND (*(REG32_PTR_T)(0x39C00010))
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#define AESCONTROL (*(REG32_PTR_T)(0x39800000))
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@ -709,4 +711,20 @@
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#define HASHRESULT ((REG32_PTR_T)(0x3C600020))
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#define HASHDATAIN ((REG32_PTR_T)(0x3C600040))
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/* Clickwheel controller - S5L8701 only */
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#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
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#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
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#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
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#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
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#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
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#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
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#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
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#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
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/* Synopsys OTG - S5L8701 only */
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#define OTGBASE 0x38800000
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#define PHYBASE 0x3C400000
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#define SYNOPSYSOTG_CLOCK 0
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#define SYNOPSYSOTG_AHBCFG 0x27
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#endif /* CONFIG_CPU==S5L8701 */
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@ -22,320 +22,322 @@
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#define USB_S3C6400X_H
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#define REG32_PTR_T volatile uint32_t *
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/*** OTG PHY CONTROL REGISTERS ***/
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#define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000)
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#define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004)
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#define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008)
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#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
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/*** OTG LINK CORE REGISTERS ***/
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/* Core Global Registers */
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#define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000)
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#define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004)
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#define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008)
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#define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C)
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#define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010)
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#define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014)
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#define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018)
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#define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C)
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#define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020)
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#define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024)
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#define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028)
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#define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C)
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#define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100)
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#define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x)
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#define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104)
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#define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108)
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#define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C)
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#define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110)
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#define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114)
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#define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118)
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#define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C)
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#define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120)
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#define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124)
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#define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128)
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#define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C)
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#define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130)
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#define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134)
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#define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138)
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#define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C)
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#define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000)))
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#define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004)))
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#define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008)))
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#define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C)))
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#define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010)))
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#define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014)))
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#define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018)))
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#define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C)))
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#define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020)))
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#define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024)))
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#define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028)))
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#define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C)))
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#define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100)))
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#define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
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#define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104)))
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#define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108)))
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#define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C)))
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#define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110)))
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#define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114)))
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#define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118)))
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#define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C)))
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#define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120)))
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#define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124)))
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#define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128)))
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#define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C)))
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#define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130)))
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#define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134)))
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#define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138)))
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#define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C)))
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/*** HOST MODE REGISTERS ***/
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/* Host Global Registers */
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#define HCFG *(REG32_PTR_T)(OTGBASE + 0x400)
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#define HFIR *(REG32_PTR_T)(OTGBASE + 0x404)
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#define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408)
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#define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410)
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#define HAINT *(REG32_PTR_T)(OTGBASE + 0x414)
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#define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418)
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#define HCFG (*((uint32_t volatile*)(OTGBASE + 0x400)))
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#define HFIR (*((uint32_t volatile*)(OTGBASE + 0x404)))
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#define HFNUM (*((uint32_t volatile*)(OTGBASE + 0x408)))
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#define HPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x410)))
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#define HAINT (*((uint32_t volatile*)(OTGBASE + 0x414)))
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#define HAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x418)))
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/* Host Port Control and Status Registers */
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#define HPRT *(REG32_PTR_T)(OTGBASE + 0x440)
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#define HPRT (*((uint32_t volatile*)(OTGBASE + 0x440)))
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/* Host Channel-Specific Registers */
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#define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x)
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#define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x)
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#define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x)
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#define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x)
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#define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x)
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#define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x)
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#define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500)
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#define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504)
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#define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508)
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#define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C)
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#define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510)
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#define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514)
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#define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520)
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#define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524)
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#define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528)
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#define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C)
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#define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530)
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#define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534)
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#define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540)
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#define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544)
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#define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548)
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#define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C)
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#define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550)
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#define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554)
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#define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560)
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#define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564)
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#define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568)
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#define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C)
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#define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570)
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#define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574)
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#define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580)
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#define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584)
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#define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588)
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#define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C)
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#define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590)
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#define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594)
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#define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0)
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#define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4)
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#define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8)
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#define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC)
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#define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0)
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#define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4)
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#define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0)
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#define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4)
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#define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8)
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#define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC)
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#define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0)
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#define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4)
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#define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0)
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#define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4)
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#define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8)
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#define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC)
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#define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0)
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#define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4)
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#define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600)
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#define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604)
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#define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608)
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#define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C)
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#define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610)
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#define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614)
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#define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620)
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#define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624)
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#define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628)
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#define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C)
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#define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630)
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#define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634)
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#define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640)
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#define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644)
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#define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648)
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#define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C)
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#define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650)
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#define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654)
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#define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660)
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#define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664)
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#define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668)
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#define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C)
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#define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670)
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#define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674)
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#define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680)
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#define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684)
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#define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688)
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#define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C)
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#define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690)
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#define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694)
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#define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0)
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#define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4)
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#define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8)
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#define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC)
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#define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0)
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#define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4)
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#define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0)
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#define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4)
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#define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8)
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#define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC)
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#define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0)
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#define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4)
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#define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0)
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#define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4)
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#define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8)
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#define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC)
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#define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0)
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#define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4)
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#define HCCHAR(x) (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
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#define HCSPLT(x) (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
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#define HCINT(x) (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
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#define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
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#define HCTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
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#define HCDMA(x) (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
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#define HCCHAR0 (*((uint32_t volatile*)(OTGBASE + 0x500)))
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#define HCSPLT0 (*((uint32_t volatile*)(OTGBASE + 0x504)))
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#define HCINT0 (*((uint32_t volatile*)(OTGBASE + 0x508)))
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#define HCINTMSK0 (*((uint32_t volatile*)(OTGBASE + 0x50C)))
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#define HCTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x510)))
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#define HCDMA0 (*((uint32_t volatile*)(OTGBASE + 0x514)))
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#define HCCHAR1 (*((uint32_t volatile*)(OTGBASE + 0x520)))
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#define HCSPLT1 (*((uint32_t volatile*)(OTGBASE + 0x524)))
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#define HCINT1 (*((uint32_t volatile*)(OTGBASE + 0x528)))
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#define HCINTMSK1 (*((uint32_t volatile*)(OTGBASE + 0x52C)))
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#define HCTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x530)))
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#define HCDMA1 (*((uint32_t volatile*)(OTGBASE + 0x534)))
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#define HCCHAR2 (*((uint32_t volatile*)(OTGBASE + 0x540)))
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#define HCSPLT2 (*((uint32_t volatile*)(OTGBASE + 0x544)))
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#define HCINT2 (*((uint32_t volatile*)(OTGBASE + 0x548)))
|
||||
#define HCINTMSK2 (*((uint32_t volatile*)(OTGBASE + 0x54C)))
|
||||
#define HCTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x550)))
|
||||
#define HCDMA2 (*((uint32_t volatile*)(OTGBASE + 0x554)))
|
||||
#define HCCHAR3 (*((uint32_t volatile*)(OTGBASE + 0x560)))
|
||||
#define HCSPLT3 (*((uint32_t volatile*)(OTGBASE + 0x564)))
|
||||
#define HCINT3 (*((uint32_t volatile*)(OTGBASE + 0x568)))
|
||||
#define HCINTMSK3 (*((uint32_t volatile*)(OTGBASE + 0x56C)))
|
||||
#define HCTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x570)))
|
||||
#define HCDMA3 (*((uint32_t volatile*)(OTGBASE + 0x574)))
|
||||
#define HCCHAR4 (*((uint32_t volatile*)(OTGBASE + 0x580)))
|
||||
#define HCSPLT4 (*((uint32_t volatile*)(OTGBASE + 0x584)))
|
||||
#define HCINT4 (*((uint32_t volatile*)(OTGBASE + 0x588)))
|
||||
#define HCINTMSK4 (*((uint32_t volatile*)(OTGBASE + 0x58C)))
|
||||
#define HCTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x590)))
|
||||
#define HCDMA4 (*((uint32_t volatile*)(OTGBASE + 0x594)))
|
||||
#define HCCHAR5 (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
|
||||
#define HCSPLT5 (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
|
||||
#define HCINT5 (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
|
||||
#define HCINTMSK5 (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
|
||||
#define HCTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
|
||||
#define HCDMA5 (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
|
||||
#define HCCHAR6 (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
|
||||
#define HCSPLT6 (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
|
||||
#define HCINT6 (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
|
||||
#define HCINTMSK6 (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
|
||||
#define HCTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
|
||||
#define HCDMA6 (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
|
||||
#define HCCHAR7 (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
|
||||
#define HCSPLT7 (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
|
||||
#define HCINT7 (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
|
||||
#define HCINTMSK7 (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
|
||||
#define HCTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
|
||||
#define HCDMA7 (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
|
||||
#define HCCHAR8 (*((uint32_t volatile*)(OTGBASE + 0x600)))
|
||||
#define HCSPLT8 (*((uint32_t volatile*)(OTGBASE + 0x604)))
|
||||
#define HCINT8 (*((uint32_t volatile*)(OTGBASE + 0x608)))
|
||||
#define HCINTMSK8 (*((uint32_t volatile*)(OTGBASE + 0x60C)))
|
||||
#define HCTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x610)))
|
||||
#define HCDMA8 (*((uint32_t volatile*)(OTGBASE + 0x614)))
|
||||
#define HCCHAR9 (*((uint32_t volatile*)(OTGBASE + 0x620)))
|
||||
#define HCSPLT9 (*((uint32_t volatile*)(OTGBASE + 0x624)))
|
||||
#define HCINT9 (*((uint32_t volatile*)(OTGBASE + 0x628)))
|
||||
#define HCINTMSK9 (*((uint32_t volatile*)(OTGBASE + 0x62C)))
|
||||
#define HCTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x630)))
|
||||
#define HCDMA9 (*((uint32_t volatile*)(OTGBASE + 0x634)))
|
||||
#define HCCHAR10 (*((uint32_t volatile*)(OTGBASE + 0x640)))
|
||||
#define HCSPLT10 (*((uint32_t volatile*)(OTGBASE + 0x644)))
|
||||
#define HCINT10 (*((uint32_t volatile*)(OTGBASE + 0x648)))
|
||||
#define HCINTMSK10 (*((uint32_t volatile*)(OTGBASE + 0x64C)))
|
||||
#define HCTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x650)))
|
||||
#define HCDMA10 (*((uint32_t volatile*)(OTGBASE + 0x654)))
|
||||
#define HCCHAR11 (*((uint32_t volatile*)(OTGBASE + 0x660)))
|
||||
#define HCSPLT11 (*((uint32_t volatile*)(OTGBASE + 0x664)))
|
||||
#define HCINT11 (*((uint32_t volatile*)(OTGBASE + 0x668)))
|
||||
#define HCINTMSK11 (*((uint32_t volatile*)(OTGBASE + 0x66C)))
|
||||
#define HCTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x670)))
|
||||
#define HCDMA11 (*((uint32_t volatile*)(OTGBASE + 0x674)))
|
||||
#define HCCHAR12 (*((uint32_t volatile*)(OTGBASE + 0x680)))
|
||||
#define HCSPLT12 (*((uint32_t volatile*)(OTGBASE + 0x684)))
|
||||
#define HCINT12 (*((uint32_t volatile*)(OTGBASE + 0x688)))
|
||||
#define HCINTMSK12 (*((uint32_t volatile*)(OTGBASE + 0x68C)))
|
||||
#define HCTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x690)))
|
||||
#define HCDMA12 (*((uint32_t volatile*)(OTGBASE + 0x694)))
|
||||
#define HCCHAR13 (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
|
||||
#define HCSPLT13 (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
|
||||
#define HCINT13 (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
|
||||
#define HCINTMSK13 (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
|
||||
#define HCTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
|
||||
#define HCDMA13 (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
|
||||
#define HCCHAR14 (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
|
||||
#define HCSPLT14 (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
|
||||
#define HCINT14 (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
|
||||
#define HCINTMSK14 (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
|
||||
#define HCTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
|
||||
#define HCDMA14 (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
|
||||
#define HCCHAR15 (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
|
||||
#define HCSPLT15 (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
|
||||
#define HCINT15 (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
|
||||
#define HCINTMSK15 (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
|
||||
#define HCTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
|
||||
#define HCDMA15 (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
|
||||
|
||||
/*** DEVICE MODE REGISTERS ***/
|
||||
/* Device Global Registers */
|
||||
#define DCFG *(REG32_PTR_T)(OTGBASE + 0x800)
|
||||
#define DCTL *(REG32_PTR_T)(OTGBASE + 0x804)
|
||||
#define DSTS *(REG32_PTR_T)(OTGBASE + 0x808)
|
||||
#define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810)
|
||||
#define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814)
|
||||
#define DAINT *(REG32_PTR_T)(OTGBASE + 0x818)
|
||||
#define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C)
|
||||
#define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820)
|
||||
#define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824)
|
||||
#define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828)
|
||||
#define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C)
|
||||
#define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830)
|
||||
#define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834)
|
||||
#define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800)))
|
||||
#define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804)))
|
||||
#define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808)))
|
||||
#define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810)))
|
||||
#define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814)))
|
||||
#define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818)))
|
||||
#define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C)))
|
||||
#define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820)))
|
||||
#define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824)))
|
||||
#define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828)))
|
||||
#define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C)))
|
||||
#define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830)))
|
||||
#define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834)))
|
||||
|
||||
/* Device Logical IN Endpoint-Specific Registers */
|
||||
#define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x)
|
||||
#define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x)
|
||||
#define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x)
|
||||
#define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x)
|
||||
#define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900)
|
||||
#define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908)
|
||||
#define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910)
|
||||
#define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914)
|
||||
#define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920)
|
||||
#define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928)
|
||||
#define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930)
|
||||
#define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934)
|
||||
#define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940)
|
||||
#define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948)
|
||||
#define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950)
|
||||
#define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954)
|
||||
#define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960)
|
||||
#define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968)
|
||||
#define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970)
|
||||
#define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974)
|
||||
#define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980)
|
||||
#define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988)
|
||||
#define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990)
|
||||
#define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994)
|
||||
#define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0)
|
||||
#define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8)
|
||||
#define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0)
|
||||
#define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4)
|
||||
#define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0)
|
||||
#define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8)
|
||||
#define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0)
|
||||
#define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4)
|
||||
#define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0)
|
||||
#define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8)
|
||||
#define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0)
|
||||
#define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4)
|
||||
#define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00)
|
||||
#define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08)
|
||||
#define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10)
|
||||
#define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14)
|
||||
#define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20)
|
||||
#define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28)
|
||||
#define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30)
|
||||
#define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34)
|
||||
#define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40)
|
||||
#define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48)
|
||||
#define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50)
|
||||
#define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54)
|
||||
#define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60)
|
||||
#define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68)
|
||||
#define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70)
|
||||
#define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74)
|
||||
#define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80)
|
||||
#define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88)
|
||||
#define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90)
|
||||
#define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94)
|
||||
#define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0)
|
||||
#define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8)
|
||||
#define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0)
|
||||
#define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4)
|
||||
#define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0)
|
||||
#define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8)
|
||||
#define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0)
|
||||
#define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4)
|
||||
#define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0)
|
||||
#define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8)
|
||||
#define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0)
|
||||
#define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4)
|
||||
#define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x))))
|
||||
#define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x))))
|
||||
#define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x))))
|
||||
#define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x))))
|
||||
#define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900)))
|
||||
#define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908)))
|
||||
#define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910)))
|
||||
#define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914)))
|
||||
#define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920)))
|
||||
#define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928)))
|
||||
#define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930)))
|
||||
#define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934)))
|
||||
#define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940)))
|
||||
#define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948)))
|
||||
#define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950)))
|
||||
#define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954)))
|
||||
#define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960)))
|
||||
#define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968)))
|
||||
#define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970)))
|
||||
#define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974)))
|
||||
#define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980)))
|
||||
#define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988)))
|
||||
#define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990)))
|
||||
#define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994)))
|
||||
#define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0)))
|
||||
#define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8)))
|
||||
#define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0)))
|
||||
#define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4)))
|
||||
#define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0)))
|
||||
#define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8)))
|
||||
#define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0)))
|
||||
#define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4)))
|
||||
#define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0)))
|
||||
#define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8)))
|
||||
#define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0)))
|
||||
#define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4)))
|
||||
#define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00)))
|
||||
#define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08)))
|
||||
#define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10)))
|
||||
#define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14)))
|
||||
#define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20)))
|
||||
#define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28)))
|
||||
#define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30)))
|
||||
#define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34)))
|
||||
#define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40)))
|
||||
#define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48)))
|
||||
#define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50)))
|
||||
#define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54)))
|
||||
#define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60)))
|
||||
#define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68)))
|
||||
#define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70)))
|
||||
#define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74)))
|
||||
#define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80)))
|
||||
#define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88)))
|
||||
#define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90)))
|
||||
#define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94)))
|
||||
#define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0)))
|
||||
#define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8)))
|
||||
#define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0)))
|
||||
#define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4)))
|
||||
#define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0)))
|
||||
#define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8)))
|
||||
#define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0)))
|
||||
#define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4)))
|
||||
#define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0)))
|
||||
#define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8)))
|
||||
#define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0)))
|
||||
#define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4)))
|
||||
|
||||
/* Device Logical OUT Endpoint-Specific Registers */
|
||||
#define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x)
|
||||
#define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x)
|
||||
#define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x)
|
||||
#define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x)
|
||||
#define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00)
|
||||
#define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08)
|
||||
#define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10)
|
||||
#define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14)
|
||||
#define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20)
|
||||
#define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28)
|
||||
#define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30)
|
||||
#define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34)
|
||||
#define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40)
|
||||
#define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48)
|
||||
#define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50)
|
||||
#define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54)
|
||||
#define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60)
|
||||
#define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68)
|
||||
#define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70)
|
||||
#define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74)
|
||||
#define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80)
|
||||
#define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88)
|
||||
#define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90)
|
||||
#define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94)
|
||||
#define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0)
|
||||
#define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8)
|
||||
#define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0)
|
||||
#define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4)
|
||||
#define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0)
|
||||
#define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8)
|
||||
#define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0)
|
||||
#define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4)
|
||||
#define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0)
|
||||
#define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8)
|
||||
#define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0)
|
||||
#define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4)
|
||||
#define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00)
|
||||
#define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08)
|
||||
#define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10)
|
||||
#define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14)
|
||||
#define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20)
|
||||
#define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28)
|
||||
#define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30)
|
||||
#define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34)
|
||||
#define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40)
|
||||
#define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48)
|
||||
#define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50)
|
||||
#define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54)
|
||||
#define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60)
|
||||
#define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68)
|
||||
#define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70)
|
||||
#define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74)
|
||||
#define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80)
|
||||
#define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88)
|
||||
#define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90)
|
||||
#define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94)
|
||||
#define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0)
|
||||
#define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8)
|
||||
#define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0)
|
||||
#define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4)
|
||||
#define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0)
|
||||
#define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8)
|
||||
#define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0)
|
||||
#define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4)
|
||||
#define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0)
|
||||
#define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8)
|
||||
#define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0)
|
||||
#define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4)
|
||||
#define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x))))
|
||||
#define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x))))
|
||||
#define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x))))
|
||||
#define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x))))
|
||||
#define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00)))
|
||||
#define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08)))
|
||||
#define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10)))
|
||||
#define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14)))
|
||||
#define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20)))
|
||||
#define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28)))
|
||||
#define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30)))
|
||||
#define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34)))
|
||||
#define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40)))
|
||||
#define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48)))
|
||||
#define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50)))
|
||||
#define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54)))
|
||||
#define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60)))
|
||||
#define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68)))
|
||||
#define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70)))
|
||||
#define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74)))
|
||||
#define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80)))
|
||||
#define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88)))
|
||||
#define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90)))
|
||||
#define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94)))
|
||||
#define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0)))
|
||||
#define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8)))
|
||||
#define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0)))
|
||||
#define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4)))
|
||||
#define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0)))
|
||||
#define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8)))
|
||||
#define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0)))
|
||||
#define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4)))
|
||||
#define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0)))
|
||||
#define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8)))
|
||||
#define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0)))
|
||||
#define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4)))
|
||||
#define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00)))
|
||||
#define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08)))
|
||||
#define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10)))
|
||||
#define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14)))
|
||||
#define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20)))
|
||||
#define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28)))
|
||||
#define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30)))
|
||||
#define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34)))
|
||||
#define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40)))
|
||||
#define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48)))
|
||||
#define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50)))
|
||||
#define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54)))
|
||||
#define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60)))
|
||||
#define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68)))
|
||||
#define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70)))
|
||||
#define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74)))
|
||||
#define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80)))
|
||||
#define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88)))
|
||||
#define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90)))
|
||||
#define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94)))
|
||||
#define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0)))
|
||||
#define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8)))
|
||||
#define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0)))
|
||||
#define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4)))
|
||||
#define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0)))
|
||||
#define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8)))
|
||||
#define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0)))
|
||||
#define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4)))
|
||||
#define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0)))
|
||||
#define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8)))
|
||||
#define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0)))
|
||||
#define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4)))
|
||||
|
||||
/* Power and Clock Gating Register */
|
||||
#define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00)
|
||||
#define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00)))
|
||||
|
||||
|
||||
#endif /* USB_S3C6400X_H */
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
#include "serial.h"
|
||||
#include "power.h"
|
||||
#include "powermgmt.h"
|
||||
#if defined(IPOD_NANO2G)
|
||||
#if defined(IPOD_NANO2G) || defined(IPOD_6G)
|
||||
#include "pmu-target.h"
|
||||
#endif
|
||||
|
||||
|
|
@ -49,18 +49,8 @@
|
|||
|
||||
#ifdef CPU_PP
|
||||
#define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x7000c140))
|
||||
#elif CONFIG_CPU==S5L8701
|
||||
#define PCON15 (*((volatile uint32_t*)(0x3CF000F0)))
|
||||
#define PUNK15 (*((volatile uint32_t*)(0x3CF000FC)))
|
||||
#define WHEEL00 (*((volatile uint32_t*)(0x3C200000)))
|
||||
#define WHEEL04 (*((volatile uint32_t*)(0x3C200004)))
|
||||
#define WHEEL08 (*((volatile uint32_t*)(0x3C200008)))
|
||||
#define WHEEL0C (*((volatile uint32_t*)(0x3C20000C)))
|
||||
#define WHEEL10 (*((volatile uint32_t*)(0x3C200010)))
|
||||
#define WHEELINT (*((volatile uint32_t*)(0x3C200014)))
|
||||
#define WHEELRX (*((volatile uint32_t*)(0x3C200018)))
|
||||
#define WHEELTX (*((volatile uint32_t*)(0x3C20001C)))
|
||||
#define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x3c200018))
|
||||
#elif CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
|
||||
#define CLICKWHEEL_DATA WHEELRX
|
||||
#else
|
||||
#error CPU architecture not supported!
|
||||
#endif
|
||||
|
|
@ -93,7 +83,7 @@ int int_btn = BUTTON_NONE;
|
|||
static bool send_events = true;
|
||||
#endif
|
||||
|
||||
#if CONFIG_CPU==S5L8701
|
||||
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
|
||||
static struct wakeup button_init_wakeup;
|
||||
#endif
|
||||
|
||||
|
|
@ -265,7 +255,7 @@ static inline int ipod_4g_button_read(void)
|
|||
}
|
||||
|
||||
}
|
||||
#if CONFIG_CPU==S5L8701
|
||||
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
|
||||
else if ((status & 0x8000FFFF) == 0x8000023A)
|
||||
{
|
||||
if (status & 0x00010000)
|
||||
|
|
@ -345,7 +335,7 @@ bool headphones_inserted(void)
|
|||
return (GPIOA_INPUT_VAL & 0x80)?true:false;
|
||||
}
|
||||
#else
|
||||
void INT_SPI(void)
|
||||
void INT_WHEEL(void)
|
||||
{
|
||||
int clickwheel_events = WHEELINT;
|
||||
|
||||
|
|
@ -359,6 +349,7 @@ void INT_SPI(void)
|
|||
|
||||
void s5l_clickwheel_init(void)
|
||||
{
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCONEXT &= ~1;
|
||||
PCON15 = (PCON15 & ~0xFFFF0000) | 0x22220000;
|
||||
PUNK15 = 0xF0;
|
||||
|
|
@ -370,24 +361,35 @@ void s5l_clickwheel_init(void)
|
|||
WHEELTX = 0x8000023A;
|
||||
WHEEL04 |= 1;
|
||||
PDAT10 &= ~2;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
//TODO: Implement
|
||||
#endif
|
||||
}
|
||||
|
||||
void button_init_device(void)
|
||||
{
|
||||
wakeup_init(&button_init_wakeup);
|
||||
#if CONFIG_CPU==S5L8701
|
||||
INTMSK |= (1<<26);
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
//TODO: Implement
|
||||
#endif
|
||||
s5l_clickwheel_init();
|
||||
wakeup_wait(&button_init_wakeup, HZ / 10);
|
||||
}
|
||||
|
||||
bool button_hold(void)
|
||||
{
|
||||
return ((PDAT14 & (1 << 6)) == 0);
|
||||
//TODO: Implement
|
||||
//return ((PDAT14 & (1 << 6)) == 0);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool headphones_inserted(void)
|
||||
{
|
||||
return ((PDAT14 & (1 << 5)) != 0);
|
||||
//TODO: Implement
|
||||
//return ((PDAT14 & (1 << 5)) == 0);
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -419,6 +421,8 @@ int button_read_device(void)
|
|||
WHEEL00 = 0;
|
||||
WHEEL10 = 0;
|
||||
PWRCONEXT |= 1;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
//TODO: Implement
|
||||
#endif
|
||||
}
|
||||
else
|
||||
|
|
@ -430,6 +434,8 @@ int button_read_device(void)
|
|||
#elif CONFIG_CPU==S5L8701
|
||||
pmu_ldo_power_on(1); /* enable clickwheel power supply */
|
||||
s5l_clickwheel_init();
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
//TODO: Implement
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,15 +24,13 @@
|
|||
#include "usb-target.h"
|
||||
#include "usb_drv.h"
|
||||
|
||||
#define OTGBASE 0x38800000
|
||||
#define PHYBASE 0x3C400000
|
||||
#include "usb-s3c6400x.h"
|
||||
|
||||
#include "cpu.h"
|
||||
#include "system.h"
|
||||
#include "kernel.h"
|
||||
#include "panic.h"
|
||||
|
||||
#include "usb-s3c6400x.h"
|
||||
|
||||
#ifdef HAVE_USBSTACK
|
||||
#include "usb_ch9.h"
|
||||
#include "usb_core.h"
|
||||
|
|
@ -72,7 +70,7 @@ static void reset_endpoints(int reinit)
|
|||
DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */
|
||||
DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size:
|
||||
64 Bytes, 1 Packet, 1 Setup Packet */
|
||||
DOEPDMA0 = (uint32_t)&ctrlreq;
|
||||
DOEPDMA0 = &ctrlreq;
|
||||
DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */
|
||||
if (reinit)
|
||||
{
|
||||
|
|
@ -139,10 +137,13 @@ static void usb_reset(void)
|
|||
DCTL = 0x802; /* Soft Disconnect */
|
||||
|
||||
OPHYPWR = 0; /* PHY: Power up */
|
||||
OPHYUNK1 = 1;
|
||||
OPHYUNK2 = 0xE3F;
|
||||
OPHYCLK = SYNOPSYSOTG_CLOCK;
|
||||
ORSTCON = 1; /* PHY: Assert Software Reset */
|
||||
for (i = 0; i < 50; i++);
|
||||
ORSTCON = 0; /* PHY: Deassert Software Reset */
|
||||
OPHYCLK = 0; /* PHY: 48MHz clock */
|
||||
OPHYUNK3 = 0x600;
|
||||
|
||||
GRSTCTL = 1; /* OTG: Assert Software Reset */
|
||||
while (GRSTCTL & 1); /* Wait for OTG to ack reset */
|
||||
|
|
@ -150,7 +151,7 @@ static void usb_reset(void)
|
|||
|
||||
GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */
|
||||
GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */
|
||||
GAHBCFG = 0x27; /* OTG AHB config: Unmask ints, burst length 4, DMA on */
|
||||
GAHBCFG = SYNOPSYSOTG_AHBCFG;
|
||||
GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */
|
||||
|
||||
DCFG = 4; /* Address 0 */
|
||||
|
|
@ -375,12 +376,16 @@ void usb_drv_stall(int endpoint, bool stall, bool in)
|
|||
void usb_drv_init(void)
|
||||
{
|
||||
/* Enable USB clock */
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON &= ~0x4000;
|
||||
PWRCONEXT &= ~0x800;
|
||||
PCGCCTL = 0;
|
||||
|
||||
/* unmask irq */
|
||||
INTMSK |= INTMSK_USB_OTG;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) &= ~0x4;
|
||||
PWRCON(1) &= ~0x8;
|
||||
VIC0INTENABLE |= 1 << 19;
|
||||
#endif
|
||||
PCGCCTL = 0;
|
||||
|
||||
/* reset the beast */
|
||||
usb_reset();
|
||||
|
|
@ -394,8 +399,13 @@ void usb_drv_exit(void)
|
|||
PCGCCTL = 1; /* Shut down PHY clock */
|
||||
OPHYPWR = 0xF; /* PHY: Power down */
|
||||
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON |= 0x4000;
|
||||
PWRCONEXT |= 0x800;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) |= 0x4;
|
||||
PWRCON(1) |= 0x8;
|
||||
#endif
|
||||
}
|
||||
|
||||
void usb_init_device(void)
|
||||
|
|
@ -406,10 +416,16 @@ void usb_init_device(void)
|
|||
|
||||
/* Power up the core clocks to allow writing
|
||||
to some registers needed to power it down */
|
||||
PCGCCTL = 0;
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON &= ~0x4000;
|
||||
PWRCONEXT &= ~0x800;
|
||||
PCGCCTL = 0;
|
||||
INTMSK |= INTMSK_USB_OTG;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) &= ~0x4;
|
||||
PWRCON(1) &= ~0x8;
|
||||
VIC0INTENABLE |= 1 << 19;
|
||||
#endif
|
||||
|
||||
usb_drv_exit();
|
||||
}
|
||||
|
|
@ -441,8 +457,13 @@ void usb_init_device(void)
|
|||
PCGCCTL = 1; /* Shut down PHY clock */
|
||||
OPHYPWR = 0xF; /* PHY: Power down */
|
||||
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON |= 0x4000;
|
||||
PWRCONEXT |= 0x800;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) |= 0x4;
|
||||
PWRCON(1) |= 0x8;
|
||||
#endif
|
||||
}
|
||||
|
||||
void usb_enable(bool on)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue