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usb-s3c6400x.[ch], button-clickwheel.c: Move s5l8701-specific parts to where they belong, prepare for s5l8702

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28800 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann 2010-12-12 00:52:02 +00:00
parent 8e1021bd4c
commit 70447b529c
4 changed files with 369 additions and 322 deletions
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20
firmware/export/s5l8700.h
View file

@ -571,6 +571,8 @@
#define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ #define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */
#define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ #define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */
#define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ #define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */
#define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */
#define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */
#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ #define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */
#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ #define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
@ -686,9 +688,9 @@
#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ #define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */
/* Hardware AES crypto unit - S5L8701 only */
#if CONFIG_CPU==S5L8701 #if CONFIG_CPU==S5L8701
/* Hardware AES crypto unit - S5L8701 only */
#define ICONSRCPND (*(REG32_PTR_T)(0x39C00000)) #define ICONSRCPND (*(REG32_PTR_T)(0x39C00000))
#define ICONINTPND (*(REG32_PTR_T)(0x39C00010)) #define ICONINTPND (*(REG32_PTR_T)(0x39C00010))
#define AESCONTROL (*(REG32_PTR_T)(0x39800000)) #define AESCONTROL (*(REG32_PTR_T)(0x39800000))
@ -709,4 +711,20 @@
#define HASHRESULT ((REG32_PTR_T)(0x3C600020)) #define HASHRESULT ((REG32_PTR_T)(0x3C600020))
#define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) #define HASHDATAIN ((REG32_PTR_T)(0x3C600040))
/* Clickwheel controller - S5L8701 only */
#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
/* Synopsys OTG - S5L8701 only */
#define OTGBASE 0x38800000
#define PHYBASE 0x3C400000
#define SYNOPSYSOTG_CLOCK 0
#define SYNOPSYSOTG_AHBCFG 0x27
#endif /* CONFIG_CPU==S5L8701 */ #endif /* CONFIG_CPU==S5L8701 */

586
firmware/export/usb-s3c6400x.h
View file

@ -22,320 +22,322 @@
#define USB_S3C6400X_H #define USB_S3C6400X_H
#define REG32_PTR_T volatile uint32_t *
/*** OTG PHY CONTROL REGISTERS ***/ /*** OTG PHY CONTROL REGISTERS ***/
#define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000) #define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
#define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004) #define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
#define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008) #define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
/*** OTG LINK CORE REGISTERS ***/ /*** OTG LINK CORE REGISTERS ***/
/* Core Global Registers */ /* Core Global Registers */
#define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000) #define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000)))
#define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004) #define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004)))
#define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008) #define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008)))
#define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C) #define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C)))
#define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010) #define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010)))
#define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014) #define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014)))
#define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018) #define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018)))
#define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C) #define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C)))
#define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020) #define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020)))
#define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024) #define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024)))
#define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028) #define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028)))
#define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C) #define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C)))
#define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100) #define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100)))
#define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x) #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
#define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104) #define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104)))
#define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108) #define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108)))
#define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C) #define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C)))
#define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110) #define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110)))
#define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114) #define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114)))
#define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118) #define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118)))
#define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C) #define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C)))
#define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120) #define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120)))
#define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124) #define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124)))
#define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128) #define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128)))
#define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C) #define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C)))
#define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130) #define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130)))
#define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134) #define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134)))
#define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138) #define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138)))
#define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C) #define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C)))
/*** HOST MODE REGISTERS ***/ /*** HOST MODE REGISTERS ***/
/* Host Global Registers */ /* Host Global Registers */
#define HCFG *(REG32_PTR_T)(OTGBASE + 0x400) #define HCFG (*((uint32_t volatile*)(OTGBASE + 0x400)))
#define HFIR *(REG32_PTR_T)(OTGBASE + 0x404) #define HFIR (*((uint32_t volatile*)(OTGBASE + 0x404)))
#define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408) #define HFNUM (*((uint32_t volatile*)(OTGBASE + 0x408)))
#define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410) #define HPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x410)))
#define HAINT *(REG32_PTR_T)(OTGBASE + 0x414) #define HAINT (*((uint32_t volatile*)(OTGBASE + 0x414)))
#define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418) #define HAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x418)))
/* Host Port Control and Status Registers */ /* Host Port Control and Status Registers */
#define HPRT *(REG32_PTR_T)(OTGBASE + 0x440) #define HPRT (*((uint32_t volatile*)(OTGBASE + 0x440)))
/* Host Channel-Specific Registers */ /* Host Channel-Specific Registers */
#define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x) #define HCCHAR(x) (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
#define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x) #define HCSPLT(x) (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
#define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x) #define HCINT(x) (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
#define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x) #define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
#define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x) #define HCTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
#define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x) #define HCDMA(x) (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
#define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500) #define HCCHAR0 (*((uint32_t volatile*)(OTGBASE + 0x500)))
#define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504) #define HCSPLT0 (*((uint32_t volatile*)(OTGBASE + 0x504)))
#define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508) #define HCINT0 (*((uint32_t volatile*)(OTGBASE + 0x508)))
#define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C) #define HCINTMSK0 (*((uint32_t volatile*)(OTGBASE + 0x50C)))
#define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510) #define HCTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x510)))
#define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514) #define HCDMA0 (*((uint32_t volatile*)(OTGBASE + 0x514)))
#define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520) #define HCCHAR1 (*((uint32_t volatile*)(OTGBASE + 0x520)))
#define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524) #define HCSPLT1 (*((uint32_t volatile*)(OTGBASE + 0x524)))
#define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528) #define HCINT1 (*((uint32_t volatile*)(OTGBASE + 0x528)))
#define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C) #define HCINTMSK1 (*((uint32_t volatile*)(OTGBASE + 0x52C)))
#define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530) #define HCTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x530)))
#define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534) #define HCDMA1 (*((uint32_t volatile*)(OTGBASE + 0x534)))
#define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540) #define HCCHAR2 (*((uint32_t volatile*)(OTGBASE + 0x540)))
#define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544) #define HCSPLT2 (*((uint32_t volatile*)(OTGBASE + 0x544)))
#define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548) #define HCINT2 (*((uint32_t volatile*)(OTGBASE + 0x548)))
#define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C) #define HCINTMSK2 (*((uint32_t volatile*)(OTGBASE + 0x54C)))
#define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550) #define HCTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x550)))
#define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554) #define HCDMA2 (*((uint32_t volatile*)(OTGBASE + 0x554)))
#define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560) #define HCCHAR3 (*((uint32_t volatile*)(OTGBASE + 0x560)))
#define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564) #define HCSPLT3 (*((uint32_t volatile*)(OTGBASE + 0x564)))
#define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568) #define HCINT3 (*((uint32_t volatile*)(OTGBASE + 0x568)))
#define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C) #define HCINTMSK3 (*((uint32_t volatile*)(OTGBASE + 0x56C)))
#define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570) #define HCTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x570)))
#define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574) #define HCDMA3 (*((uint32_t volatile*)(OTGBASE + 0x574)))
#define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580) #define HCCHAR4 (*((uint32_t volatile*)(OTGBASE + 0x580)))
#define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584) #define HCSPLT4 (*((uint32_t volatile*)(OTGBASE + 0x584)))
#define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588) #define HCINT4 (*((uint32_t volatile*)(OTGBASE + 0x588)))
#define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C) #define HCINTMSK4 (*((uint32_t volatile*)(OTGBASE + 0x58C)))
#define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590) #define HCTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x590)))
#define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594) #define HCDMA4 (*((uint32_t volatile*)(OTGBASE + 0x594)))
#define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0) #define HCCHAR5 (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
#define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4) #define HCSPLT5 (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
#define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8) #define HCINT5 (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
#define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC) #define HCINTMSK5 (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
#define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0) #define HCTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
#define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4) #define HCDMA5 (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
#define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0) #define HCCHAR6 (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
#define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4) #define HCSPLT6 (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
#define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8) #define HCINT6 (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
#define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC) #define HCINTMSK6 (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
#define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0) #define HCTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
#define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4) #define HCDMA6 (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
#define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0) #define HCCHAR7 (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
#define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4) #define HCSPLT7 (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
#define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8) #define HCINT7 (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
#define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC) #define HCINTMSK7 (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
#define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0) #define HCTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
#define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4) #define HCDMA7 (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
#define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600) #define HCCHAR8 (*((uint32_t volatile*)(OTGBASE + 0x600)))
#define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604) #define HCSPLT8 (*((uint32_t volatile*)(OTGBASE + 0x604)))
#define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608) #define HCINT8 (*((uint32_t volatile*)(OTGBASE + 0x608)))
#define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C) #define HCINTMSK8 (*((uint32_t volatile*)(OTGBASE + 0x60C)))
#define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610) #define HCTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x610)))
#define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614) #define HCDMA8 (*((uint32_t volatile*)(OTGBASE + 0x614)))
#define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620) #define HCCHAR9 (*((uint32_t volatile*)(OTGBASE + 0x620)))
#define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624) #define HCSPLT9 (*((uint32_t volatile*)(OTGBASE + 0x624)))
#define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628) #define HCINT9 (*((uint32_t volatile*)(OTGBASE + 0x628)))
#define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C) #define HCINTMSK9 (*((uint32_t volatile*)(OTGBASE + 0x62C)))
#define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630) #define HCTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x630)))
#define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634) #define HCDMA9 (*((uint32_t volatile*)(OTGBASE + 0x634)))
#define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640) #define HCCHAR10 (*((uint32_t volatile*)(OTGBASE + 0x640)))
#define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644) #define HCSPLT10 (*((uint32_t volatile*)(OTGBASE + 0x644)))
#define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648) #define HCINT10 (*((uint32_t volatile*)(OTGBASE + 0x648)))
#define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C) #define HCINTMSK10 (*((uint32_t volatile*)(OTGBASE + 0x64C)))
#define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650) #define HCTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x650)))
#define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654) #define HCDMA10 (*((uint32_t volatile*)(OTGBASE + 0x654)))
#define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660) #define HCCHAR11 (*((uint32_t volatile*)(OTGBASE + 0x660)))
#define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664) #define HCSPLT11 (*((uint32_t volatile*)(OTGBASE + 0x664)))
#define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668) #define HCINT11 (*((uint32_t volatile*)(OTGBASE + 0x668)))
#define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C) #define HCINTMSK11 (*((uint32_t volatile*)(OTGBASE + 0x66C)))
#define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670) #define HCTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x670)))
#define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674) #define HCDMA11 (*((uint32_t volatile*)(OTGBASE + 0x674)))
#define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680) #define HCCHAR12 (*((uint32_t volatile*)(OTGBASE + 0x680)))
#define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684) #define HCSPLT12 (*((uint32_t volatile*)(OTGBASE + 0x684)))
#define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688) #define HCINT12 (*((uint32_t volatile*)(OTGBASE + 0x688)))
#define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C) #define HCINTMSK12 (*((uint32_t volatile*)(OTGBASE + 0x68C)))
#define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690) #define HCTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x690)))
#define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694) #define HCDMA12 (*((uint32_t volatile*)(OTGBASE + 0x694)))
#define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0) #define HCCHAR13 (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
#define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4) #define HCSPLT13 (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
#define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8) #define HCINT13 (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
#define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC) #define HCINTMSK13 (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
#define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0) #define HCTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
#define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4) #define HCDMA13 (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
#define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0) #define HCCHAR14 (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
#define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4) #define HCSPLT14 (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
#define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8) #define HCINT14 (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
#define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC) #define HCINTMSK14 (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
#define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0) #define HCTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
#define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4) #define HCDMA14 (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
#define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0) #define HCCHAR15 (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
#define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4) #define HCSPLT15 (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
#define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8) #define HCINT15 (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
#define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC) #define HCINTMSK15 (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
#define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0) #define HCTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
#define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4) #define HCDMA15 (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
/*** DEVICE MODE REGISTERS ***/ /*** DEVICE MODE REGISTERS ***/
/* Device Global Registers */ /* Device Global Registers */
#define DCFG *(REG32_PTR_T)(OTGBASE + 0x800) #define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800)))
#define DCTL *(REG32_PTR_T)(OTGBASE + 0x804) #define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804)))
#define DSTS *(REG32_PTR_T)(OTGBASE + 0x808) #define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808)))
#define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810) #define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810)))
#define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814) #define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814)))
#define DAINT *(REG32_PTR_T)(OTGBASE + 0x818) #define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818)))
#define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C) #define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C)))
#define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820) #define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820)))
#define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824) #define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824)))
#define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828) #define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828)))
#define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C) #define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C)))
#define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830) #define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830)))
#define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834) #define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834)))
/* Device Logical IN Endpoint-Specific Registers */ /* Device Logical IN Endpoint-Specific Registers */
#define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x) #define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x))))
#define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x) #define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x))))
#define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x) #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x))))
#define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x) #define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x))))
#define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900) #define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900)))
#define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908) #define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908)))
#define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910) #define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910)))
#define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914) #define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914)))
#define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920) #define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920)))
#define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928) #define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928)))
#define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930) #define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930)))
#define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934) #define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934)))
#define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940) #define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940)))
#define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948) #define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948)))
#define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950) #define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950)))
#define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954) #define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954)))
#define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960) #define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960)))
#define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968) #define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968)))
#define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970) #define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970)))
#define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974) #define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974)))
#define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980) #define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980)))
#define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988) #define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988)))
#define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990) #define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990)))
#define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994) #define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994)))
#define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0) #define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0)))
#define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8) #define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8)))
#define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0) #define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0)))
#define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4) #define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4)))
#define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0) #define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0)))
#define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8) #define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8)))
#define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0) #define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0)))
#define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4) #define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4)))
#define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0) #define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0)))
#define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8) #define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8)))
#define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0) #define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0)))
#define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4) #define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4)))
#define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00) #define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00)))
#define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08) #define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08)))
#define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10) #define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10)))
#define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14) #define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14)))
#define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20) #define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20)))
#define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28) #define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28)))
#define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30) #define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30)))
#define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34) #define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34)))
#define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40) #define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40)))
#define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48) #define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48)))
#define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50) #define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50)))
#define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54) #define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54)))
#define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60) #define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60)))
#define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68) #define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68)))
#define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70) #define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70)))
#define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74) #define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74)))
#define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80) #define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80)))
#define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88) #define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88)))
#define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90) #define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90)))
#define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94) #define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94)))
#define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0) #define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0)))
#define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8) #define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8)))
#define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0) #define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0)))
#define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4) #define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4)))
#define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0) #define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0)))
#define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8) #define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8)))
#define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0) #define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0)))
#define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4) #define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4)))
#define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0) #define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0)))
#define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8) #define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8)))
#define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0) #define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0)))
#define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4) #define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4)))
/* Device Logical OUT Endpoint-Specific Registers */ /* Device Logical OUT Endpoint-Specific Registers */
#define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x) #define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x))))
#define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x) #define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x))))
#define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x) #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x))))
#define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x) #define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x))))
#define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00) #define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00)))
#define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08) #define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08)))
#define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10) #define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10)))
#define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14) #define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14)))
#define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20) #define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20)))
#define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28) #define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28)))
#define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30) #define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30)))
#define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34) #define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34)))
#define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40) #define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40)))
#define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48) #define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48)))
#define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50) #define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50)))
#define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54) #define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54)))
#define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60) #define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60)))
#define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68) #define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68)))
#define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70) #define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70)))
#define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74) #define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74)))
#define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80) #define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80)))
#define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88) #define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88)))
#define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90) #define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90)))
#define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94) #define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94)))
#define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0) #define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0)))
#define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8) #define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8)))
#define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0) #define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0)))
#define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4) #define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4)))
#define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0) #define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0)))
#define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8) #define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8)))
#define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0) #define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0)))
#define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4) #define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4)))
#define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0) #define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0)))
#define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8) #define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8)))
#define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0) #define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0)))
#define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4) #define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4)))
#define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00) #define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00)))
#define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08) #define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08)))
#define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10) #define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10)))
#define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14) #define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14)))
#define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20) #define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20)))
#define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28) #define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28)))
#define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30) #define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30)))
#define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34) #define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34)))
#define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40) #define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40)))
#define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48) #define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48)))
#define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50) #define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50)))
#define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54) #define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54)))
#define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60) #define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60)))
#define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68) #define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68)))
#define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70) #define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70)))
#define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74) #define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74)))
#define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80) #define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80)))
#define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88) #define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88)))
#define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90) #define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90)))
#define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94) #define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94)))
#define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0) #define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0)))
#define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8) #define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8)))
#define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0) #define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0)))
#define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4) #define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4)))
#define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0) #define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0)))
#define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8) #define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8)))
#define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0) #define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0)))
#define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4) #define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4)))
#define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0) #define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0)))
#define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8) #define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8)))
#define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0) #define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0)))
#define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4) #define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4)))
/* Power and Clock Gating Register */ /* Power and Clock Gating Register */
#define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00) #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00)))
#endif /* USB_S3C6400X_H */ #endif /* USB_S3C6400X_H */

42
firmware/target/arm/ipod/button-clickwheel.c
View file

@ -39,7 +39,7 @@
#include "serial.h" #include "serial.h"
#include "power.h" #include "power.h"
#include "powermgmt.h" #include "powermgmt.h"
#if defined(IPOD_NANO2G) #if defined(IPOD_NANO2G) || defined(IPOD_6G)
#include "pmu-target.h" #include "pmu-target.h"
#endif #endif
@ -49,18 +49,8 @@
#ifdef CPU_PP #ifdef CPU_PP
#define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x7000c140)) #define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x7000c140))
#elif CONFIG_CPU==S5L8701 #elif CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
#define PCON15 (*((volatile uint32_t*)(0x3CF000F0))) #define CLICKWHEEL_DATA WHEELRX
#define PUNK15 (*((volatile uint32_t*)(0x3CF000FC)))
#define WHEEL00 (*((volatile uint32_t*)(0x3C200000)))
#define WHEEL04 (*((volatile uint32_t*)(0x3C200004)))
#define WHEEL08 (*((volatile uint32_t*)(0x3C200008)))
#define WHEEL0C (*((volatile uint32_t*)(0x3C20000C)))
#define WHEEL10 (*((volatile uint32_t*)(0x3C200010)))
#define WHEELINT (*((volatile uint32_t*)(0x3C200014)))
#define WHEELRX (*((volatile uint32_t*)(0x3C200018)))
#define WHEELTX (*((volatile uint32_t*)(0x3C20001C)))
#define CLICKWHEEL_DATA (*(volatile unsigned long*)(0x3c200018))
#else #else
#error CPU architecture not supported! #error CPU architecture not supported!
#endif #endif
@ -93,7 +83,7 @@ int int_btn = BUTTON_NONE;
static bool send_events = true; static bool send_events = true;
#endif #endif
#if CONFIG_CPU==S5L8701 #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
static struct wakeup button_init_wakeup; static struct wakeup button_init_wakeup;
#endif #endif
@ -265,7 +255,7 @@ static inline int ipod_4g_button_read(void)
} }
} }
#if CONFIG_CPU==S5L8701 #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702
else if ((status & 0x8000FFFF) == 0x8000023A) else if ((status & 0x8000FFFF) == 0x8000023A)
{ {
if (status & 0x00010000) if (status & 0x00010000)
@ -345,7 +335,7 @@ bool headphones_inserted(void)
return (GPIOA_INPUT_VAL & 0x80)?true:false; return (GPIOA_INPUT_VAL & 0x80)?true:false;
} }
#else #else
void INT_SPI(void) void INT_WHEEL(void)
{ {
int clickwheel_events = WHEELINT; int clickwheel_events = WHEELINT;
@ -359,6 +349,7 @@ void INT_SPI(void)
void s5l_clickwheel_init(void) void s5l_clickwheel_init(void)
{ {
#if CONFIG_CPU==S5L8701
PWRCONEXT &= ~1; PWRCONEXT &= ~1;
PCON15 = (PCON15 & ~0xFFFF0000) | 0x22220000; PCON15 = (PCON15 & ~0xFFFF0000) | 0x22220000;
PUNK15 = 0xF0; PUNK15 = 0xF0;
@ -370,24 +361,35 @@ void s5l_clickwheel_init(void)
WHEELTX = 0x8000023A; WHEELTX = 0x8000023A;
WHEEL04 |= 1; WHEEL04 |= 1;
PDAT10 &= ~2; PDAT10 &= ~2;
#elif CONFIG_CPU==S5L8702
//TODO: Implement
#endif
} }
void button_init_device(void) void button_init_device(void)
{ {
wakeup_init(&button_init_wakeup); wakeup_init(&button_init_wakeup);
#if CONFIG_CPU==S5L8701
INTMSK |= (1<<26); INTMSK |= (1<<26);
#elif CONFIG_CPU==S5L8702
//TODO: Implement
#endif
s5l_clickwheel_init(); s5l_clickwheel_init();
wakeup_wait(&button_init_wakeup, HZ / 10); wakeup_wait(&button_init_wakeup, HZ / 10);
} }
bool button_hold(void) bool button_hold(void)
{ {
return ((PDAT14 & (1 << 6)) == 0); //TODO: Implement
//return ((PDAT14 & (1 << 6)) == 0);
return false;
} }
bool headphones_inserted(void) bool headphones_inserted(void)
{ {
return ((PDAT14 & (1 << 5)) != 0); //TODO: Implement
//return ((PDAT14 & (1 << 5)) == 0);
return false;
} }
#endif #endif
@ -419,6 +421,8 @@ int button_read_device(void)
WHEEL00 = 0; WHEEL00 = 0;
WHEEL10 = 0; WHEEL10 = 0;
PWRCONEXT |= 1; PWRCONEXT |= 1;
#elif CONFIG_CPU==S5L8702
//TODO: Implement
#endif #endif
} }
else else
@ -430,6 +434,8 @@ int button_read_device(void)
#elif CONFIG_CPU==S5L8701 #elif CONFIG_CPU==S5L8701
pmu_ldo_power_on(1); /* enable clickwheel power supply */ pmu_ldo_power_on(1); /* enable clickwheel power supply */
s5l_clickwheel_init(); s5l_clickwheel_init();
#elif CONFIG_CPU==S5L8702
//TODO: Implement
#endif #endif
} }
} }

43
firmware/target/arm/usb-s3c6400x.c
View file

@ -24,15 +24,13 @@
#include "usb-target.h" #include "usb-target.h"
#include "usb_drv.h" #include "usb_drv.h"
#define OTGBASE 0x38800000
#define PHYBASE 0x3C400000
#include "usb-s3c6400x.h"
#include "cpu.h" #include "cpu.h"
#include "system.h" #include "system.h"
#include "kernel.h" #include "kernel.h"
#include "panic.h" #include "panic.h"
#include "usb-s3c6400x.h"
#ifdef HAVE_USBSTACK #ifdef HAVE_USBSTACK
#include "usb_ch9.h" #include "usb_ch9.h"
#include "usb_core.h" #include "usb_core.h"
@ -72,7 +70,7 @@ static void reset_endpoints(int reinit)
DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */ DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */
DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size: DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size:
64 Bytes, 1 Packet, 1 Setup Packet */ 64 Bytes, 1 Packet, 1 Setup Packet */
DOEPDMA0 = (uint32_t)&ctrlreq; DOEPDMA0 = &ctrlreq;
DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */
if (reinit) if (reinit)
{ {
@ -139,10 +137,13 @@ static void usb_reset(void)
DCTL = 0x802; /* Soft Disconnect */ DCTL = 0x802; /* Soft Disconnect */
OPHYPWR = 0; /* PHY: Power up */ OPHYPWR = 0; /* PHY: Power up */
OPHYUNK1 = 1;
OPHYUNK2 = 0xE3F;
OPHYCLK = SYNOPSYSOTG_CLOCK;
ORSTCON = 1; /* PHY: Assert Software Reset */ ORSTCON = 1; /* PHY: Assert Software Reset */
for (i = 0; i < 50; i++); for (i = 0; i < 50; i++);
ORSTCON = 0; /* PHY: Deassert Software Reset */ ORSTCON = 0; /* PHY: Deassert Software Reset */
OPHYCLK = 0; /* PHY: 48MHz clock */ OPHYUNK3 = 0x600;
GRSTCTL = 1; /* OTG: Assert Software Reset */ GRSTCTL = 1; /* OTG: Assert Software Reset */
while (GRSTCTL & 1); /* Wait for OTG to ack reset */ while (GRSTCTL & 1); /* Wait for OTG to ack reset */
@ -150,7 +151,7 @@ static void usb_reset(void)
GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */ GRXFSIZ = 0x00000200; /* RX FIFO: 512 bytes */
GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */ GNPTXFSIZ = 0x02000200; /* Non-periodic TX FIFO: 512 bytes */
GAHBCFG = 0x27; /* OTG AHB config: Unmask ints, burst length 4, DMA on */ GAHBCFG = SYNOPSYSOTG_AHBCFG;
GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */
DCFG = 4; /* Address 0 */ DCFG = 4; /* Address 0 */
@ -375,12 +376,16 @@ void usb_drv_stall(int endpoint, bool stall, bool in)
void usb_drv_init(void) void usb_drv_init(void)
{ {
/* Enable USB clock */ /* Enable USB clock */
#if CONFIG_CPU==S5L8701
PWRCON &= ~0x4000; PWRCON &= ~0x4000;
PWRCONEXT &= ~0x800; PWRCONEXT &= ~0x800;
PCGCCTL = 0;
/* unmask irq */
INTMSK |= INTMSK_USB_OTG; INTMSK |= INTMSK_USB_OTG;
#elif CONFIG_CPU==S5L8702
PWRCON(0) &= ~0x4;
PWRCON(1) &= ~0x8;
VIC0INTENABLE |= 1 << 19;
#endif
PCGCCTL = 0;
/* reset the beast */ /* reset the beast */
usb_reset(); usb_reset();
@ -394,8 +399,13 @@ void usb_drv_exit(void)
PCGCCTL = 1; /* Shut down PHY clock */ PCGCCTL = 1; /* Shut down PHY clock */
OPHYPWR = 0xF; /* PHY: Power down */ OPHYPWR = 0xF; /* PHY: Power down */
#if CONFIG_CPU==S5L8701
PWRCON |= 0x4000; PWRCON |= 0x4000;
PWRCONEXT |= 0x800; PWRCONEXT |= 0x800;
#elif CONFIG_CPU==S5L8702
PWRCON(0) |= 0x4;
PWRCON(1) |= 0x8;
#endif
} }
void usb_init_device(void) void usb_init_device(void)
@ -406,10 +416,16 @@ void usb_init_device(void)
/* Power up the core clocks to allow writing /* Power up the core clocks to allow writing
to some registers needed to power it down */ to some registers needed to power it down */
PCGCCTL = 0;
#if CONFIG_CPU==S5L8701
PWRCON &= ~0x4000; PWRCON &= ~0x4000;
PWRCONEXT &= ~0x800; PWRCONEXT &= ~0x800;
PCGCCTL = 0;
INTMSK |= INTMSK_USB_OTG; INTMSK |= INTMSK_USB_OTG;
#elif CONFIG_CPU==S5L8702
PWRCON(0) &= ~0x4;
PWRCON(1) &= ~0x8;
VIC0INTENABLE |= 1 << 19;
#endif
usb_drv_exit(); usb_drv_exit();
} }
@ -441,8 +457,13 @@ void usb_init_device(void)
PCGCCTL = 1; /* Shut down PHY clock */ PCGCCTL = 1; /* Shut down PHY clock */
OPHYPWR = 0xF; /* PHY: Power down */ OPHYPWR = 0xF; /* PHY: Power down */
#if CONFIG_CPU==S5L8701
PWRCON |= 0x4000; PWRCON |= 0x4000;
PWRCONEXT |= 0x800; PWRCONEXT |= 0x800;
#elif CONFIG_CPU==S5L8702
PWRCON(0) |= 0x4;
PWRCON(1) |= 0x8;
#endif
} }
void usb_enable(bool on) void usb_enable(bool on)