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https://github.com/Rockbox/rockbox.git
synced 2026-07-10 13:29:52 -04:00
target: arm: s5l8700: fix mcr/mrc usage in crt0.S for lld
Change-Id: I6d25e4759e1d86f8de3047d10f5fcac8030afc6e
This commit is contained in:
mojyack
parent
21fe45caad
commit
6fc41c7cdf
1 changed files with 64 additions and 64 deletions
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@ -49,9 +49,9 @@ newstart2:
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#ifdef ROCKBOX_BIG_ENDIAN
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mov r1, #0x80
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // set bigendian
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mcr p15, 0, r0, c1, c0, 0 // set bigendian
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#endif
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ldr r1, =0x3c800000 // disable watchdog
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@ -144,11 +144,11 @@ start_loc:
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str r0, [r1,#0x10] // CLKCON3
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ldr r2, =0xc0000078
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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mvn r1, #0xc0000000
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and r0, r0, r1
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orr r0, r0, r2
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mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
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mcr p15, 0, r0, c1, c0, 0 // asynchronous clocking mode
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nop
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nop
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nop
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@ -179,17 +179,17 @@ start_loc:
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ldr r0, =0xffffef7e
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str r0, [r1,#0x40] // PWRCONEXT
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000
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bic r0, r0, #0x5
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mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit
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mcr p15, 0, r0, c1, c0, 0 // disable caches and protection unit
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mov r1, #0
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1:
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mov r0, #0
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2:
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orr r2, r1, r0
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mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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mcr p15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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add r0, r0, #0x10
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cmp r0, #0x40
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bne 2b
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@ -199,48 +199,48 @@ start_loc:
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nop
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nop
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mov r0, #0
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mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mcr 15, 0, r0, c7, c5, 0 // flush icache
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mcr 15, 0, r0, c7, c6, 0 // flush dcache
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mcr p15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mcr p15, 0, r0, c7, c5, 0 // flush icache
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mcr p15, 0, r0, c7, c6, 0 // flush dcache
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 1 // CS0: 4GB at offset 0 - everything
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mcr 15, 0, r0, c6, c0, 0 // DS0: 4GB at offset 0 - everything
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mcr p15, 0, r0, c6, c0, 1 // CS0: 4GB at offset 0 - everything
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mcr p15, 0, r0, c6, c0, 0 // DS0: 4GB at offset 0 - everything
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#ifdef IPOD_NANO2G
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mov r0, #0x31 // FIXME: calculate that from MEMORYSIZE
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#else
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mov r0, #0x2f // FIXME: calculate that from MEMORYSIZE
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#endif
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mcr 15, 0, r0, c6, c1, 1 // CS1: SRAM/SDRAM mirror
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mcr 15, 0, r0, c6, c1, 0 // DS1: SRAM/SDRAM mirror
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mcr p15, 0, r0, c6, c1, 1 // CS1: SRAM/SDRAM mirror
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mcr p15, 0, r0, c6, c1, 0 // DS1: SRAM/SDRAM mirror
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add r0, r0, #0x08000000
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mcr 15, 0, r0, c6, c2, 1 // CS2: SDRAM
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mcr 15, 0, r0, c6, c2, 0 // DS2: SDRAM
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mcr p15, 0, r0, c6, c2, 1 // CS2: SDRAM
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mcr p15, 0, r0, c6, c2, 0 // DS2: SDRAM
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 1 // CS3: SRAM
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mcr 15, 0, r0, c6, c3, 0 // DS3: SRAM
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mcr p15, 0, r0, c6, c3, 1 // CS3: SRAM
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mcr p15, 0, r0, c6, c3, 0 // DS3: SRAM
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ldr r0, =0x24000027
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mcr 15, 0, r0, c6, c4, 1 // CS4: NOR flash
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mcr 15, 0, r0, c6, c4, 0 // DS4: NOR flash
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mcr p15, 0, r0, c6, c4, 1 // CS4: NOR flash
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mcr p15, 0, r0, c6, c4, 0 // DS4: NOR flash
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mov r0, #0
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mcr 15, 0, r0, c6, c5, 1 // CS5: unused
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mcr 15, 0, r0, c6, c5, 0 // DS5: unused
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mcr 15, 0, r0, c6, c6, 1 // CS6: unused
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mcr 15, 0, r0, c6, c6, 0 // DS6: unused
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mcr 15, 0, r0, c6, c7, 1 // CS7: unused
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mcr 15, 0, r0, c6, c7, 0 // DS7: unused
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mcr p15, 0, r0, c6, c5, 1 // CS5: unused
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mcr p15, 0, r0, c6, c5, 0 // DS5: unused
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mcr p15, 0, r0, c6, c6, 1 // CS6: unused
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mcr p15, 0, r0, c6, c6, 0 // DS6: unused
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mcr p15, 0, r0, c6, c7, 1 // CS7: unused
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mcr p15, 0, r0, c6, c7, 0 // DS7: unused
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 1 // CS1-4: cacheable
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mcr 15, 0, r0, c2, c0, 0 // DS1-4: cacheable
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mcr 15, 0, r0, c3, c0, 0 // DS1-4: write cacheable
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mcr p15, 0, r0, c2, c0, 1 // CS1-4: cacheable
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mcr p15, 0, r0, c2, c0, 0 // DS1-4: cacheable
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mcr p15, 0, r0, c3, c0, 0 // DS1-4: write cacheable
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ldr r0, =0x000003ff
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mcr 15, 0, r0, c5, c0, 1 // CS0-4: full access
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mcr 15, 0, r0, c5, c0, 0 // DS0-4: full access
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mcr p15, 0, r0, c5, c0, 1 // CS0-4: full access
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mcr p15, 0, r0, c5, c0, 0 // DS0-4: full access
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x5
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orr r0, r0, #0x1000
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mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
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mcr p15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
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ldr r1, =0x38200000
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ldr r0, =0x006A49A5 // default: settings from Apple FW (96 MHz HCLK)
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@ -255,26 +255,26 @@ start_loc:
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str r0, [r1, #44] // do not enter any power saving mode
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mov r1, #0x1
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // disable protection unit
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mcr p15, 0, r0, c1, c0, 0 // disable protection unit
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mov r1, #0x4
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // dcache disable
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mcr p15, 0, r0, c1, c0, 0 // dcache disable
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mov r1, #0x1000
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // icache disable
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mcr p15, 0, r0, c1, c0, 0 // icache disable
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mov r1, #0
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1:
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mov r0, #0
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2:
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orr r2, r1, r0
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mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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mcr p15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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add r0, r0, #0x10
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cmp r0, #0x40
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bne 2b
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@ -284,59 +284,59 @@ start_loc:
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nop
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nop
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mov r0, #0
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mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mcr p15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mov r0, #0
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mcr 15, 0, r0, c7, c5, 0 // flush icache
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mcr p15, 0, r0, c7, c5, 0 // flush icache
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mov r0, #0
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mcr 15, 0, r0, c7, c6, 0 // flush dcache
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mcr p15, 0, r0, c7, c6, 0 // flush dcache
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 1
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mcr p15, 0, r0, c6, c0, 1
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mov r0, #0x2f
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mcr 15, 0, r0, c6, c1, 1
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mcr p15, 0, r0, c6, c1, 1
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ldr r0, =0x08000031
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mcr 15, 0, r0, c6, c2, 1
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mcr p15, 0, r0, c6, c2, 1
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 1
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mcr p15, 0, r0, c6, c3, 1
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ldr r0, =0x24000027
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mcr 15, 0, r0, c6, c4, 1
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mcr p15, 0, r0, c6, c4, 1
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 0
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mcr p15, 0, r0, c6, c0, 0
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mov r0, #0x2f
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mcr 15, 0, r0, c6, c1, 0
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mcr p15, 0, r0, c6, c1, 0
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ldr r0, =0x08000031
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mcr 15, 0, r0, c6, c2, 0
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mcr p15, 0, r0, c6, c2, 0
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 0
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mcr p15, 0, r0, c6, c3, 0
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ldr r0, =0x24000029
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mcr 15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c4, 0
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 1
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mcr p15, 0, r0, c2, c0, 1
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 0
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mcr p15, 0, r0, c2, c0, 0
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mov r0, #0x1e
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mcr 15, 0, r0, c3, c0, 0
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mcr p15, 0, r0, c3, c0, 0
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ldr r0, =0x0000ffff
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mcr 15, 0, r0, c5, c0, 1
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mcr p15, 0, r0, c5, c0, 1
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ldr r0, =0x0000ffff
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mcr 15, 0, r0, c5, c0, 0 // set up protection and caching
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mcr p15, 0, r0, c5, c0, 0 // set up protection and caching
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mov r1, #0x4
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // dcache enable
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mcr p15, 0, r0, c1, c0, 0 // dcache enable
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mov r1, #0x1000
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // icache enable
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mcr p15, 0, r0, c1, c0, 0 // icache enable
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mov r1, #0x1
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mrc 15, 0, r0, c1, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // enable protection unit
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mcr p15, 0, r0, c1, c0, 0 // enable protection unit
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#endif
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#if CONFIG_CPU==S5L8700 || !defined(BOOTLOADER)
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