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Patch by Rafaël Carré - Sansa AMS: Fix a few mistakes in DMA code

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DMAC_INT_TC_CLEAR is a write-only reg
HIGH bits of DMAC_SYNC mean synchronisation logic disabled.
Also, according to the OF and to tests, all the peripherals we use run at the same frequency (PCLK?).



git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20643 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Bertrik Sikken 2009-04-07 17:08:26 +00:00
parent e15cf78987
commit 6b63f23648
1 changed files with 2 additions and 5 deletions
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7
firmware/target/arm/as3525/dma-pl081.c
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@ -48,7 +48,7 @@ void dma_release(void)
void dma_init(void)
{
DMAC_SYNC = 0;
DMAC_SYNC = 0xffff; /* disable synchronisation logic */
VIC_INT_ENABLE |= INTERRUPT_DMAC;
}
@ -88,9 +88,6 @@ void dma_enable_channel(int channel, void *src, void *dst, int peri,
DMAC_CH_CONTROL(channel) = control;
/* only needed if DMAC and Peripheral do not run at the same clock speed */
DMAC_SYNC |= (1<<peri);
/* we set the same peripheral as source and destination because we always
* use memory-to-peripheral or peripheral-to-memory transfers */
DMAC_CH_CONFIGURATION(channel) =
@ -116,7 +113,7 @@ void INT_DMAC(void)
panicf("DMA error, channel %d", channel);
/* clear terminal count interrupt */
DMAC_INT_TC_CLEAR |= (1<<channel);
DMAC_INT_TC_CLEAR = (1<<channel);
if(dma_callback[channel])
dma_callback[channel]();