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echoplayer: enable SD card using sdmmc_host
Enable pullups on SDMMC CMD/DATx lines and set output speed to medium. Using HIGH and VERYHIGH speeds seems to cause data corruption, with frequent CRC failures. Change-Id: I732d19e03a2a857453755b68b6749497eafaef70
This commit is contained in:
Aidan MacDonald
Solomon Peachy
parent
141b4a223f
commit
6a8989f347
5 changed files with 138 additions and 3 deletions
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@ -2038,6 +2038,7 @@ target/arm/stm32/echoplayer/button-echoplayer.c
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target/arm/stm32/echoplayer/clock-echoplayer.c
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target/arm/stm32/echoplayer/lcd-echoplayer.c
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target/arm/stm32/echoplayer/power-echoplayer.c
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target/arm/stm32/echoplayer/sdmmc-echoplayer.c
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target/arm/stm32/echoplayer/system-echoplayer.c
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#endif
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@ -67,6 +67,9 @@
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#define STORAGE_WANTS_ALIGN
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#define STORAGE_NEEDS_BOUNCE_BUFFER
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/* One SD card slot */
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#define SDMMC_HOST_NUM_SD_CONTROLLERS 1
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/* RTC settings */
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#define CONFIG_RTC RTC_STM32H743
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#define HAVE_RTC_ALARM
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@ -27,6 +27,8 @@
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/syscfg.h"
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#define PLL1Q_FREQ 48000000
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
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@ -44,6 +46,8 @@ static void init_pll(void)
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"HSE frequency not correct");
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_Static_assert(LCD_DOTCLOCK_FREQ == 6199200,
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"PLL3 parameters not correct for dot clock");
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_Static_assert(PLL1Q_FREQ == 48000000,
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"PLL1Q parameters not correct");
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/*
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* Use HSE/4 input for PLL1
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@ -76,7 +80,7 @@ static void init_pll(void)
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reg_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
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DIVP(1 - 1), /* 480 / 1 = 480 MHz */
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DIVQ(8 - 1), /* 480 / 8 = 60 MHz */
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DIVQ(10 - 1), /* 480 / 10 = 48 MHz */
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DIVR(1 - 1));
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reg_writef(RCC_PLL3FRACR, FRACN(1468));
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@ -159,6 +163,7 @@ static void init_lse(void)
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static void init_periph_clock(void)
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{
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reg_writef(RCC_D1CCIPR, SDMMCSEL_V(PLL1Q));
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reg_writef(RCC_D2CCIP1R, SPI45SEL_V(HSE));
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/* Enable AXI SRAM in sleep mode to allow DMA'ing out of it */
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@ -189,6 +194,11 @@ void stm_target_clock_enable(enum stm_clock clock, bool enable)
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reg_writef(RCC_APB3LPENR, LTDCEN(enable));
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break;
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case STM_CLOCK_SDMMC1_KER:
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reg_writef(RCC_AHB3ENR, SDMMC1EN(enable));
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reg_writef(RCC_AHB3LPENR, SDMMC1EN(enable));
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break;
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default:
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panicf("%s: unsupported clock %d", __func__, (int)clock);
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break;
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@ -202,6 +212,9 @@ size_t stm_target_clock_get_frequency(enum stm_clock clock)
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case STM_CLOCK_SPI5_KER:
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return STM32_HSE_FREQ;
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case STM_CLOCK_SDMMC1_KER:
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return PLL1Q_FREQ;
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default:
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panicf("%s: unsupported clock %d", __func__, (int)clock);
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return 0;
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116
firmware/target/arm/stm32/echoplayer/sdmmc-echoplayer.c
Normal file
116
firmware/target/arm/stm32/echoplayer/sdmmc-echoplayer.c
Normal file
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@ -0,0 +1,116 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 by Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "sdmmc_host.h"
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#include "sdmmc-stm32h7.h"
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#include "gpio-stm32h7.h"
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#include "nvic-arm.h"
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#include "regs/stm32h743/sdmmc.h"
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/* 300ms poll interval */
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#define SDCARD_POLL_TICKS (300 * HZ / 1000)
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static struct sdmmc_host sdmmc1;
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static struct stm32h7_sdmmc_controller sdmmc1_ctl;
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static const struct sdmmc_controller_ops sdmmc_ops = {
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.set_power_enabled = stm32h7_sdmmc_set_power_enabled,
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.set_bus_width = stm32h7_sdmmc_set_bus_width,
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.set_bus_clock = stm32h7_sdmmc_set_bus_clock,
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.submit_command = stm32h7_sdmmc_submit_command,
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.abort_command = stm32h7_sdmmc_abort_command,
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};
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static const struct sdmmc_host_config sdmmc_config INITDATA_ATTR = {
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.type = STORAGE_SD,
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.bus_voltages = SDMMC_BUS_VOLTAGE_3V2_3V3 |
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SDMMC_BUS_VOLTAGE_3V3_3V4,
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.bus_widths = SDMMC_BUS_WIDTH_1BIT |
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SDMMC_BUS_WIDTH_4BIT,
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.bus_clocks = SDMMC_BUS_CLOCK_400KHZ |
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SDMMC_BUS_CLOCK_25MHZ |
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SDMMC_BUS_CLOCK_50MHZ,
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.is_removable = true,
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};
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/*
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* simple SD insertion poller
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*/
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struct sdmmc_poll
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{
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struct sdmmc_host *host;
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bool is_inserted;
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bool last_state;
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bool curr_state;
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};
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static bool is_sdcard_inserted(void)
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{
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return gpio_get_level(GPIO_SDMMC_DETECT) == 0;
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}
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static int poll_sdcard_inserted(struct timeout *tmo)
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{
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struct sdmmc_poll *poll = (void *)tmo->data;
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poll->last_state = poll->curr_state;
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poll->curr_state = is_sdcard_inserted();
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if (!poll->curr_state && poll->is_inserted)
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{
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poll->is_inserted = false;
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sdmmc_host_set_medium_present(poll->host, false);
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}
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else if (poll->curr_state && !poll->is_inserted &&
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poll->curr_state == poll->last_state)
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{
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poll->is_inserted = true;
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sdmmc_host_set_medium_present(poll->host, true);
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}
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return SDCARD_POLL_TICKS;
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}
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static struct timeout sdcard_poll_timeout;
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static struct sdmmc_poll sdcard_poll;
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void sdmmc_host_target_init(void)
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{
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/* Initialize controller */
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stm32h7_sdmmc_init(&sdmmc1_ctl, ITA_SDMMC1, STM_CLOCK_SDMMC1_KER,
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stm32h7_reset_sdmmc1, NULL);
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nvic_enable_irq(NVIC_IRQN_SDMMC1);
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/* Initialize card detect polling */
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sdcard_poll.host = &sdmmc1;
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sdcard_poll.is_inserted = is_sdcard_inserted();
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timeout_register(&sdcard_poll_timeout, poll_sdcard_inserted,
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SDCARD_POLL_TICKS, (intptr_t)&sdcard_poll);
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/* Initialize SD/MMC host driver */
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sdmmc_host_init(&sdmmc1, &sdmmc_config, &sdmmc_ops, &sdmmc1_ctl);
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sdmmc_host_init_medium_present(&sdmmc1, sdcard_poll.is_inserted);
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}
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void sdmmc1_irq_handler(void)
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{
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stm32h7_sdmmc_irq_handler(&sdmmc1_ctl);
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}
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@ -32,7 +32,8 @@
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#define F_ULPI GPIOF_FUNCTION(10, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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#define F_MCO1 GPIOF_FUNCTION(0, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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#define F_I2C1 GPIOF_FUNCTION(4, GPIO_TYPE_OPEN_DRAIN, GPIO_SPEED_LOW, GPIO_PULL_DISABLED)
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#define F_SDMMC1 GPIOF_FUNCTION(12, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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#define F_SDMMC1 GPIOF_FUNCTION(12, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP)
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#define F_SDMMC1CK GPIOF_FUNCTION(12, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_DISABLED)
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#define F_SAI1 GPIOF_FUNCTION(6, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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#define F_SPI5 GPIOF_FUNCTION(5, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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#define F_LCD_AF14 GPIOF_FUNCTION(14, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_VERYHIGH, GPIO_PULL_DISABLED)
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@ -93,7 +94,8 @@ static const struct pingroup_setting pingroups[] = {
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/* I2C1 */
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STM_DEFPINS(GPIO_B, 0x00c0, F_I2C1),
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/* SDMMC1 */
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STM_DEFPINS(GPIO_C, 0x1f00, F_SDMMC1),
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STM_DEFPINS(GPIO_C, 0x1000, F_SDMMC1CK),
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STM_DEFPINS(GPIO_C, 0x0f00, F_SDMMC1),
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STM_DEFPINS(GPIO_D, 0x0004, F_SDMMC1),
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/* SAI1 */
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STM_DEFPINS(GPIO_E, 0x007c, F_SAI1),
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