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iPod Classic: use new PL080 DMA driver
This patch uses the new pl080 DMA driver for I2S playback and LCD update. I have tried to be as fiel as possible to the current behaviour, algorithms and configurations are the same, but using the new driver. Other modifications: Playback: - CHUNK_SIZE is decreased from 42988 to 8188 bytes, it does not affect normal playback (block size 1024), was tested using metronome (block size 46080). This change is needed because the new code commits d-cache range instead of commiting the whole d-cache, maximum time spent commiting the range should be limited, CHUNK_SIZE can be decreased even more if necessary. - pcm_play_dma_start() calls pcm_play_dma_stop() to stop the channel when it is running (metronome replays the tick sound without stopping the channel). - pcm_play_dma_get_peak_buffer(): same as actual SVN function but returns samples count instead of bytes count. TODO: AFAIK, actually this function is not used in RB. Not tested, but probably this function will fail because it returns pointers to the internal double buffer. LCD update: - suppresses lcd_wakeup semaphore and uses yield() Change-Id: I79b8aa47a941e0dd91847150618f3f7f676c26ef
This commit is contained in:
Cástor Muñoz
parent
d6ee2c9eaf
commit
67b4e7f958
9 changed files with 336 additions and 343 deletions
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@ -44,7 +44,7 @@ bool dbg_hw_info(void)
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int line;
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int i;
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unsigned int state = 0;
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const unsigned int max_states=3;
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const unsigned int max_states=2;
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lcd_clear_display();
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lcd_setfont(FONT_SYSFIXED);
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@ -95,16 +95,6 @@ bool dbg_hw_info(void)
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_DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
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_DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
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}
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else if(state==2)
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{
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_DEBUG_PRINTF("Audio DMA:");
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_DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
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DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
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for(i = 0; i < PCM_LLICOUNT; i++)
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_DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
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pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
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_DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
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}
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else
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{
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state=0;
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68
firmware/target/arm/s5l8702/dma-s5l8702.c
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68
firmware/target/arm/s5l8702/dma-s5l8702.c
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@ -0,0 +1,68 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <config.h>
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#include "s5l8702.h"
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#include "pl080.h"
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#include "dma-s5l8702.h"
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/* s5l8702 PL080 controllers configuration */
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struct dmac s5l8702_dmac0 = {
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.baddr = S5L8702_DMAC0_BASE,
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.m1 = DMACCONFIG_M_LITTLE_ENDIAN,
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.m2 = DMACCONFIG_M_LITTLE_ENDIAN,
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};
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struct dmac s5l8702_dmac1 = {
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.baddr = S5L8702_DMAC1_BASE,
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.m1 = DMACCONFIG_M_LITTLE_ENDIAN,
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.m2 = DMACCONFIG_M_LITTLE_ENDIAN,
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};
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void ICODE_ATTR INT_DMAC0(void)
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{
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dmac_callback(&s5l8702_dmac0);
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}
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void ICODE_ATTR INT_DMAC1(void)
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{
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dmac_callback(&s5l8702_dmac1);
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}
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void dma_init_ctrl(struct dmac* dmac, int irq, int clockgate, int onoff)
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{
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/* init DMAC */
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VIC0INTENCLEAR = (1 << irq); /* disable interrupts */
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PWRCON(0) &= ~(1 << clockgate); /* unmask clock gate */
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dmac_open(dmac); /* init/reset controller */
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if (onoff)
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VIC0INTENABLE = (1 << irq); /* enable interrupts */
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else
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PWRCON(0) |= (1 << clockgate); /* mask clockgate */
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}
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void dma_init(void)
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{
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dma_init_ctrl(&s5l8702_dmac0, IRQ_DMAC0, CLOCKGATE_DMAC0, 1);
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dma_init_ctrl(&s5l8702_dmac1, IRQ_DMAC1, CLOCKGATE_DMAC1, 0);
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}
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107
firmware/target/arm/s5l8702/dma-s5l8702.h
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107
firmware/target/arm/s5l8702/dma-s5l8702.h
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@ -0,0 +1,107 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _DMA_S5l8702_H
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#define _DMA_S5l8702_H
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#include "pl080.h"
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/*
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* s5l8702 PL080 controllers configuration
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*/
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extern struct dmac s5l8702_dmac0;
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extern struct dmac s5l8702_dmac1;
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#define S5L8702_DMAC_COUNT 2 /* N PL080 controllers */
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#define S5L8702_DMAC0_BASE 0x38200000
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#define S5L8702_DMAC1_BASE 0x39900000
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/* S5L7802 DMAC0 peripherals */
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#define S5L8702_DMAC0_PERI_IIS2_TX 0x0
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#define S5L8702_DMAC0_PERI_IIS2_RX 0x1
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#define S5L8702_DMAC0_PERI_UNKNOWN 0x2
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#define S5L8702_DMAC0_PERI_LCD_WR 0x3
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#define S5L8702_DMAC0_PERI_SPI0_TX 0x4
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#define S5L8702_DMAC0_PERI_SPI0_RX 0x5
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#define S5L8702_DMAC0_PERI_UART0_TX 0x6
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#define S5L8702_DMAC0_PERI_UART0_RX 0x7
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#define S5L8702_DMAC0_PERI_UART1_TX 0x8
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#define S5L8702_DMAC0_PERI_UART1_RX 0x9
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#define S5L8702_DMAC0_PERI_IIS0_TX 0xA
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#define S5L8702_DMAC0_PERI_IIS0_RX 0xB
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#define S5L8702_DMAC0_PERI_SPI2_TX 0xC
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#define S5L8702_DMAC0_PERI_SPI2_RX 0xD
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#define S5L8702_DMAC0_PERI_SPI1_TX 0xE
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#define S5L8702_DMAC0_PERI_SPI1_RX 0xF
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/* S5L7802 DMAC1 peripherals */
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#define S5L8702_DMAC1_PERI_CEATA_WR 0x0
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#define S5L8702_DMAC1_PERI_CEATA_RD 0x1
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#define S5L8702_DMAC1_PERI_IIS1_TX 0x2
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#define S5L8702_DMAC1_PERI_IIS1_RX 0x3
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#define S5L8702_DMAC1_PERI_IIS2_TX 0x4
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#define S5L8702_DMAC1_PERI_IIS2_RX 0x5
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#define S5L8702_DMAC1_PERI_SPI1_TX 0x6
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#define S5L8702_DMAC1_PERI_SPI1_RX 0x7
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#define S5L8702_DMAC1_PERI_UART2_TX 0x8
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#define S5L8702_DMAC1_PERI_UART2_RX 0x9
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#define S5L8702_DMAC1_PERI_SPI0_TX 0xA
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#define S5L8702_DMAC1_PERI_SPI0_RX 0xB
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#define S5L8702_DMAC1_PERI_UART3_TX 0xC
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#define S5L8702_DMAC1_PERI_UART3_RX 0xD
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#define S5L8702_DMAC1_PERI_SPI2_TX 0xE
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#define S5L8702_DMAC1_PERI_SPI2_RX 0xF
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/* used when src and/or dst peripheral is memory */
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#define S5L8702_DMAC0_PERI_MEM DMAC_PERI_NONE
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#define S5L8702_DMAC1_PERI_MEM DMAC_PERI_NONE
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/* s5l8702 peripheral DMA R/W addesses */
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#define S5L8702_DADDR_PERI_LCD_WR 0x38300040
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#define S5L8702_DADDR_PERI_UNKNOWN 0x3CB00010 /* SPDIF ??? */
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#define S5L8702_DADDR_PERI_UART0_TX 0x3CC00020
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#define S5L8702_DADDR_PERI_UART0_RX 0x3CC00024
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#define S5L8702_DADDR_PERI_UART1_TX 0x3CC04020
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#define S5L8702_DADDR_PERI_UART1_RX 0x3CC04024
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#define S5L8702_DADDR_PERI_UART2_TX 0x3CC08020
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#define S5L8702_DADDR_PERI_UART2_RX 0x3CC08024
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#define S5L8702_DADDR_PERI_UART3_TX 0x3CC0C020
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#define S5L8702_DADDR_PERI_UART3_RX 0x3CC0C024
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#define S5L8702_DADDR_PERI_IIS0_TX 0x3CA00010
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#define S5L8702_DADDR_PERI_IIS0_RX 0x3CA00038
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#define S5L8702_DADDR_PERI_IIS1_TX 0x3CD00010
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#define S5L8702_DADDR_PERI_IIS1_RX 0x3CD00038
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#define S5L8702_DADDR_PERI_IIS2_TX 0x3D400010
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#define S5L8702_DADDR_PERI_IIS2_RX 0x3D400038
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#define S5L8702_DADDR_PERI_CEATA_WR 0x38A00080
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#define S5L8702_DADDR_PERI_CEATA_RD 0x38A04080
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#define S5L8702_DADDR_PERI_SPI0_TX 0x3C300010
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#define S5L8702_DADDR_PERI_SPI0_RX 0x3C300020
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#define S5L8702_DADDR_PERI_SPI1_TX 0x3CE00010
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#define S5L8702_DADDR_PERI_SPI1_RX 0x3CE00020
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#define S5L8702_DADDR_PERI_SPI2_TX 0x3D200010
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#define S5L8702_DADDR_PERI_SPI2_RX 0x3D200020
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/* proto */
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void dma_init(void);
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#endif /* _DMA_S5l8702_H */
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@ -28,6 +28,7 @@
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#include "pmu-target.h"
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#include "power.h"
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#include "string.h"
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#include "dma-s5l8702.h"
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#define R_HORIZ_GRAM_ADDR_SET 0x200
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@ -49,10 +50,8 @@
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/** globals **/
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int lcd_type; /* also needed in debug-s5l8702.c */
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static struct dma_lli lcd_lli[(LCD_WIDTH * LCD_HEIGHT - 1) / 0xfff] CACHEALIGN_ATTR;
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static struct semaphore lcd_wakeup;
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static struct mutex lcd_mutex;
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static uint16_t lcd_dblbuf[LCD_HEIGHT][LCD_WIDTH];
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static uint16_t lcd_dblbuf[LCD_HEIGHT][LCD_WIDTH] CACHEALIGN_ATTR;
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static bool lcd_ispowered;
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#define SLEEP 0
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@ -197,6 +196,48 @@ static const unsigned short lcd_init_sequence_23[] =
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};
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#endif
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/* DMA configuration */
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/* one single transfer at once, needed LLIs:
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* screen_size / (DMAC_LLI_MAX_COUNT << swidth) =
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* (320*240*2) / (4095*2) = 19
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*/
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#define LCD_DMA_TSKBUF_SZ 1 /* N tasks, MUST be pow2 */
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#define LCD_DMA_LLIBUF_SZ 32 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk lcd_dma_tskbuf[LCD_DMA_TSKBUF_SZ];
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static struct dmac_lli volatile \
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lcd_dma_llibuf[LCD_DMA_LLIBUF_SZ] CACHEALIGN_ATTR;
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static struct dmac_ch lcd_dma_ch = {
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.dmac = &s5l8702_dmac0,
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.prio = DMAC_CH_PRIO(4),
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.cb_fn = NULL,
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.tskbuf = lcd_dma_tskbuf,
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.tskbuf_mask = LCD_DMA_TSKBUF_SZ - 1,
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.queue_mode = QUEUE_NORMAL,
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.llibuf = lcd_dma_llibuf,
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.llibuf_mask = LCD_DMA_LLIBUF_SZ - 1,
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.llibuf_bus = DMAC_MASTER_AHB1,
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};
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static struct dmac_ch_cfg lcd_dma_ch_cfg = {
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.srcperi = S5L8702_DMAC0_PERI_MEM,
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.dstperi = S5L8702_DMAC0_PERI_LCD_WR,
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.sbsize = DMACCxCONTROL_BSIZE_1,
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.dbsize = DMACCxCONTROL_BSIZE_1,
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.swidth = DMACCxCONTROL_WIDTH_16,
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.dwidth = DMACCxCONTROL_WIDTH_16,
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.sbus = DMAC_MASTER_AHB1,
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.dbus = DMAC_MASTER_AHB1,
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.sinc = DMACCxCONTROL_INC_ENABLE,
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.dinc = DMACCxCONTROL_INC_DISABLE,
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.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
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.lli_xfer_max_count = DMAC_LLI_MAX_COUNT,
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};
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static inline void s5l_lcd_write_reg(int cmd, unsigned int data)
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{
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while (LCD_STATUS & 0x10);
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@ -328,12 +369,14 @@ void lcd_awake(void)
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void lcd_init_device(void)
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{
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/* Detect lcd type */
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semaphore_init(&lcd_wakeup, 1, 0);
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mutex_init(&lcd_mutex);
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lcd_type = (PDAT6 & 0x30) >> 4;
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while (!(LCD_STATUS & 0x2));
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LCD_CONFIG = 0x80100db0;
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/* Configure DMA channel */
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dmac_ch_init(&lcd_dma_ch, &lcd_dma_ch_cfg);
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lcd_ispowered = true;
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}
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@ -362,8 +405,10 @@ extern void lcd_write_line(const fb_data *addr,
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static void displaylcd_setup(int x, int y, int width, int height) ICODE_ATTR;
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static void displaylcd_setup(int x, int y, int width, int height)
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{
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/* TODO: ISR()->panicf()->lcd_update() blocks forever */
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mutex_lock(&lcd_mutex);
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while (DMAC0C4CONFIG & 1) semaphore_wait(&lcd_wakeup, HZ / 10);
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while (dmac_ch_running(&lcd_dma_ch))
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yield();
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int xe = (x + width) - 1; /* max horiz */
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int ye = (y + height) - 1; /* max vert */
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@ -398,31 +443,12 @@ static void displaylcd_setup(int x, int y, int width, int height)
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static void displaylcd_dma(int pixels) ICODE_ATTR;
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static void displaylcd_dma(int pixels)
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{
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int i;
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void* data = lcd_dblbuf;
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for (i = -1; i < (int)ARRAYLEN(lcd_lli) && pixels > 0; i++, pixels -= 0xfff)
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{
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bool last = i + 1 >= (int)ARRAYLEN(lcd_lli) || pixels <= 0xfff;
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struct dma_lli* lli = i < 0 ? (struct dma_lli*)((int)&DMAC0C4LLI) : &lcd_lli[i];
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lli->srcaddr = data;
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lli->dstaddr = (void*)((int)&LCD_WDATA);
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lli->nextlli = last ? NULL : &lcd_lli[i + 1];
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lli->control = 0x70240000 | (last ? pixels : 0xfff)
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| (last ? 0x80000000 : 0) | 0x4000000;
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data += 0x1ffe;
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}
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commit_dcache();
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DMAC0C4CONFIG = 0x88c1;
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dmac_ch_queue(&lcd_dma_ch, lcd_dblbuf,
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(void*)S5L8702_DADDR_PERI_LCD_WR, pixels*2, NULL);
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mutex_unlock(&lcd_mutex);
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}
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void INT_DMAC0C4(void) ICODE_ATTR;
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void INT_DMAC0C4(void)
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{
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DMAC0INTTCCLR = 0x10;
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semaphore_release(&lcd_wakeup);
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}
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/* Update a fraction of the display. */
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void lcd_update_rect(int, int, int, int) ICODE_ATTR;
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void lcd_update_rect(int x, int y, int width, int height)
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@ -31,104 +31,129 @@
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#include "pcm_sampr.h"
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#include "mmu-arm.h"
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#include "pcm-target.h"
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#include "dma-s5l8702.h"
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/* DMA configuration */
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/* 3 DMA tasks needed, one chunk task and two dblbuf tasks */
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#define DMA_PLAY_TSKBUF_SZ 4 /* N tasks, MUST be pow2 */
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#define DMA_PLAY_LLIBUF_SZ 4 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk dma_play_tskbuf[DMA_PLAY_TSKBUF_SZ];
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static struct dmac_lli volatile \
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dma_play_llibuf[DMA_PLAY_LLIBUF_SZ] CACHEALIGN_ATTR;
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|
||||
static void dma_play_callback(void *data) ICODE_ATTR;
|
||||
|
||||
static struct dmac_ch dma_play_ch = {
|
||||
.dmac = &s5l8702_dmac0,
|
||||
.prio = DMAC_CH_PRIO(2),
|
||||
.cb_fn = dma_play_callback,
|
||||
|
||||
.tskbuf = dma_play_tskbuf,
|
||||
.tskbuf_mask = DMA_PLAY_TSKBUF_SZ - 1,
|
||||
.queue_mode = QUEUE_LINK,
|
||||
|
||||
.llibuf = dma_play_llibuf,
|
||||
.llibuf_mask = DMA_PLAY_LLIBUF_SZ - 1,
|
||||
.llibuf_bus = DMAC_MASTER_AHB1,
|
||||
};
|
||||
|
||||
static struct dmac_ch_cfg dma_play_ch_cfg = {
|
||||
.srcperi = S5L8702_DMAC0_PERI_MEM,
|
||||
.dstperi = S5L8702_DMAC0_PERI_IIS0_TX,
|
||||
.sbsize = DMACCxCONTROL_BSIZE_8,
|
||||
.dbsize = DMACCxCONTROL_BSIZE_4,
|
||||
.swidth = DMACCxCONTROL_WIDTH_16,
|
||||
.dwidth = DMACCxCONTROL_WIDTH_16,
|
||||
.sbus = DMAC_MASTER_AHB1,
|
||||
.dbus = DMAC_MASTER_AHB1,
|
||||
.sinc = DMACCxCONTROL_INC_ENABLE,
|
||||
.dinc = DMACCxCONTROL_INC_DISABLE,
|
||||
.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
|
||||
/* align LLI transfers to L-R pairs (samples) */
|
||||
.lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
|
||||
};
|
||||
#define LLI_MAX_BYTES 8188 /* lli_xfer_max_count << swidth */
|
||||
|
||||
/* Use all available LLIs for chunk */
|
||||
/*#define CHUNK_MAX_BYTES (LLI_MAX_BYTES * (DMA_PLAY_LLIBUF_SZ - 2))*/
|
||||
#define CHUNK_MAX_BYTES (LLI_MAX_BYTES * 1)
|
||||
#define WATERMARK_BYTES (PCM_WATERMARK * 4)
|
||||
|
||||
static volatile int locked = 0;
|
||||
static const int zerosample = 0;
|
||||
static unsigned char dblbuf[2][PCM_WATERMARK * 4];
|
||||
static unsigned char dblbuf[2][WATERMARK_BYTES] CACHEALIGN_ATTR;
|
||||
static int active_dblbuf;
|
||||
struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
|
||||
static struct dma_lli* lastlli;
|
||||
static const void* dataptr;
|
||||
size_t pcm_remaining;
|
||||
size_t pcm_chunksize;
|
||||
|
||||
/* Mask the DMA interrupt */
|
||||
void pcm_play_lock(void)
|
||||
{
|
||||
if (locked++ == 0) {
|
||||
//TODO: Urgh, I don't like that at all...
|
||||
VIC0INTENCLEAR = 1 << IRQ_DMAC0;
|
||||
}
|
||||
if (locked++ == 0)
|
||||
dmac_ch_lock_int(&dma_play_ch);
|
||||
}
|
||||
|
||||
/* Unmask the DMA interrupt if enabled */
|
||||
void pcm_play_unlock(void)
|
||||
{
|
||||
if (--locked == 0) {
|
||||
VIC0INTENABLE = 1 << IRQ_DMAC0;
|
||||
}
|
||||
if (--locked == 0)
|
||||
dmac_ch_unlock_int(&dma_play_ch);
|
||||
}
|
||||
|
||||
void INT_DMAC0C0(void) ICODE_ATTR;
|
||||
void INT_DMAC0C0(void)
|
||||
static inline void play_queue_dma(void *addr, size_t size, void *cb_data)
|
||||
{
|
||||
DMAC0INTTCCLR = 1;
|
||||
commit_dcache_range(addr, size);
|
||||
dmac_ch_queue(&dma_play_ch, addr,
|
||||
(void*)S5L8702_DADDR_PERI_IIS0_TX, size, cb_data);
|
||||
}
|
||||
|
||||
static void dma_play_callback(void *cb_data)
|
||||
{
|
||||
if (!cb_data)
|
||||
return; /* dblbuf callback entered, nothing to do */
|
||||
|
||||
const void *dataptr = cb_data;
|
||||
|
||||
if (!pcm_remaining)
|
||||
{
|
||||
pcm_play_dma_complete_callback(PCM_DMAST_OK, &dataptr, &pcm_remaining);
|
||||
pcm_chunksize = pcm_remaining;
|
||||
}
|
||||
if (!pcm_remaining)
|
||||
{
|
||||
pcm_lli->nextlli = NULL;
|
||||
pcm_lli->control = 0x7524a000;
|
||||
commit_dcache();
|
||||
return;
|
||||
}
|
||||
uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
|
||||
if (!pcm_play_dma_complete_callback(
|
||||
PCM_DMAST_OK, &dataptr, &pcm_remaining))
|
||||
return;
|
||||
|
||||
uint32_t lastsize = MIN(WATERMARK_BYTES, pcm_remaining >> 1);
|
||||
pcm_remaining -= lastsize;
|
||||
if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
|
||||
else lastlli = pcm_lli;
|
||||
uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
|
||||
if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
|
||||
chunksize = pcm_remaining - PCM_WATERMARK * 8;
|
||||
uint32_t chunksize = MIN(CHUNK_MAX_BYTES, pcm_remaining);
|
||||
|
||||
/* last chunk should be at least 2*WATERMARK_BYTES in size */
|
||||
if ((pcm_remaining > chunksize) &&
|
||||
(pcm_remaining < chunksize + WATERMARK_BYTES * 2))
|
||||
chunksize = pcm_remaining - WATERMARK_BYTES * 2;
|
||||
|
||||
pcm_remaining -= chunksize;
|
||||
bool last = !chunksize;
|
||||
int i = 0;
|
||||
while (chunksize)
|
||||
{
|
||||
uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
|
||||
chunksize -= thislli;
|
||||
pcm_lli[i].srcaddr = (void*)dataptr;
|
||||
pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
|
||||
pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
|
||||
pcm_lli[i].control = (chunksize ? 0x7524a000 : 0xf524a000) | (thislli / 2);
|
||||
dataptr += thislli;
|
||||
i++;
|
||||
}
|
||||
if (!pcm_remaining)
|
||||
{
|
||||
memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
|
||||
lastlli->srcaddr = dblbuf[active_dblbuf];
|
||||
active_dblbuf ^= 1;
|
||||
}
|
||||
else lastlli->srcaddr = dataptr;
|
||||
lastlli->dstaddr = (void*)((int)&I2STXDB0);
|
||||
lastlli->nextlli = last ? NULL : pcm_lli;
|
||||
lastlli->control = (last ? 0xf524a000 : 0x7524a000) | (lastsize / 2);
|
||||
dataptr += lastsize;
|
||||
commit_dcache();
|
||||
if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
|
||||
{
|
||||
DMAC0C0LLI = pcm_lli[0];
|
||||
DMAC0C0CONFIG = 0x8a81;
|
||||
}
|
||||
else DMAC0C0NEXTLLI = pcm_lli;
|
||||
|
||||
/* first part */
|
||||
play_queue_dma((void*)dataptr, chunksize,
|
||||
(void*)dataptr + chunksize + lastsize); /* cb_data */
|
||||
|
||||
/* second part */
|
||||
memcpy(dblbuf[active_dblbuf], dataptr + chunksize, lastsize);
|
||||
play_queue_dma(dblbuf[active_dblbuf], lastsize, NULL);
|
||||
active_dblbuf ^= 1;
|
||||
|
||||
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
|
||||
}
|
||||
|
||||
void pcm_play_dma_start(const void* addr, size_t size)
|
||||
{
|
||||
dataptr = addr;
|
||||
pcm_play_dma_stop();
|
||||
|
||||
pcm_remaining = size;
|
||||
I2STXCOM = 0xe;
|
||||
INT_DMAC0C0();
|
||||
dma_play_callback((void*)addr);
|
||||
}
|
||||
|
||||
void pcm_play_dma_stop(void)
|
||||
{
|
||||
DMAC0C0CONFIG = 0x8a80;
|
||||
dmac_ch_stop(&dma_play_ch);
|
||||
I2STXCOM = 0xa;
|
||||
}
|
||||
|
||||
|
|
@ -184,9 +209,11 @@ void pcm_play_dma_init(void)
|
|||
{
|
||||
PWRCON(0) &= ~(1 << 4);
|
||||
PWRCON(1) &= ~(1 << 7);
|
||||
|
||||
dmac_ch_init(&dma_play_ch, &dma_play_ch_cfg);
|
||||
|
||||
I2STXCON = 0xb100019;
|
||||
I2SCLKCON = 1;
|
||||
VIC0INTENABLE = 1 << IRQ_DMAC0;
|
||||
|
||||
audiohw_preinit();
|
||||
pcm_dma_apply_settings();
|
||||
|
|
@ -199,21 +226,16 @@ void pcm_play_dma_postinit(void)
|
|||
|
||||
size_t pcm_get_bytes_waiting(void)
|
||||
{
|
||||
int bytes = pcm_remaining;
|
||||
const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
|
||||
while (lli)
|
||||
{
|
||||
bytes += (lli->control & 0xfff) * 2;
|
||||
if (lli == lastlli) break;
|
||||
lli = lli->nextlli;
|
||||
}
|
||||
return bytes;
|
||||
size_t total_bytes;
|
||||
dmac_ch_get_info(&dma_play_ch, NULL, &total_bytes);
|
||||
return total_bytes;
|
||||
}
|
||||
|
||||
const void* pcm_play_dma_get_peak_buffer(int *count)
|
||||
{
|
||||
*count = (DMAC0C0LLI.control & 0xfff) * 2;
|
||||
return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
|
||||
void *addr = dmac_ch_get_info(&dma_play_ch, count, NULL);
|
||||
*count >>= 2; /* bytes to samples */
|
||||
return addr; /* aligned to dest burst */
|
||||
}
|
||||
|
||||
#ifdef HAVE_PCM_DMA_ADDRESS
|
||||
|
|
|
|||
|
|
@ -23,18 +23,7 @@
|
|||
|
||||
|
||||
/* S5L8702 PCM driver tunables: */
|
||||
#define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */
|
||||
#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
|
||||
/* (bigger chunks will be segmented internally) */
|
||||
#define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */
|
||||
|
||||
|
||||
#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
|
||||
|
||||
|
||||
extern struct dma_lli pcm_lli[PCM_LLICOUNT];
|
||||
extern size_t pcm_remaining;
|
||||
extern size_t pcm_chunksize;
|
||||
|
||||
|
||||
#endif /* __PCM_TARGET_H__ */
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include "system-target.h"
|
||||
#include "pmu-target.h"
|
||||
#include "gpio-s5l8702.h"
|
||||
#include "dma-s5l8702.h"
|
||||
|
||||
#define default_interrupt(name) \
|
||||
extern __attribute__((weak,alias("UIRQ"))) void name (void)
|
||||
|
|
@ -55,22 +56,8 @@ default_interrupt(INT_IRQ12);
|
|||
default_interrupt(INT_IRQ13);
|
||||
default_interrupt(INT_IRQ14);
|
||||
default_interrupt(INT_IRQ15);
|
||||
default_interrupt(INT_DMAC0C0);
|
||||
default_interrupt(INT_DMAC0C1);
|
||||
default_interrupt(INT_DMAC0C2);
|
||||
default_interrupt(INT_DMAC0C3);
|
||||
default_interrupt(INT_DMAC0C4);
|
||||
default_interrupt(INT_DMAC0C5);
|
||||
default_interrupt(INT_DMAC0C6);
|
||||
default_interrupt(INT_DMAC0C7);
|
||||
default_interrupt(INT_DMAC1C0);
|
||||
default_interrupt(INT_DMAC1C1);
|
||||
default_interrupt(INT_DMAC1C2);
|
||||
default_interrupt(INT_DMAC1C3);
|
||||
default_interrupt(INT_DMAC1C4);
|
||||
default_interrupt(INT_DMAC1C5);
|
||||
default_interrupt(INT_DMAC1C6);
|
||||
default_interrupt(INT_DMAC1C7);
|
||||
default_interrupt(INT_DMAC0);
|
||||
default_interrupt(INT_DMAC1);
|
||||
default_interrupt(INT_IRQ18);
|
||||
default_interrupt(INT_USB_FUNC);
|
||||
default_interrupt(INT_IRQ20);
|
||||
|
|
@ -141,34 +128,6 @@ void INT_TIMER32()
|
|||
if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH();
|
||||
}
|
||||
|
||||
void INT_DMAC0(void) ICODE_ATTR;
|
||||
void INT_DMAC0()
|
||||
{
|
||||
uint32_t intsts = DMAC0INTSTS;
|
||||
if (intsts & 1) INT_DMAC0C0();
|
||||
if (intsts & 2) INT_DMAC0C1();
|
||||
if (intsts & 4) INT_DMAC0C2();
|
||||
if (intsts & 8) INT_DMAC0C3();
|
||||
if (intsts & 0x10) INT_DMAC0C4();
|
||||
if (intsts & 0x20) INT_DMAC0C5();
|
||||
if (intsts & 0x40) INT_DMAC0C6();
|
||||
if (intsts & 0x80) INT_DMAC0C7();
|
||||
}
|
||||
|
||||
void INT_DMAC1(void) ICODE_ATTR;
|
||||
void INT_DMAC1()
|
||||
{
|
||||
uint32_t intsts = DMAC1INTSTS;
|
||||
if (intsts & 1) INT_DMAC1C0();
|
||||
if (intsts & 2) INT_DMAC1C1();
|
||||
if (intsts & 4) INT_DMAC1C2();
|
||||
if (intsts & 8) INT_DMAC1C3();
|
||||
if (intsts & 0x10) INT_DMAC1C4();
|
||||
if (intsts & 0x20) INT_DMAC1C5();
|
||||
if (intsts & 0x40) INT_DMAC1C6();
|
||||
if (intsts & 0x80) INT_DMAC1C7();
|
||||
}
|
||||
|
||||
static void (* const irqvector[])(void) =
|
||||
{
|
||||
INT_EXT0,INT_EXT1,INT_EXT2,INT_EXT3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_TIMER32,
|
||||
|
|
@ -225,6 +184,7 @@ void system_init(void)
|
|||
{
|
||||
/*gpio_init();*/
|
||||
pmu_init();
|
||||
dma_init();
|
||||
VIC0INTENABLE = 1 << IRQ_WHEEL;
|
||||
VIC0INTENABLE = 1 << IRQ_ATA;
|
||||
VIC1INTENABLE = 1 << (IRQ_MMC - 32);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue