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jz74x0: MSC clock needs to be divided from PLL clock.

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Change-Id: I0cf2f0d55e0859f896afef289e833935d7c5a599
This commit is contained in:
Solomon Peachy 2018-08-30 08:28:19 -04:00
parent 72820d8b2d
commit 679a0bd193
2 changed files with 7 additions and 2 deletions
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4
firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c
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@ -612,8 +612,10 @@ static inline unsigned int jz_sd_calc_clkrt(unsigned int rate)
static inline void cpm_select_msc_clk(unsigned int rate)
{
unsigned int div = __cpm_get_pllout2() / rate;
if (div == 0)
div = 1;
REG_CPM_MSCCDR = div - 1;
REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1);
}
/* Set the MMC clock frequency */

5
firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c
View file

@ -647,8 +647,11 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate)
static inline void cpm_select_msc_clk(unsigned int rate)
{
unsigned int div = __cpm_get_pllout2() / rate;
if (div == 0)
div = 1;
REG_CPM_MSCCDR = div - 1;
REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1);
DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR);
}
/* Set the MMC clock frequency */