From 66bc0728d5e422ff26496140f168b8a49540be08 Mon Sep 17 00:00:00 2001 From: Andrew Rice Date: Sat, 12 Sep 2026 22:41:36 +1000 Subject: [PATCH] ipodnano3g: preserve PMU register 0x10 bit 2, which the NAND needs pmu_preinit() masked register 0x10 with 0xdb, which clears bits 2 and 5. With bit 2 clear the NAND chip does not answer and nand_init() fails. Masking with 0xdf clears only bit 5 and leaves bit 2 alone. Measured on a 4GB Nano 3G. Every build that had worked carried debug PMU reads, i.e. extra I2C delay, so delay was the confound to rule out and each mask was tried with and without it: 0xdb, no extra delay dead 0xdb, extra delay dead 0xdf, extra delay reads (3 runs) 0xdf, no extra delay reads One early 0xdf build without instrumentation failed once (rc=-1). That has not been explained; the final validation run is the same configuration and reads correctly. Reading the register back after pmu_preinit() gives 0xdf. The new mask keeps bit 2 and "| 0x8" only sets bit 3, so bit 2 is set as the BootROM left it - the old mask was clearing it. Bit 5 is hidden by the mask, so what the ROM leaves there is not known. What bit 2 does is not established. The old comment guessed "bit4 is related to NAND, LDO_0x15 on/off"; the register does sit among the NAND supply settings (0x15 reads back the value commented as Vnand), but no datasheet was consulted, so the new comment states only the observed effect. AI provenance: developed with Claude Opus 5 (Anthropic), used through Claude Code. The model wrote most of the code and this message under Andrew Rice's direction. Any hardware testing described above was carried out by Andrew Rice, who is responsible for this change. Change-Id: Iee73f876b7b6a5c85e09f8bf1c5ac174a49409e0 --- firmware/target/arm/s5l8702/ipodnano3g/pmu-nano3g.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/target/arm/s5l8702/ipodnano3g/pmu-nano3g.c b/firmware/target/arm/s5l8702/ipodnano3g/pmu-nano3g.c index c7cfebf7fc..08f0ef6ff9 100644 --- a/firmware/target/arm/s5l8702/ipodnano3g/pmu-nano3g.c +++ b/firmware/target/arm/s5l8702/ipodnano3g/pmu-nano3g.c @@ -339,7 +339,7 @@ void pmu_preinit(void) pmu_wr(0x16, 0x14); pmu_wr(0x15, 0x14); // TBC: Vnand = 2000 + val*50 = 3000 mV pmu_wr(0x18, 0x18); // TBC TBC TBC: Vaccy = 3200 mV ??? - pmu_wr(0x10, (pmu_rd(0x10) & 0xdb) | 0x8); // TBC: bit4 is related to NAND, LDO_0x15 on/off ??? + pmu_wr(0x10, (pmu_rd(0x10) & 0xdf) | 0x8); /* keep bit 2: NAND needs it */ // TBC: 0x30, 0x31 y 0x32 seems related to ADC (norboot) pmu_wr(0x34, 0x72); // TBC: en DA9030: TBATHIGH (0-255, TBAT high temperature threshold