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https://github.com/Rockbox/rockbox.git
synced 2025-12-08 12:45:26 -05:00
Remove Linux's mmci.h since the license is strict GPLv2
Rewrite a new header distributed under GPLv2 or later, and place it in export/ in case other targets ship with an ARM PL180 controller git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18959 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
e8753f3b25
commit
646cac0bde
3 changed files with 85 additions and 143 deletions
65
firmware/export/pl180.h
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65
firmware/export/pl180.h
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@ -0,0 +1,65 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* ARM PrimeCell PL180 SD/MMC controller */
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/* MCIStatus bits */
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#define MCI_CMD_CRC_FAIL (1<<0)
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#define MCI_DATA_CRC_FAIL (1<<1)
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#define MCI_CMD_TIMEOUT (1<<2)
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#define MCI_DATA_TIMEOUT (1<<3)
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#define MCI_TX_UNDERRUN (1<<4)
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#define MCI_RX_OVERRUN (1<<5)
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#define MCI_CMD_RESP_END (1<<6)
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#define MCI_CMD_SENT (1<<7)
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#define MCI_DATA_END (1<<8)
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#define MCI_START_BIT_ERR (1<<9)
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#define MCI_DATA_BLOCK_END (1<<10)
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#define MCI_CMD_ACTIVE (1<<11)
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/* MCIPower bits */
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#define MCI_POWER_OFF 0x0
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/* 0x1 is reserved */
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#define MCI_POWER_UP 0x2
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#define MCI_POWER_ON 0x3
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/* bits 5:2 are the voltage */
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#define MCI_POWER_OPEN_DRAIN (1<<6)
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#define MCI_POWER_ROD (1<<7)
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/* MCIClock bits */
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/* bits 7:0 are the clock divider */
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#define MCI_CLOCK_ENABLE (1<<8)
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#define MCI_CLOCK_POWERSAVE (1<<9)
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#define MCI_CLOCK_BYPASS (1<<10)
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#define MCI_CLOCK_WIDEBUS (1<<11)
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/* MCICommand bits */
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/* bits 5:0 are the command index */
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#define MCI_COMMAND_RESPONSE (1<<6)
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#define MCI_COMMAND_LONG_RESPONSE (1<<7)
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#define MCI_COMMAND_INTERRUPT (1<<8)
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#define MCI_COMMAND_PENDING (1<<9)
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#define MCI_COMMAND_ENABLE (1<<10)
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@ -24,7 +24,7 @@
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#include "config.h" /* for HAVE_MULTIVOLUME */
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#include "as3525.h"
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#include "mmci.h"
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#include "pl180.h"
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#include "panic.h"
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#include "stdbool.h"
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#include "ata.h"
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@ -87,7 +87,7 @@ static void mci_set_clock_divider(const int drive, int divider)
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if(divider > 1)
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{
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/* use divide logic */
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clock &= ~MCI_CLK_BYPASS;
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clock &= ~MCI_CLOCK_BYPASS;
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/* convert divider to MMC_CLOCK logic */
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divider = (divider/2) - 1;
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@ -97,7 +97,7 @@ static void mci_set_clock_divider(const int drive, int divider)
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else
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{
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/* bypass dividing logic */
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clock |= MCI_CLK_BYPASS;
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clock |= MCI_CLOCK_BYPASS;
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divider = 0;
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}
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@ -110,20 +110,20 @@ static int send_cmd(const int drive, struct mmc_command *cmd)
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{
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int val, status;
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while(MMC_STATUS(drive) & MCI_CMDACTIVE); /* useless */
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while(MMC_STATUS(drive) & MCI_CMD_ACTIVE); /* useless */
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if(MMC_COMMAND(drive) & MCI_CPSM_ENABLE) /* clears existing command */
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if(MMC_COMMAND(drive) & MCI_COMMAND_ENABLE) /* clears existing command */
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{
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MMC_COMMAND(drive) = 0;
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mci_delay();
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}
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val = cmd->cmd | MCI_CPSM_ENABLE;
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val = cmd->cmd | MCI_COMMAND_ENABLE;
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if(cmd->flags & MMC_RESP)
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{
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val |= MCI_CPSM_RESPONSE;
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val |= MCI_COMMAND_RESPONSE;
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if(cmd->flags & MMC_LONG_RESP)
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val |= MCI_CPSM_LONGRSP;
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val |= MCI_COMMAND_LONG_RESPONSE;
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}
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MMC_CLEAR(drive) = 0x7ff;
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@ -131,7 +131,7 @@ static int send_cmd(const int drive, struct mmc_command *cmd)
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MMC_ARGUMENT(drive) = (cmd->flags & MMC_ARG) ? cmd->arg : 0;
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MMC_COMMAND(drive) = val;
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while(MMC_STATUS(drive) & MCI_CMDACTIVE);
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while(MMC_STATUS(drive) & MCI_CMD_ACTIVE);
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MMC_COMMAND(drive) = 0;
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MMC_ARGUMENT(drive) = ~0;
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@ -141,13 +141,13 @@ static int send_cmd(const int drive, struct mmc_command *cmd)
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status = MMC_STATUS(drive);
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if(cmd->flags & MMC_RESP)
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{
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if(status & MCI_CMDTIMEOUT)
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if(status & MCI_CMD_TIMEOUT)
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{
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if(cmd->cmd == SEND_IF_COND)
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break; /* SDHC test can fail */
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panicf("Response timeout");
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}
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else if(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND))
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else if(status & (MCI_CMD_CRC_FAIL|MCI_CMD_RESP_END))
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{ /* resp received */
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cmd->resp[0] = MMC_RESP0(drive);
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if(cmd->flags & MMC_LONG_RESP)
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@ -160,7 +160,7 @@ static int send_cmd(const int drive, struct mmc_command *cmd)
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}
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}
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else
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if(status & MCI_CMDSENT)
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if(status & MCI_CMD_SENT)
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break;
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} while(1);
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@ -183,7 +183,7 @@ static void sd_init_card(const int drive)
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cmd_idle.cmd = GO_IDLE_STATE;
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cmd_idle.arg = 0;
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cmd_idle.flags = MMC_NO_FLAGS;
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if(send_cmd(drive, &cmd_idle) != MCI_CMDSENT)
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if(send_cmd(drive, &cmd_idle) != MCI_CMD_SENT)
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panicf("goto idle failed!");
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#ifdef DEBUG
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else
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@ -209,7 +209,7 @@ static void sd_init_card(const int drive)
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sdhc = false;
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status = send_cmd(drive, &cmd_if_cond);
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if(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND))
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if(status & (MCI_CMD_CRC_FAIL|MCI_CMD_RESP_END))
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{
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if((cmd_if_cond.resp[0] & 0xFFF) == cmd_if_cond.arg)
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sdhc = true;
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@ -240,7 +240,7 @@ static void sd_init_card(const int drive)
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#endif
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/* app_cmd */
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status = send_cmd(drive, &cmd_app);
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if( !(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND)) ||
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if( !(status & (MCI_CMD_CRC_FAIL|MCI_CMD_RESP_END)) ||
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!(cmd_app.resp[0] & (1<<5)) )
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{
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panicf("app_cmd failed");
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@ -248,7 +248,7 @@ static void sd_init_card(const int drive)
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cmd_op_cond.arg = sdhc ? 0x40FF8000 : (8<<0x14); /* ocr */
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status = send_cmd(drive, &cmd_op_cond);
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if(!(status & (MCI_CMDCRCFAIL|MCI_CMDRESPEND)))
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if(!(status & (MCI_CMD_CRC_FAIL|MCI_CMD_RESP_END)))
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panicf("cmd_op_cond failed");
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#ifdef DEBUG
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@ -268,16 +268,16 @@ static void init_pl180_controller(const int drive)
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MMC_MASK0(drive) = MMC_MASK1(drive) = 0; /* disable all interrupts */
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MMC_POWER(drive) = MCI_PWR_UP | (10 /*voltage*/ << 2); /* use OF voltage */
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MMC_POWER(drive) = MCI_POWER_UP|(10 /*voltage*/ << 2); /* use OF voltage */
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mci_delay();
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MMC_POWER(drive) |= MCI_PWR_ON;
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MMC_POWER(drive) |= MCI_POWER_ON;
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mci_delay();
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MMC_SELECT(drive) = 0;
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MMC_CLOCK(drive) = MCI_CLK_ENABLE;
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MMC_CLOCK(drive) &= ~MCI_CLK_PWRSAVE;
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MMC_CLOCK(drive) = MCI_CLOCK_ENABLE;
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MMC_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE;
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/* set MCLK divider */
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mci_set_clock_divider(drive, 200);
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@ -1,123 +0,0 @@
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/*
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* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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//#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_ROD (1 << 7)
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//#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_BYPASS (1 << 10)
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#define MCI_WIDEBUS (1 << 11)
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//#define MMCIARGUMENT 0x008
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//#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_INTERRUPT (1 << 8)
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#define MCI_CPSM_PENDING (1 << 9)
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#define MCI_CPSM_ENABLE (1 << 10)
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#if 0
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#endif
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_DPSM_MODE (1 << 2)
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#define MCI_DPSM_DMAENABLE (1 << 3)
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//#define MMCIDATACNT 0x030
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//#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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//#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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//#define MMCIMASK0 0x03c
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#define MCI_CMDCRCFAILMASK (1 << 0)
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#define MCI_DATACRCFAILMASK (1 << 1)
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#define MCI_CMDTIMEOUTMASK (1 << 2)
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#define MCI_DATATIMEOUTMASK (1 << 3)
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#define MCI_TXUNDERRUNMASK (1 << 4)
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#define MCI_RXOVERRUNMASK (1 << 5)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_RXACTIVEMASK (1 << 13)
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#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
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#define MCI_RXFIFOHALFFULLMASK (1 << 15)
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#define MCI_TXFIFOFULLMASK (1 << 16)
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#define MCI_RXFIFOFULLMASK (1 << 17)
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#define MCI_TXFIFOEMPTYMASK (1 << 18)
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#define MCI_RXFIFOEMPTYMASK (1 << 19)
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#define MCI_TXDATAAVLBLMASK (1 << 20)
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#define MCI_RXDATAAVLBLMASK (1 << 21)
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#if 0
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#define MMCIMASK1 0x040
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#define MMCIFIFOCNT 0x048
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#define MMCIFIFO 0x080 /* to 0x0bc */
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#endif
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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#define NR_SG 16
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