mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-09 05:05:20 -05:00
Refine the routines in mmu-arm.c and move them to mmu-arm.S since the code is now 100% assembly.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19980 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
00a9685985
commit
63e709c7c8
8 changed files with 515 additions and 346 deletions
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@ -57,13 +57,6 @@ void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
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#define KDEV_INIT
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#define HAVE_CPUCACHE_INVALIDATE
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#define HAVE_CPUCACHE_FLUSH
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/* Different internal names */
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#define cpucache_flush clean_dcache
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#define cpucache_invalidate invalidate_idcache
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struct ARM_REGS {
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int r0;
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int r1;
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487
firmware/target/arm/mmu-arm.S
Normal file
487
firmware/target/arm/mmu-arm.S
Normal file
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@ -0,0 +1,487 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#if CONFIG_CPU == IMX31L
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/* TTB routines not used */
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/** Cache coherency **/
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/*
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* Invalidate DCache for this range
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* will do write back
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* void invalidate_dcache_range(const void *base, unsigned int size)
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache_range
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.type invalidate_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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invalidate_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache_range, .-invalidate_dcache_range
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/*
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* clean DCache for this range
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* forces DCache writeback for the specified range
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* void clean_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache_range
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.type clean_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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clean_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache_range, .-clean_dcache_range
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/*
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* Dump DCache for this range
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void dump_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global dump_dcache_range
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.type dump_dcache_range, %function
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@ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ
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@ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
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dump_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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sub r1, r1, #32 @ Move to the previous cache line
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cmp r1, r0 @ end < start now?
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mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size dump_dcache_range, .-dump_dcache_range
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache
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.type clean_dcache, %function
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.global cpucache_flush @ Alias
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clean_dcache:
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cpucache_flush:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache, .-clean_dcache
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/*
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* Invalidate entire DCache
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* will do writeback
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* void invalidate_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache
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.type invalidate_dcache, %function
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invalidate_dcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache, .-invalidate_dcache
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/*
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* Invalidate entire ICache and DCache
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* will do writeback
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* void invalidate_idcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_idcache
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.type invalidate_idcache, %function
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.global cpucache_invalidate @ Alias
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invalidate_idcache:
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cpucache_invalidate:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
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@ Also flushes the branch target cache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
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bx lr @
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.size invalidate_idcache, .-invalidate_idcache
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#else /* !IMX31L */
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/** MMU setup **/
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/*
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* void ttb_init(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global ttb_init
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.type ttb_init, %function
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ttb_init:
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ldr r0, =TTB_BASE_ADDR @
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mvn r1, #0 @
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mcr p15, 0, r0, c2, c0, 0 @ Set the TTB base address
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mcr p15, 0, r1, c3, c0, 0 @ Set all domains to manager status
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bx lr @
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.size ttb_init, .-ttb_init
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/*
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* void map_section(unsigned int pa, unsigned int va, int mb, int flags);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global map_section
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.type map_section, %function
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map_section:
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@ align to 1MB
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@ pa &= (-1 << 20);
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mov r0, r0, lsr #20
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mov r0, r0, lsl #20
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@ pa |= (flags | 0x412);
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@ bit breakdown:
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@ 10: superuser - r/w, user - no access
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@ 4: should be "1"
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@ 3,2: Cache flags (flags (r3))
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@ 1: Section signature
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orr r0, r0, r3
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orr r0, r0, #0x410
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orr r0, r0, #0x2
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@ unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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@ sections are 1MB size
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mov r1, r1, lsr #20
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ldr r3, =TTB_BASE_ADDR
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add r1, r3, r1, lsl #0x2
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@ Add MB to pa, flags are already present in pa, but addition
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@ should not effect them
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@
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@ for( ; mb>0; mb--, pa += (1 << 20))
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@ {
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@ *(ttbPtr++) = pa;
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@ }
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cmp r2, #0
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bxle lr
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mov r3, #0x0
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1: @ loop
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str r0, [r1], #4
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add r0, r0, #0x100000
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add r3, r3, #0x1
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cmp r2, r3
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bne 1b @ loop
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bx lr
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.size map_section, .-map_section
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/*
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* void enable_mmu(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global enable_mmu
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.type enable_mmu, %function
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enable_mmu:
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mov r0, #0 @
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLB
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mcr p15, 0, r0, c7, c7,0 @ invalidate both i and dcache
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mrc p15, 0, r0, c1, c0, 0 @
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orr r0, r0, #1 @ enable mmu bit, i and dcache
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orr r0, r0, #1<<2 @ enable dcache
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orr r0, r0, #1<<12 @ enable icache
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mcr p15, 0, r0, c1, c0, 0 @
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nop @
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nop @
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nop @
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nop @
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bx lr @
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.size enable_mmu, .-enable_mmu
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.ltorg
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/** Cache coherency **/
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/*
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* Invalidate DCache for this range
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* will do write back
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* void invalidate_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache_range
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.type invalidate_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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invalidate_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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bic r0, r0, #31 @ Align start to cache line (down)
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1: @ inv_start @
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mcr p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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add r0, r0, #32 @
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cmp r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @ inv_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size invalidate_dcache_range, .-invalidate_dcache_range
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/*
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* clean DCache for this range
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* forces DCache writeback for the specified range
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* void clean_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache_range
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.type clean_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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clean_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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bic r0, r0, #31 @ Align start to cache line (down)
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1: @ clean_start @
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mcr p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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add r0, r0, #32 @
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cmp r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @clean_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size clean_dcache_range, .-clean_dcache_range
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/*
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* Dump DCache for this range
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void dump_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global dump_dcache_range
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.type dump_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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dump_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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cmp r1, r0 @ end <= start now?
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1: @ dump_start @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @ dump_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size dump_dcache_range, .-dump_dcache_range
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .text, "ax", %progbits
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||||
.align 2
|
||||
.global clean_dcache
|
||||
.type clean_dcache, %function
|
||||
.global cpucache_flush @ Alias
|
||||
clean_dcache:
|
||||
cpucache_flush:
|
||||
@ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ
|
||||
mov r0, #0x00000000 @
|
||||
1: @ clean_start @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
|
||||
sub r0, r0, #0x000000e0 @
|
||||
adds r0, r0, #0x04000000 @ will wrap to zero at loop end
|
||||
bne 1b @ clean_start @
|
||||
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
|
||||
bx lr @
|
||||
.size clean_dcache, .-clean_dcache
|
||||
|
||||
/*
|
||||
* Invalidate entire DCache
|
||||
* will do writeback
|
||||
* void invalidate_dcache(void);
|
||||
*/
|
||||
.section .text, "ax", %progbits
|
||||
.align 2
|
||||
.global invalidate_dcache
|
||||
.type invalidate_dcache, %function
|
||||
invalidate_dcache:
|
||||
@ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ
|
||||
mov r0, #0x00000000 @
|
||||
1: @ inv_start @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
add r0, r0, #0x00000020 @
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
|
||||
sub r0, r0, #0x000000e0 @
|
||||
adds r0, r0, #0x04000000 @ will wrap to zero at loop end
|
||||
bne 1b @ inv_start @
|
||||
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
|
||||
bx lr @
|
||||
.size invalidate_dcache, .-invalidate_dcache
|
||||
|
||||
/*
|
||||
* Invalidate entire ICache and DCache
|
||||
* will do writeback
|
||||
* void invalidate_idcache(void);
|
||||
*/
|
||||
.section .text, "ax", %progbits
|
||||
.align 2
|
||||
.global invalidate_idcache
|
||||
.type invalidate_idcache, %function
|
||||
.global cpucache_invalidate @ Alias
|
||||
invalidate_idcache:
|
||||
cpucache_invalidate:
|
||||
mov r1, lr @ save lr to r1, call uses r0 only
|
||||
bl invalidate_dcache @ Clean and invalidate entire DCache
|
||||
mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call)
|
||||
mov pc, r1 @
|
||||
.size invalidate_idcache, .-invalidate_idcache
|
||||
|
||||
#endif /* !IMX31L */
|
||||
|
||||
|
|
@ -1,322 +0,0 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2006,2007 by Greg White
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#include "cpu.h"
|
||||
#include "mmu-arm.h"
|
||||
#include "panic.h"
|
||||
|
||||
void __attribute__((naked)) ttb_init(void) {
|
||||
asm volatile
|
||||
(
|
||||
"mcr p15, 0, %[ttbB], c2, c0, 0 \n" /* Set the TTB base address */
|
||||
"mcr p15, 0, %[ffff], c3, c0, 0 \n" /* Set all domains to manager status */
|
||||
"bx lr \n"
|
||||
:
|
||||
: [ttbB] "r" (TTB_BASE),
|
||||
[ffff] "r" (0xFFFFFFFF)
|
||||
);
|
||||
}
|
||||
|
||||
void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb, int flags) {
|
||||
asm volatile
|
||||
(
|
||||
/* pa &= (-1 << 20); // align to 1MB */
|
||||
"mov r0, r0, lsr #20 \n"
|
||||
"mov r0, r0, lsl #20 \n"
|
||||
|
||||
/* pa |= (flags | 0x412);
|
||||
* bit breakdown:
|
||||
* 10: superuser - r/w, user - no access
|
||||
* 4: should be "1"
|
||||
* 3,2: Cache flags (flags (r3))
|
||||
* 1: Section signature
|
||||
*/
|
||||
|
||||
"orr r0, r0, r3 \n"
|
||||
"orr r0, r0, #0x410 \n"
|
||||
"orr r0, r0, #0x2 \n"
|
||||
:
|
||||
:
|
||||
);
|
||||
|
||||
register unsigned long *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */
|
||||
|
||||
asm volatile
|
||||
(
|
||||
/* unsigned int* ttbPtr = TTB_BASE + (va >> 20);
|
||||
* sections are 1MB size
|
||||
*/
|
||||
|
||||
"mov r1, r1, lsr #20 \n"
|
||||
"add r1, %[ttbB], r1, lsl #0x2 \n"
|
||||
|
||||
/* Add MB to pa, flags are already present in pa, but addition
|
||||
* should not effect them
|
||||
*
|
||||
* #define MB (1 << 20)
|
||||
* for( ; mb>0; mb--, pa += MB)
|
||||
* {
|
||||
* *(ttbPtr++) = pa;
|
||||
* }
|
||||
* #undef MB
|
||||
*/
|
||||
|
||||
"cmp r2, #0 \n"
|
||||
"bxle lr \n"
|
||||
"mov r3, #0x0 \n"
|
||||
"loop: \n"
|
||||
"str r0, [r1], #4 \n"
|
||||
"add r0, r0, #0x100000 \n"
|
||||
"add r3, r3, #0x1 \n"
|
||||
"cmp r2, r3 \n"
|
||||
"bne loop \n"
|
||||
"bx lr \n"
|
||||
:
|
||||
: [ttbB] "r" (ttb_base) /* This /HAS/ to be in r3 */
|
||||
);
|
||||
(void) pa;
|
||||
(void) va;
|
||||
(void) mb;
|
||||
(void) flags;
|
||||
}
|
||||
|
||||
void __attribute__((naked)) enable_mmu(void) {
|
||||
asm volatile(
|
||||
"mov r0, #0 \n"
|
||||
"mcr p15, 0, r0, c8, c7, 0 \n" /* invalidate TLB */
|
||||
"mcr p15, 0, r0, c7, c7,0 \n" /* invalidate both icache and dcache */
|
||||
"mrc p15, 0, r0, c1, c0, 0 \n"
|
||||
"orr r0, r0, #1 \n" /* enable mmu bit, icache and dcache */
|
||||
"orr r0, r0, #1<<2 \n" /* enable dcache */
|
||||
"orr r0, r0, #1<<12 \n" /* enable icache */
|
||||
"mcr p15, 0, r0, c1, c0, 0 \n"
|
||||
"nop \n"
|
||||
"nop \n"
|
||||
"nop \n"
|
||||
"nop \n"
|
||||
"bx lr \n"
|
||||
:
|
||||
:
|
||||
: "r0"
|
||||
);
|
||||
}
|
||||
|
||||
#if CONFIG_CPU == IMX31L
|
||||
void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned int size)
|
||||
{
|
||||
asm volatile(
|
||||
"add r1, r1, r0 \n"
|
||||
"mov r2, #0 \n"
|
||||
"mcrr p15, 0, r1, r0, c14 \n" /* Clean and invalidate dcache range */
|
||||
"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
|
||||
"bx lr \n"
|
||||
);
|
||||
(void)base; (void)size;
|
||||
}
|
||||
#else
|
||||
/* Invalidate DCache for this range */
|
||||
/* Will do write back */
|
||||
void invalidate_dcache_range(const void *base, unsigned int size) {
|
||||
unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
|
||||
unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
|
||||
asm volatile(
|
||||
"inv_start: \n"
|
||||
"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"add %0, %0, #32 \n"
|
||||
"cmp %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
|
||||
"addne %0, %0, #32 \n"
|
||||
"cmpne %0, %1 \n"
|
||||
"bne inv_start \n"
|
||||
"mov %0, #0\n"
|
||||
"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
|
||||
: : "r" (addr), "r" (end)
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if CONFIG_CPU == IMX31L
|
||||
void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int size)
|
||||
{
|
||||
asm volatile(
|
||||
"add r1, r1, r0 \n"
|
||||
"mov r2, #0 \n"
|
||||
"mcrr p15, 0, r1, r0, c12 \n" /* Clean dcache range */
|
||||
"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
|
||||
"bx lr \n"
|
||||
);
|
||||
(void)base; (void)size;
|
||||
}
|
||||
#else
|
||||
/* clean DCache for this range */
|
||||
/* forces DCache writeback for the specified range */
|
||||
void clean_dcache_range(const void *base, unsigned int size) {
|
||||
unsigned int addr = (int) base;
|
||||
unsigned int end = addr+size+32;
|
||||
asm volatile(
|
||||
"bic %0, %0, #31 \n"
|
||||
"clean_start: \n"
|
||||
"mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"add %0, %0, #32 \n"
|
||||
"cmp %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
|
||||
"addlo %0, %0, #32 \n"
|
||||
"cmplo %0, %1 \n"
|
||||
"blo clean_start \n"
|
||||
"mov %0, #0\n"
|
||||
"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
|
||||
: : "r" (addr), "r" (end));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_CPU == IMX31L
|
||||
void __attribute__((naked)) dump_dcache_range(const void *base, unsigned int size)
|
||||
{
|
||||
asm volatile(
|
||||
"add r1, r1, r0 \n"
|
||||
"mcrr p15, 0, r1, r0, c6 \n"
|
||||
"bx lr \n"
|
||||
);
|
||||
(void)base; (void)size;
|
||||
}
|
||||
#else
|
||||
/* Dump DCache for this range */
|
||||
/* Will *NOT* do write back */
|
||||
void dump_dcache_range(const void *base, unsigned int size) {
|
||||
unsigned int addr = (int) base;
|
||||
unsigned int end = addr+size;
|
||||
asm volatile(
|
||||
"tst %0, #31 \n" /* Check to see if low five bits are set */
|
||||
"bic %0, %0, #31 \n" /* Clear them */
|
||||
"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */
|
||||
"add %0, %0, #32 \n" /* Move to the next cache line */
|
||||
"tst %1, #31 \n" /* Check last line for bits set */
|
||||
"bic %1, %1, #31 \n" /* Clear those bits */
|
||||
"mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */
|
||||
"dump_start: \n"
|
||||
"mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */
|
||||
"add %0, %0, #32 \n" /* Next cache line */
|
||||
"cmp %0, %1 \n"
|
||||
"bne dump_start \n"
|
||||
"dump_end: \n"
|
||||
"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
|
||||
: : "r" (addr), "r" (end));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_CPU == IMX31L
|
||||
void __attribute__((naked)) clean_dcache(void)
|
||||
{
|
||||
asm volatile (
|
||||
/* Clean entire data cache */
|
||||
"mov r0, #0 \n"
|
||||
"mcr p15, 0, r0, c7, c10, 0 \n"
|
||||
/* Data synchronization barrier */
|
||||
"mcr p15, 0, r0, c7, c10, 4 \n"
|
||||
"bx lr \n"
|
||||
);
|
||||
}
|
||||
#else
|
||||
/* Cleans entire DCache */
|
||||
void clean_dcache(void)
|
||||
{
|
||||
unsigned int index, addr, low;
|
||||
|
||||
for(index = 0; index <= 63; index++)
|
||||
{
|
||||
for(low = 0;low <= 7; low++)
|
||||
{
|
||||
addr = (index << 26) | (low << 5);
|
||||
asm volatile
|
||||
(
|
||||
"mcr p15, 0, %[addr], c7, c10, 2 \n" /* Clean this entry by index */
|
||||
:
|
||||
: [addr] "r" (addr)
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_CPU == IMX31L
|
||||
void invalidate_idcache(void)
|
||||
{
|
||||
asm volatile(
|
||||
/* Clean and invalidate entire data cache */
|
||||
"mcr p15, 0, %0, c7, c14, 0 \n"
|
||||
/* Invalidate entire instruction cache
|
||||
* Also flushes the branch target cache */
|
||||
"mcr p15, 0, %0, c7, c5, 0 \n"
|
||||
/* Data synchronization barrier */
|
||||
"mcr p15, 0, %0, c7, c10, 4 \n"
|
||||
/* Flush prefetch buffer */
|
||||
"mcr p15, 0, %0, c7, c5, 4 \n"
|
||||
: : "r"(0)
|
||||
);
|
||||
}
|
||||
#else
|
||||
void invalidate_idcache(void)
|
||||
{
|
||||
clean_dcache();
|
||||
asm volatile(
|
||||
"mov r0, #0 \n"
|
||||
"mcr p15, 0, r0, c7, c5, 0 \n"
|
||||
: : : "r0"
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -18,11 +18,14 @@
|
|||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef MMU_ARM_H
|
||||
#define MMY_ARM_H
|
||||
|
||||
#define CACHE_ALL 0x0C
|
||||
#define CACHE_NONE 0
|
||||
#define BUFFERED 0x04
|
||||
|
||||
void memory_init(void);
|
||||
void ttb_init(void);
|
||||
void enable_mmu(void);
|
||||
void map_section(unsigned int pa, unsigned int va, int mb, int flags);
|
||||
|
|
@ -30,8 +33,12 @@ void map_section(unsigned int pa, unsigned int va, int mb, int flags);
|
|||
/* Cleans entire DCache */
|
||||
void clean_dcache(void);
|
||||
|
||||
/* Invalidate entire DCache */
|
||||
/* will do writeback */
|
||||
void invalidate_dcache(void);
|
||||
|
||||
/* Invalidate DCache for this range */
|
||||
/* Will do write back */
|
||||
/* will do writeback */
|
||||
void invalidate_dcache_range(const void *base, unsigned int size);
|
||||
|
||||
/* clean DCache for this range */
|
||||
|
|
@ -39,7 +46,14 @@ void invalidate_dcache_range(const void *base, unsigned int size);
|
|||
void clean_dcache_range(const void *base, unsigned int size);
|
||||
|
||||
/* Dump DCache for this range */
|
||||
/* Will *NOT* do write back */
|
||||
/* Will *NOT* do write back except for buffer ends not on a line boundary */
|
||||
void dump_dcache_range(const void *base, unsigned int size);
|
||||
|
||||
void memory_init(void);
|
||||
/* Invalidate entire ICache and DCache */
|
||||
/* will do writeback */
|
||||
void invalidate_idcache(void);
|
||||
|
||||
#define HAVE_CPUCACHE_INVALIDATE
|
||||
#define HAVE_CPUCACHE_FLUSH
|
||||
|
||||
#endif /* MMU_ARM_H */
|
||||
|
|
|
|||
|
|
@ -41,9 +41,4 @@ void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
|
|||
/* Clear register bits */
|
||||
void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
|
||||
|
||||
#define HAVE_CPUCACHE_FLUSH
|
||||
#define HAVE_CPUCACHE_INVALIDATE
|
||||
#define cpucache_flush clean_dcache
|
||||
#define cpucache_invalidate invalidate_idcache
|
||||
|
||||
#endif /* SYSTEM_TARGET_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue