mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-10-14 02:27:39 -04:00
Gigabeat: Use vectored IRQ mode interrupts and add a trap for unhandled ones.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13792 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
21b90e3466
commit
60efd38bbe
5 changed files with 201 additions and 42 deletions
27
apps/main.c
27
apps/main.c
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@ -558,6 +558,33 @@ static void init(void)
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#if CONFIG_CHARGING
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car_adapter_mode_init();
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#endif
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int fd = creat("/timer_regs.txt");
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if (fd >= 0)
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{
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fdprintf(fd, "TCFG0: %08X\n", TCFG0);
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fdprintf(fd, "TCFG1: %08X\n", TCFG1);
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fdprintf(fd, "TCON: %08X\n", TCON);
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fdprintf(fd, "TCFG0: %08X\n", TCFG0);
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fdprintf(fd, "TCNTB0: %08X\n", TCNTB0);
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fdprintf(fd, "TCMPB0: %08X\n", TCMPB0);
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fdprintf(fd, "TCNTO0: %08X\n", TCNTO0);
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fdprintf(fd, "TCNTB1: %08X\n", TCNTB1);
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fdprintf(fd, "TCMPB1: %08X\n", TCMPB1);
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fdprintf(fd, "TCNTO1: %08X\n", TCNTO1);
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fdprintf(fd, "TCNTB2: %08X\n", TCNTB2);
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fdprintf(fd, "TCMPB2: %08X\n", TCMPB2);
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fdprintf(fd, "TCNTO2: %08X\n", TCNTO2);
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fdprintf(fd, "TCNTB3: %08X\n", TCNTB3);
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fdprintf(fd, "TCMPB3: %08X\n", TCMPB3);
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fdprintf(fd, "TCNTO3: %08X\n", TCNTO3);
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fdprintf(fd, "TCNTB4: %08X\n", TCNTB4);
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fdprintf(fd, "TCNTO4: %08X\n", TCNTO4);
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close(fd);
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}
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}
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#ifdef CPU_PP
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@ -16,6 +16,8 @@
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __S3C2440_H__
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#define __S3C2440_H__
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/* Memory Controllers */
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@ -74,6 +76,86 @@
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#define SUBSRCPND (*(volatile int *)0x4A000018) /* Sub source pending */
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#define INTSUBMSK (*(volatile int *)0x4A00001C) /* Interrupt sub mask */
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/* Interrupt indexes - INTOFFSET - IRQ mode only */
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/* Arbiter 5 => Arbiter 6 Req 5 */
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#define ADC_OFFSET 31 /* REQ4 */
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#define RTC_OFFSET 30 /* REQ3 */
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#define SPI1_OFFSET 29 /* REQ2 */
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#define UART0_OFFSET 28 /* REQ1 */
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/* Arbiter 4 => Arbiter 6 Req 4 */
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#define IIC_OFFSET 27 /* REQ5 */
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#define USBH_OFFSET 26 /* REQ4 */
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#define USBD_OFFSET 25 /* REQ3 */
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#define NFCON_OFFSET 24 /* REQ2 */
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#define UART1_OFFSET 23 /* REQ1 */
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#define SPI0_OFFSET 22 /* REQ0 */
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/* Arbiter 3 => Arbiter 6 Req 3 */
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#define SDI_OFFSET 21 /* REQ5 */
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#define DMA3_OFFSET 20 /* REQ4 */
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#define DMA2_OFFSET 19 /* REQ3 */
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#define DMA1_OFFSET 18 /* REQ2 */
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#define DMA0_OFFSET 17 /* REQ1 */
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#define LCD_OFFSET 16 /* REQ0 */
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/* Arbiter 2 => Arbiter 6 Req 2 */
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#define UART2_OFFSET 15 /* REQ5 */
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#define TIMER4_OFFSET 14 /* REQ4 */
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#define TIMER3_OFFSET 13 /* REQ3 */
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#define TIMER2_OFFSET 12 /* REQ2 */
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#define TIMER1_OFFSET 11 /* REQ1 */
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#define TIMER0_OFFSET 10 /* REQ0 */
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/* Arbiter 1 => Arbiter 6 Req 1 */
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#define WDT_AC97_OFFSET 9 /* REQ5 */
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#define TICK_OFFSET 8 /* REQ4 */
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#define nBATT_FLT_OFFSET 7 /* REQ3 */
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#define CAM_OFFSET 6 /* REQ2 */
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#define EINT8_23_OFFSET 5 /* REQ1 */
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#define EINT4_7_OFFSET 4 /* REQ0 */
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/* Arbiter 0 => Arbiter 6 Req 0 */
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#define EINT3_OFFSET 3 /* REQ4 */
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#define EINT2_OFFSET 2 /* REQ3 */
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#define EINT1_OFFSET 1 /* REQ2 */
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#define EINT0_OFFSET 0 /* REQ1 */
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/* Interrupt bitmasks - SRCPND, INTMOD, INTMSK, INTPND */
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/* Arbiter 5 => Arbiter 6 Req 5 */
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#define ADC_MASK (1 << 31) /* REQ4 */
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#define RTC_MASK (1 << 30) /* REQ3 */
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#define SPI1_MASK (1 << 29) /* REQ2 */
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#define UART0_MASK (1 << 28) /* REQ1 */
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/* Arbiter 4 => Arbiter 6 Req 4 */
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#define IIC_MASK (1 << 27) /* REQ5 */
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#define USBH_MASK (1 << 26) /* REQ4 */
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#define USBD_MASK (1 << 25) /* REQ3 */
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#define NFCON_MASK (1 << 24) /* REQ2 */
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#define UART1_MASK (1 << 23) /* REQ1 */
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#define SPI0_MASK (1 << 22) /* REQ0 */
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/* Arbiter 3 => Arbiter 6 Req 3 */
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#define SDI_MASK (1 << 21) /* REQ5 */
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#define DMA3_MASK (1 << 20) /* REQ4 */
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#define DMA2_MASK (1 << 19) /* REQ3 */
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#define DMA1_MASK (1 << 18) /* REQ2 */
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#define DMA0_MASK (1 << 17) /* REQ1 */
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#define LCD_MASK (1 << 16) /* REQ0 */
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/* Arbiter 2 => Arbiter 6 Req 2 */
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#define UART2_MASK (1 << 15) /* REQ5 */
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#define TIMER4_MASK (1 << 14) /* REQ4 */
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#define TIMER3_MASK (1 << 13) /* REQ3 */
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#define TIMER2_MASK (1 << 12) /* REQ2 */
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#define TIMER1_MASK (1 << 11) /* REQ1 */
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#define TIMER0_MASK (1 << 10) /* REQ0 */
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/* Arbiter 1 => Arbiter 6 Req 1 */
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#define WDT_AC97_MASK (1 << 9) /* REQ5 */
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#define TICK_MASK (1 << 8) /* REQ4 */
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#define nBATT_FLT_MASK (1 << 7) /* REQ3 */
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#define CAM_MASK (1 << 6) /* REQ2 */
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#define EINT8_23_MASK (1 << 5) /* REQ1 */
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#define EINT4_7_MASK (1 << 4) /* REQ0 */
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/* Arbiter 0 => Arbiter 6 Req 0 */
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#define EINT3_MASK (1 << 3) /* REQ4 */
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#define EINT2_MASK (1 << 2) /* REQ3 */
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#define EINT1_MASK (1 << 1) /* REQ2 */
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#define EINT0_MASK (1 << 0) /* REQ1 */
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/* DMA */
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#define DISRC0 (*(volatile int *)0x4B000000) /* DMA 0 initial source */
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@ -465,3 +547,4 @@
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#define DRAM1 0x31000000
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#define BOOTRAM 0x40000000
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#endif /* __S3C2440_H__ */
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@ -724,8 +724,13 @@ void tick_start(unsigned int interval_in_ms)
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INTMSK &= ~(1 << 14); // timer 4 unmask interrupts
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}
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void timer4(void) {
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void TIMER4(void)
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{
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int i;
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SRCPND = TIMER4_MASK;
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INTPND = TIMER4_MASK;
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/* Run through the list of tick tasks */
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for(i = 0; i < MAX_NUM_TICK_TASKS; i++)
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{
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@ -736,9 +741,6 @@ void timer4(void) {
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}
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current_tick++;
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/* following needs to be fixed. */
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/*wake_up_thread();*/
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}
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#endif
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@ -198,14 +198,6 @@ data_abort_handler:
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mov r1, #2
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b UIE
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irq_handler:
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#ifndef STUB
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stmfd sp!, {r0-r11, r12, lr}
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bl irq
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ldmfd sp!, {r0-r11, r12, lr}
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#endif
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subs pc, lr, #4
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#ifdef STUB
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UIE:
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b UIE
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@ -3,44 +3,83 @@
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#include "panic.h"
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#include "mmu-meg-fx.h"
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#include "lcd.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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enum
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default_interrupt(EINT0);
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default_interrupt(EINT1);
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default_interrupt(EINT2);
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default_interrupt(EINT3);
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default_interrupt(EINT4_7);
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default_interrupt(EINT8_23);
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default_interrupt(CAM);
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default_interrupt(nBATT_FLT);
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default_interrupt(TICK);
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default_interrupt(WDT_AC97);
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default_interrupt(TIMER0);
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default_interrupt(TIMER1);
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default_interrupt(TIMER2);
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default_interrupt(TIMER3);
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default_interrupt(TIMER4);
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default_interrupt(UART2);
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default_interrupt(LCD);
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default_interrupt(DMA0);
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default_interrupt(DMA1);
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default_interrupt(DMA2);
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default_interrupt(DMA3);
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default_interrupt(SDI);
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default_interrupt(SPI0);
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default_interrupt(UART1);
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default_interrupt(NFCON);
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default_interrupt(USBD);
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default_interrupt(USBH);
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default_interrupt(IIC);
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default_interrupt(UART0);
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default_interrupt(SPI1);
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default_interrupt(RTC);
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default_interrupt(ADC);
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static void (* const irqvector[32])(void) =
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{
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TIMER4_MASK = (1 << 14),
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LCD_MASK = (1 << 16),
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DMA0_MASK = (1 << 17),
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DMA1_MASK = (1 << 18),
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DMA2_MASK = (1 << 19),
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DMA3_MASK = (1 << 20),
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ALARM_MASK = (1 << 30),
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EINT0, EINT1, EINT2, EINT3,
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EINT4_7, EINT8_23, CAM, nBATT_FLT, TICK, WDT_AC97,
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TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, UART2,
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LCD, DMA0, DMA1, DMA2, DMA3, SDI,
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SPI0, UART1, NFCON, USBD, IIC,
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UART0, SPI1, RTC, ADC,
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};
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int system_memory_guard(int newmode)
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static const char * const irqname[32] =
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{
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(void)newmode;
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return 0;
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"EINT0", "EINT1", "EINT2", "EINT3",
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"EINT4_7", "EINT8_23", "CAM", "nBATT_FLT", "TICK", "WDT_AC97",
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"TIMER0", "TIMER1", "TIMER2", "TIMER3", "TIMER4", "UART2",
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"LCD", "DMA0", "DMA1", "DMA2", "DMA3", "SDI",
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"SPI0", "UART1", "NFCON", "USBD", "USBH", "IIC",
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"UART0", "SPI1", "RTC", "ADC"
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};
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static void UIRQ(void)
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{
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unsigned int offset = INTOFFSET;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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extern void timer4(void);
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extern void dma0(void); /* free */
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extern void dma1(void);
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extern void dma3(void);
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void irq(void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void irq_handler(void)
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{
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int intpending = INTPND;
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SRCPND = intpending; /* Clear this interrupt. */
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INTPND = intpending; /* Clear this interrupt. */
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/* Timer 4 */
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if ((intpending & TIMER4_MASK) != 0)
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timer4();
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else
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{
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/* unexpected interrupt */
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}
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asm volatile (
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"sub lr, lr, #4 \r\n"
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"stmfd sp!, {r0-r3, ip, lr} \r\n"
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"mov r0, #0x4a000000 \r\n" /* INTOFFSET = 0x4a000014 */
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"add r0, r0, #0x00000014 \r\n"
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"ldr r0, [r0] \r\n"
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"ldr r1, =irqvector \r\n"
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"ldr r1, [r1, r0, lsl #2] \r\n"
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"mov lr, pc \r\n"
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"bx r1 \r\n"
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"ldmfd sp!, {r0-r3, ip, pc}^ \r\n"
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);
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}
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void system_reboot(void)
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@ -54,6 +93,17 @@ void system_reboot(void)
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void system_init(void)
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{
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/* Disable interrupts and set all to IRQ mode */
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INTMSK = -1;
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INTMOD = 0;
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SRCPND = -1;
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INTPND = -1;
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INTSUBMSK = -1;
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SUBSRCPND = -1;
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/* TODO: do something with PRIORITY */
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/* Turn off currently-not or never-needed devices */
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CLKCON &= ~(
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@ -90,6 +140,11 @@ void system_init(void)
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CLKSLOW |= (1 << 7);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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