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Bulk convert all DOS line endings to UNIX.

Browse source 
For the git migration we want a nice clean repository with UNIX line
endings. git does not use svn:eol-style, we just need the file contents to be
sane.

Sorry everybody. I know this messes up blame.

Scumbag *NIX developer says migrating to git will make line ending issues go
away; commits giant change to svn which changes line endings anyway. :)


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30924 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Torne Wuff 2011-11-06 22:44:25 +00:00
parent d9b7d58fa6
commit 569285794b
59 changed files with 24428 additions and 24428 deletions
Download patch file Download diff file Expand all files Collapse all files

490
firmware/drivers/audio/cs42l55.c
View file

@ -1,245 +1,245 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $
*
* Driver for Cirrus Logic CS42L55 audio codec
*
* Copyright (c) 2010 Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "logf.h"
#include "system.h"
#include "string.h"
#include "audio.h"
#include "sound.h"
#include "audiohw.h"
#include "cscodec.h"
#include "cs42l55.h"
const struct sound_settings_info audiohw_settings[] = {
[SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25},
[SOUND_BASS] = {"dB", 1, 15,-105, 120, 0},
[SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0},
[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2},
[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
};
static int bass, treble;
/* convert tenth of dB volume (-600..120) to master volume register value */
int tenthdb2master(int db)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
if (db < VOLUME_MIN) return HPACTL_HPAMUTE;
return (db / 10) & HPACTL_HPAVOL_MASK;
}
static void cscodec_setbits(int reg, unsigned char off, unsigned char on)
{
unsigned char data = (cscodec_read(reg) & ~off) | on;
cscodec_write(reg, data);
}
static void audiohw_mute(bool mute)
{
if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0);
}
void audiohw_preinit(void)
{
cscodec_power(true);
cscodec_clock(true);
cscodec_reset(true);
sleep(HZ / 100);
cscodec_reset(false);
bass = 0;
treble = 0;
/* Ask Cirrus or maybe Apple what the hell this means */
cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK);
cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT);
cscodec_write(HIDDEN32, HIDDEN32_DEFAULT);
cscodec_write(HIDDEN33, HIDDEN33_DEFAULT);
cscodec_write(HIDDEN34, HIDDEN34_DEFAULT);
cscodec_write(HIDDEN35, HIDDEN35_DEFAULT);
cscodec_write(HIDDEN36, HIDDEN36_DEFAULT);
cscodec_write(HIDDEN37, HIDDEN37_DEFAULT);
cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT);
cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT);
cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT);
cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT);
cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT);
cscodec_write(HIDDENCTL, HIDDENCTL_LOCK);
cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS
| PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER);
cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE
| CLKCTL1_MCLKDIV2);
cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP
| PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
cscodec_write(PGAACTL, 0);
cscodec_write(PGABCTL, 0);
cscodec_write(HPACTL, HPACTL_HPAMUTE);
cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB);
}
void audiohw_postinit(void)
{
cscodec_write(HPACTL, 0);
cscodec_write(HPBCTL, 0);
cscodec_write(LINEACTL, 0);
cscodec_write(LINEBCTL, 0);
cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL);
audiohw_mute(false);
}
void audiohw_set_master_vol(int vol_l, int vol_r)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE,
vol_l << HPACTL_HPAVOL_SHIFT);
cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE,
vol_r << HPBCTL_HPBVOL_SHIFT);
}
void audiohw_set_lineout_vol(int vol_l, int vol_r)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE,
vol_l << LINEACTL_LINEAVOL_SHIFT);
cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE,
vol_r << LINEBCTL_LINEBVOL_SHIFT);
}
void audiohw_enable_lineout(bool enable)
{
if (enable)
cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER);
else
cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS);
}
static void handle_dsp_power(void)
{
if (bass || treble)
{
cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0);
cscodec_setbits(BTCTL, 0, BTCTL_TCEN);
}
else
{
cscodec_setbits(BTCTL, BTCTL_TCEN, 0);
cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP);
}
}
void audiohw_set_bass(int value)
{
bass = value;
handle_dsp_power();
if (value >= -105 && value <= 120)
cscodec_setbits(TONECTL, TONECTL_BASS_MASK,
(8 - value / 15) << TONECTL_BASS_SHIFT);
}
void audiohw_set_treble(int value)
{
treble = value;
handle_dsp_power();
if (value >= -105 && value <= 120)
cscodec_setbits(TONECTL, TONECTL_TREB_MASK,
(8 - value / 15) << TONECTL_TREB_SHIFT);
}
void audiohw_set_bass_cutoff(int value)
{
cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK,
(value - 1) << BTCTL_BASSCF_SHIFT);
}
void audiohw_set_treble_cutoff(int value)
{
cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK,
(value - 1) << BTCTL_TREBCF_SHIFT);
}
void audiohw_set_prescaler(int value)
{
cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK,
(-value / 5) << MSTAVOL_VOLUME_SHIFT);
cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK,
(-value / 5) << MSTBVOL_VOLUME_SHIFT);
}
/* Nice shutdown of CS42L55 codec */
void audiohw_close(void)
{
audiohw_mute(true);
cscodec_write(HPACTL, HPACTL_HPAMUTE);
cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
cscodec_reset(true);
cscodec_clock(false);
cscodec_power(false);
}
/* Note: Disable output before calling this function */
void audiohw_set_frequency(int fsel)
{
if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ);
else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ);
else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ);
else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ);
else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ);
else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ);
else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ);
else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ);
}
#ifdef HAVE_RECORDING
//TODO: Implement
#endif /* HAVE_RECORDING */
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: wm8975.c 28572 2010-11-13 11:38:38Z theseven $
*
* Driver for Cirrus Logic CS42L55 audio codec
*
* Copyright (c) 2010 Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "logf.h"
#include "system.h"
#include "string.h"
#include "audio.h"
#include "sound.h"
#include "audiohw.h"
#include "cscodec.h"
#include "cs42l55.h"
const struct sound_settings_info audiohw_settings[] = {
[SOUND_VOLUME] = {"dB", 0, 1, -60, 12, -25},
[SOUND_BASS] = {"dB", 1, 15,-105, 120, 0},
[SOUND_TREBLE] = {"dB", 1, 15,-105, 120, 0},
[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 2},
[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
};
static int bass, treble;
/* convert tenth of dB volume (-600..120) to master volume register value */
int tenthdb2master(int db)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
if (db < VOLUME_MIN) return HPACTL_HPAMUTE;
return (db / 10) & HPACTL_HPAVOL_MASK;
}
static void cscodec_setbits(int reg, unsigned char off, unsigned char on)
{
unsigned char data = (cscodec_read(reg) & ~off) | on;
cscodec_write(reg, data);
}
static void audiohw_mute(bool mute)
{
if (mute) cscodec_setbits(PLAYCTL, 0, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
else cscodec_setbits(PLAYCTL, PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE, 0);
}
void audiohw_preinit(void)
{
cscodec_power(true);
cscodec_clock(true);
cscodec_reset(true);
sleep(HZ / 100);
cscodec_reset(false);
bass = 0;
treble = 0;
/* Ask Cirrus or maybe Apple what the hell this means */
cscodec_write(HIDDENCTL, HIDDENCTL_UNLOCK);
cscodec_write(HIDDEN2E, HIDDEN2E_DEFAULT);
cscodec_write(HIDDEN32, HIDDEN32_DEFAULT);
cscodec_write(HIDDEN33, HIDDEN33_DEFAULT);
cscodec_write(HIDDEN34, HIDDEN34_DEFAULT);
cscodec_write(HIDDEN35, HIDDEN35_DEFAULT);
cscodec_write(HIDDEN36, HIDDEN36_DEFAULT);
cscodec_write(HIDDEN37, HIDDEN37_DEFAULT);
cscodec_write(HIDDEN3A, HIDDEN3A_DEFAULT);
cscodec_write(HIDDEN3C, HIDDEN3C_DEFAULT);
cscodec_write(HIDDEN3D, HIDDEN3D_DEFAULT);
cscodec_write(HIDDEN3E, HIDDEN3E_DEFAULT);
cscodec_write(HIDDEN3F, HIDDEN3F_DEFAULT);
cscodec_write(HIDDENCTL, HIDDENCTL_LOCK);
cscodec_write(PWRCTL2, PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS
| PWRCTL2_PDN_HPA_NEVER | PWRCTL2_PDN_HPB_NEVER);
cscodec_write(CLKCTL1, CLKCTL1_MASTER | CLKCTL1_SCLKMCLK_BEFORE
| CLKCTL1_MCLKDIV2);
cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
cscodec_write(MISCCTL, MISCCTL_UNDOC4 | MISCCTL_ANLGZC | MISCCTL_DIGSFT);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
cscodec_write(PLAYCTL, PLAYCTL_PDN_DSP
| PLAYCTL_MSTAMUTE | PLAYCTL_MSTBMUTE);
cscodec_write(PGAACTL, 0);
cscodec_write(PGABCTL, 0);
cscodec_write(HPACTL, HPACTL_HPAMUTE);
cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB);
}
void audiohw_postinit(void)
{
cscodec_write(HPACTL, 0);
cscodec_write(HPBCTL, 0);
cscodec_write(LINEACTL, 0);
cscodec_write(LINEBCTL, 0);
cscodec_write(CLSHCTL, CLSHCTL_ADPTPWR_SIGNAL);
audiohw_mute(false);
}
void audiohw_set_master_vol(int vol_l, int vol_r)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
cscodec_setbits(HPACTL, HPACTL_HPAVOL_MASK | HPACTL_HPAMUTE,
vol_l << HPACTL_HPAVOL_SHIFT);
cscodec_setbits(HPBCTL, HPBCTL_HPBVOL_MASK | HPBCTL_HPBMUTE,
vol_r << HPBCTL_HPBVOL_SHIFT);
}
void audiohw_set_lineout_vol(int vol_l, int vol_r)
{
/* -60dB to +12dB in 1dB steps */
/* 0001100 == +12dB (0xc) */
/* 0000000 == 0dB (0x0) */
/* 1000100 == -60dB (0x44, this is actually -58dB) */
cscodec_setbits(LINEACTL, LINEACTL_LINEAVOL_MASK | LINEACTL_LINEAMUTE,
vol_l << LINEACTL_LINEAVOL_SHIFT);
cscodec_setbits(LINEBCTL, LINEBCTL_LINEBVOL_MASK | LINEBCTL_LINEBMUTE,
vol_r << LINEBCTL_LINEBVOL_SHIFT);
}
void audiohw_enable_lineout(bool enable)
{
if (enable)
cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
PWRCTL2_PDN_LINA_NEVER | PWRCTL2_PDN_LINB_NEVER);
else
cscodec_setbits(PWRCTL2, PWRCTL2_PDN_LINA_MASK | PWRCTL2_PDN_LINB_MASK,
PWRCTL2_PDN_LINA_ALWAYS | PWRCTL2_PDN_LINB_ALWAYS);
}
static void handle_dsp_power(void)
{
if (bass || treble)
{
cscodec_setbits(PLAYCTL, PLAYCTL_PDN_DSP, 0);
cscodec_setbits(BTCTL, 0, BTCTL_TCEN);
}
else
{
cscodec_setbits(BTCTL, BTCTL_TCEN, 0);
cscodec_setbits(PLAYCTL, 0, PLAYCTL_PDN_DSP);
}
}
void audiohw_set_bass(int value)
{
bass = value;
handle_dsp_power();
if (value >= -105 && value <= 120)
cscodec_setbits(TONECTL, TONECTL_BASS_MASK,
(8 - value / 15) << TONECTL_BASS_SHIFT);
}
void audiohw_set_treble(int value)
{
treble = value;
handle_dsp_power();
if (value >= -105 && value <= 120)
cscodec_setbits(TONECTL, TONECTL_TREB_MASK,
(8 - value / 15) << TONECTL_TREB_SHIFT);
}
void audiohw_set_bass_cutoff(int value)
{
cscodec_setbits(BTCTL, BTCTL_BASSCF_MASK,
(value - 1) << BTCTL_BASSCF_SHIFT);
}
void audiohw_set_treble_cutoff(int value)
{
cscodec_setbits(BTCTL, BTCTL_TREBCF_MASK,
(value - 1) << BTCTL_TREBCF_SHIFT);
}
void audiohw_set_prescaler(int value)
{
cscodec_setbits(MSTAVOL, MSTAVOL_VOLUME_MASK,
(-value / 5) << MSTAVOL_VOLUME_SHIFT);
cscodec_setbits(MSTBVOL, MSTBVOL_VOLUME_MASK,
(-value / 5) << MSTBVOL_VOLUME_SHIFT);
}
/* Nice shutdown of CS42L55 codec */
void audiohw_close(void)
{
audiohw_mute(true);
cscodec_write(HPACTL, HPACTL_HPAMUTE);
cscodec_write(HPBCTL, HPBCTL_HPBMUTE);
cscodec_write(LINEACTL, LINEACTL_LINEAMUTE);
cscodec_write(LINEBCTL, LINEBCTL_LINEBMUTE);
cscodec_write(PWRCTL1, PWRCTL1_PDN_CHRG | PWRCTL1_PDN_ADCA
| PWRCTL1_PDN_ADCB | PWRCTL1_PDN_CODEC);
cscodec_reset(true);
cscodec_clock(false);
cscodec_power(false);
}
/* Note: Disable output before calling this function */
void audiohw_set_frequency(int fsel)
{
if (fsel == HW_FREQ_8) cscodec_write(CLKCTL2, CLKCTL2_8000HZ);
else if (fsel == HW_FREQ_11) cscodec_write(CLKCTL2, CLKCTL2_11025HZ);
else if (fsel == HW_FREQ_12) cscodec_write(CLKCTL2, CLKCTL2_12000HZ);
else if (fsel == HW_FREQ_16) cscodec_write(CLKCTL2, CLKCTL2_16000HZ);
else if (fsel == HW_FREQ_22) cscodec_write(CLKCTL2, CLKCTL2_22050HZ);
else if (fsel == HW_FREQ_24) cscodec_write(CLKCTL2, CLKCTL2_24000HZ);
else if (fsel == HW_FREQ_32) cscodec_write(CLKCTL2, CLKCTL2_32000HZ);
else if (fsel == HW_FREQ_44) cscodec_write(CLKCTL2, CLKCTL2_44100HZ);
else if (fsel == HW_FREQ_48) cscodec_write(CLKCTL2, CLKCTL2_48000HZ);
}
#ifdef HAVE_RECORDING
//TODO: Implement
#endif /* HAVE_RECORDING */

2
firmware/drivers/audio/dac3550a.c
View file

@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: dac.c 17847 2008-06-28 18:10:04Z bagder $
* $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*

116
firmware/export/ata-defines.h
View file

@ -1,58 +1,58 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $
*
* Copyright (C) 2011 by Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __ATA_DEFINES_H__
#define __ATA_DEFINES_H__
#ifndef ATA_OUT8
#define ATA_OUT8(reg, data) (reg) = (data)
#endif
#ifndef ATA_OUT16
#define ATA_OUT16(reg, data) (reg) = (data)
#endif
#ifndef ATA_IN8
#define ATA_IN8(reg) (reg)
#endif
#ifndef ATA_IN16
#define ATA_IN16(reg) (reg)
#endif
#ifndef ATA_SWAP_IDENTIFY
#define ATA_SWAP_IDENTIFY(word) (word)
#endif
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define STATUS_DF 0x20
#define ERROR_IDNF 0x10
#define ERROR_ABRT 0x04
#define TEST_PATTERN1 0xa5
#define TEST_PATTERN2 0x5a
#define TEST_PATTERN3 0xaa
#define TEST_PATTERN4 0x55
#define ATA_FEATURE ATA_ERROR
#define ATA_STATUS ATA_COMMAND
#define ATA_ALT_STATUS ATA_CONTROL
#endif
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: ata.h 28951 2011-01-02 23:02:55Z theseven $
*
* Copyright (C) 2011 by Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __ATA_DEFINES_H__
#define __ATA_DEFINES_H__
#ifndef ATA_OUT8
#define ATA_OUT8(reg, data) (reg) = (data)
#endif
#ifndef ATA_OUT16
#define ATA_OUT16(reg, data) (reg) = (data)
#endif
#ifndef ATA_IN8
#define ATA_IN8(reg) (reg)
#endif
#ifndef ATA_IN16
#define ATA_IN16(reg) (reg)
#endif
#ifndef ATA_SWAP_IDENTIFY
#define ATA_SWAP_IDENTIFY(word) (word)
#endif
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define STATUS_DF 0x20
#define ERROR_IDNF 0x10
#define ERROR_ABRT 0x04
#define TEST_PATTERN1 0xa5
#define TEST_PATTERN2 0x5a
#define TEST_PATTERN3 0xaa
#define TEST_PATTERN4 0x55
#define ATA_FEATURE ATA_ERROR
#define ATA_STATUS ATA_COMMAND
#define ATA_ALT_STATUS ATA_CONTROL
#endif

378
firmware/export/config/rk27generic.h
View file

@ -1,189 +1,189 @@
/*
* This config file is for Rockchip rk27xx reference design
*/
#define TARGET_TREE /* this target is using the target tree system */
/* For Rolo and boot loader */
#define MODEL_NUMBER 78
#define MODEL_NAME "Rockchip 27xx generic"
/* define this if you have recording possibility */
/* #define HAVE_RECORDING */
/* Define bitmask of input sources - recordable bitmask can be defined
explicitly if different */
/* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */
/* define the bitmask of hardware sample rates */
#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
| SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
| SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
/* define the bitmask of recording sample rates */
#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
| SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
| SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
/* define this if you have a bitmap LCD display */
#define HAVE_LCD_BITMAP
/* define this if you can flip your LCD */
/* #define HAVE_LCD_FLIP */
/* define this if you have a colour LCD */
#define HAVE_LCD_COLOR
/* define this if you want album art for this target */
#define HAVE_ALBUMART
/* define this to enable bitmap scaling */
#define HAVE_BMP_SCALING
/* define this to enable JPEG decoding */
#define HAVE_JPEG
/* define this if you can invert the colours on your LCD */
/* #define HAVE_LCD_INVERT */
/* define this if you have access to the quickscreen */
#define HAVE_QUICKSCREEN
/* define this if you have access to the pitchscreen */
#define HAVE_PITCHSCREEN
/* define this if you would like tagcache to build on this target */
#define HAVE_TAGCACHE
/* define this if you have a flash memory storage */
#define HAVE_FLASH_STORAGE
#define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND)
#define CONFIG_NAND NAND_RK27XX
#define HAVE_SW_TONE_CONTROLS
/* commented for now */
/* #define HAVE_HOTSWAP */
#define NUM_DRIVES 2
#define SECTOR_SIZE 512
/* for small(ish) SD cards */
#define HAVE_FAT16SUPPORT
/* LCD dimensions */
#define LCD_WIDTH 400
#define LCD_HEIGHT 240
#define LCD_DEPTH 16 /* pseudo 262.144 colors */
#define LCD_PIXELFORMAT RGB565 /* rgb565 */
/* Define this if the LCD can shut down */
/* #define HAVE_LCD_SHUTDOWN */
/* Define this if your LCD can be enabled/disabled */
/* #define HAVE_LCD_ENABLE */
/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
should be defined as well. */
#ifndef BOOTLOADER
/* TODO: #define HAVE_LCD_SLEEP */
/* TODO: #define HAVE_LCD_SLEEP_SETTING */
#endif
#define CONFIG_KEYPAD RK27XX_GENERIC_PAD
/* Define this to enable morse code input */
#define HAVE_MORSE_INPUT
/* Define this if you do software codec */
#define CONFIG_CODEC SWCODEC
/* define this if you have a real-time clock */
/* #define CONFIG_RTC RTC_NANO2G */
/* Define if the device can wake from an RTC alarm */
/* #define HAVE_RTC_ALARM */
#define CONFIG_LCD LCD_SPFD5420A
/* Define the type of audio codec */
#define HAVE_RK27XX_CODEC
/* #define HAVE_PCM_DMA_ADDRESS */
/* Define this for LCD backlight available */
#define HAVE_BACKLIGHT
#define HAVE_BACKLIGHT_BRIGHTNESS
#define MIN_BRIGHTNESS_SETTING 0
#define MAX_BRIGHTNESS_SETTING 31
#define DEFAULT_BRIGHTNESS_SETTING 20
#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG
/* Define this if you have a software controlled poweroff */
#define HAVE_SW_POWEROFF
/* The number of bytes reserved for loadable codecs */
#define CODEC_SIZE 0x100000
/* The number of bytes reserved for loadable plugins */
#define PLUGIN_BUFFER_SIZE 0x80000
/* TODO: Figure out real values */
#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
#define BATTERY_CAPACITY_INC 10 /* capacity increment */
#define BATTERY_TYPES_COUNT 1 /* only one type */
/* Hardware controlled charging with monitoring */
#define CONFIG_CHARGING CHARGING_MONITOR
/* define current usage levels */
/* TODO: #define CURRENT_NORMAL
* TODO: #define CURRENT_BACKLIGHT 23
*/
/* define this if the unit can be powered or charged via USB */
#define HAVE_USB_POWER
/* USB On-the-go */
#define CONFIG_USBOTG USBOTG_RK27XX
/* enable these for the experimental usb stack */
#define HAVE_USBSTACK
#define USE_ROCKBOX_USB
#define USB_VENDOR_ID 0x071b
#define USB_PRODUCT_ID 0x3202
#define HAVE_BOOTLOADER_USB_MODE
/* Define this if your LCD can set contrast */
/* #define HAVE_LCD_CONTRAST */
/* The exact type of CPU */
#define CONFIG_CPU RK27XX
/* I2C interface */
#define CONFIG_I2C I2C_RK27XX
/* Define this to the CPU frequency */
#define CPU_FREQ 200000000
/* define this if the hardware can be powered off while charging */
/* #define HAVE_POWEROFF_WHILE_CHARGING */
/* Offset ( in the firmware file's header ) to the file CRC */
#define FIRMWARE_OFFSET_FILE_CRC 0
/* Offset ( in the firmware file's header ) to the real data */
#define FIRMWARE_OFFSET_FILE_DATA 8
#define STORAGE_NEEDS_ALIGN
/* Define this if you have adjustable CPU frequency */
/* #define HAVE_ADJUSTABLE_CPU_FREQ */
#define BOOTFILE_EXT "rk27"
#define BOOTFILE "rockbox." BOOTFILE_EXT
#define BOOTDIR "/.rockbox"
/*
* This config file is for Rockchip rk27xx reference design
*/
#define TARGET_TREE /* this target is using the target tree system */
/* For Rolo and boot loader */
#define MODEL_NUMBER 78
#define MODEL_NAME "Rockchip 27xx generic"
/* define this if you have recording possibility */
/* #define HAVE_RECORDING */
/* Define bitmask of input sources - recordable bitmask can be defined
explicitly if different */
/* #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_FM) */
/* define the bitmask of hardware sample rates */
#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
| SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
| SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
/* define the bitmask of recording sample rates */
#define REC_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
| SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
| SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
/* define this if you have a bitmap LCD display */
#define HAVE_LCD_BITMAP
/* define this if you can flip your LCD */
/* #define HAVE_LCD_FLIP */
/* define this if you have a colour LCD */
#define HAVE_LCD_COLOR
/* define this if you want album art for this target */
#define HAVE_ALBUMART
/* define this to enable bitmap scaling */
#define HAVE_BMP_SCALING
/* define this to enable JPEG decoding */
#define HAVE_JPEG
/* define this if you can invert the colours on your LCD */
/* #define HAVE_LCD_INVERT */
/* define this if you have access to the quickscreen */
#define HAVE_QUICKSCREEN
/* define this if you have access to the pitchscreen */
#define HAVE_PITCHSCREEN
/* define this if you would like tagcache to build on this target */
#define HAVE_TAGCACHE
/* define this if you have a flash memory storage */
#define HAVE_FLASH_STORAGE
#define CONFIG_STORAGE (STORAGE_SD | STORAGE_NAND)
#define CONFIG_NAND NAND_RK27XX
#define HAVE_SW_TONE_CONTROLS
/* commented for now */
/* #define HAVE_HOTSWAP */
#define NUM_DRIVES 2
#define SECTOR_SIZE 512
/* for small(ish) SD cards */
#define HAVE_FAT16SUPPORT
/* LCD dimensions */
#define LCD_WIDTH 400
#define LCD_HEIGHT 240
#define LCD_DEPTH 16 /* pseudo 262.144 colors */
#define LCD_PIXELFORMAT RGB565 /* rgb565 */
/* Define this if the LCD can shut down */
/* #define HAVE_LCD_SHUTDOWN */
/* Define this if your LCD can be enabled/disabled */
/* #define HAVE_LCD_ENABLE */
/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
should be defined as well. */
#ifndef BOOTLOADER
/* TODO: #define HAVE_LCD_SLEEP */
/* TODO: #define HAVE_LCD_SLEEP_SETTING */
#endif
#define CONFIG_KEYPAD RK27XX_GENERIC_PAD
/* Define this to enable morse code input */
#define HAVE_MORSE_INPUT
/* Define this if you do software codec */
#define CONFIG_CODEC SWCODEC
/* define this if you have a real-time clock */
/* #define CONFIG_RTC RTC_NANO2G */
/* Define if the device can wake from an RTC alarm */
/* #define HAVE_RTC_ALARM */
#define CONFIG_LCD LCD_SPFD5420A
/* Define the type of audio codec */
#define HAVE_RK27XX_CODEC
/* #define HAVE_PCM_DMA_ADDRESS */
/* Define this for LCD backlight available */
#define HAVE_BACKLIGHT
#define HAVE_BACKLIGHT_BRIGHTNESS
#define MIN_BRIGHTNESS_SETTING 0
#define MAX_BRIGHTNESS_SETTING 31
#define DEFAULT_BRIGHTNESS_SETTING 20
#define CONFIG_BACKLIGHT_FADING BACKLIGHT_FADING_SW_HW_REG
/* Define this if you have a software controlled poweroff */
#define HAVE_SW_POWEROFF
/* The number of bytes reserved for loadable codecs */
#define CODEC_SIZE 0x100000
/* The number of bytes reserved for loadable plugins */
#define PLUGIN_BUFFER_SIZE 0x80000
/* TODO: Figure out real values */
#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
#define BATTERY_CAPACITY_MIN 300 /* min. capacity selectable */
#define BATTERY_CAPACITY_MAX 500 /* max. capacity selectable */
#define BATTERY_CAPACITY_INC 10 /* capacity increment */
#define BATTERY_TYPES_COUNT 1 /* only one type */
/* Hardware controlled charging with monitoring */
#define CONFIG_CHARGING CHARGING_MONITOR
/* define current usage levels */
/* TODO: #define CURRENT_NORMAL
* TODO: #define CURRENT_BACKLIGHT 23
*/
/* define this if the unit can be powered or charged via USB */
#define HAVE_USB_POWER
/* USB On-the-go */
#define CONFIG_USBOTG USBOTG_RK27XX
/* enable these for the experimental usb stack */
#define HAVE_USBSTACK
#define USE_ROCKBOX_USB
#define USB_VENDOR_ID 0x071b
#define USB_PRODUCT_ID 0x3202
#define HAVE_BOOTLOADER_USB_MODE
/* Define this if your LCD can set contrast */
/* #define HAVE_LCD_CONTRAST */
/* The exact type of CPU */
#define CONFIG_CPU RK27XX
/* I2C interface */
#define CONFIG_I2C I2C_RK27XX
/* Define this to the CPU frequency */
#define CPU_FREQ 200000000
/* define this if the hardware can be powered off while charging */
/* #define HAVE_POWEROFF_WHILE_CHARGING */
/* Offset ( in the firmware file's header ) to the file CRC */
#define FIRMWARE_OFFSET_FILE_CRC 0
/* Offset ( in the firmware file's header ) to the real data */
#define FIRMWARE_OFFSET_FILE_DATA 8
#define STORAGE_NEEDS_ALIGN
/* Define this if you have adjustable CPU frequency */
/* #define HAVE_ADJUSTABLE_CPU_FREQ */
#define BOOTFILE_EXT "rk27"
#define BOOTFILE "rockbox." BOOTFILE_EXT
#define BOOTDIR "/.rockbox"

2
firmware/export/dac3550a.h
View file

@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: dac.h 24158 2010-01-03 11:31:14Z Buschel $
* $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*

2
firmware/export/mascodec.h
View file

@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: mas.h 24154 2010-01-03 10:27:43Z Buschel $
* $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*

1660
firmware/export/s5l8702.h
View file

File diff suppressed because it is too large Load diff

2
firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
View file

@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: lcd-clipzip.c 30465 2011-09-06 16:55:52Z bertrik $
* $Id$
*
* Copyright (C) 2011 Bertrik Sikken
*

616
firmware/target/arm/s5l8700/postmortemstub.S
View file

@ -1,308 +1,308 @@
.section .text.post_mortem_stub, "ax", %progbits
.align 4
.global post_mortem_stub
.type post_mortem_stub, %function
post_mortem_stub:
MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs
MRC p15, 0, R0,c1,c0
BIC R0, R0, #5
MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache
MOV R13, #0
pms_flushcache_loop:
MCR p15, 0, R13,c7,c14,2
ADD R0, R13, #0x10
MCR p15, 0, R0,c7,c14,2
ADD R0, R0, #0x10
MCR p15, 0, R0,c7,c14,2
ADD R0, R0, #0x10
MCR p15, 0, R0,c7,c14,2
ADDS R13, R13, #0x04000000
BNE pms_flushcache_loop
MCR p15, 0, R13,c7,c10,4
LDR R7, pms_00080200
ORR R8, R7, #0x8000
ADR R9, pms_recvbuf
LDR R10, pms_20080040
MOV R11, #0x38800000
MOV R12, #1
MOV R2, #0x3C400000
ADD R1, R2, #0x00100000 @ Enable USB clocks
LDR R0, [R1,#0x28]
BIC R0, R0, #0x4000
STR R0, [R1,#0x28]
LDR R0, [R1,#0x40]
BIC R0, R0, #0x800
STR R0, [R1,#0x40]
LDR R0, pms_20803180 @ Clocking config
STR R0, [R1]
MOV R0, #0x280
STR R0, [R1,#0x3C]
MRC p15, 0, R0,c1,c0
ORR R0, R0, #0xc0000000
MCR p15, 0, R0,c1,c0 @ Asynchronous mode
STR R13, [R11,#0xE00] @ PHY clock enable
MOV R1, #0x800
ORR R0, R2, #2
STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect
STR R13, [R2] @ USB2 PHY: Power on
STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset
MOV R0, #0x10000
pms_wait:
SUBS R0, R0, #1
BNE pms_wait
STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset
STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz
STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset
pms_waitcorereset:
LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset
TST R0, #1
BNE pms_waitcorereset
TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE
BEQ pms_waitcorereset
MOV R0, #0x200
STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes
ORR R0, R0, #0x2000000
STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes
MOV R0, #0x26
STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts
MOV R0, #0x1400
ADD R0, R0, #8
STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5
STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect
ADR R14, pms_ctrlbuf
ORR R5, R8, #0x84000000
@ fallthrough
pms_mainloop:
LDR R3, [R11,#0x14] @ Global USB interrupts
TST R3, #0x00001000 @ BUS reset
BEQ pms_noreset
MOV R0, #0x500
STR R0, [R11,#0x804]
MOV R0, #4
STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage
MOV R0, #0x8000
STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE
STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet
STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf
ORR R6, R0, #0x84000000
STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK
STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets
STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets
STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet
STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf
ORR R4, R5, #0x10000000
STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0
pms_noreset:
LDR R0, [R11,#0x908] @ Just ACK all IN events...
STR R0, [R11,#0x908]
LDR R0, [R11,#0x968]
STR R0, [R11,#0x968]
LDR R2, [R11,#0xB08]
MOVS R2, R2 @ Event on OUT EP0
BEQ pms_noep0out
TST R2, #8 @ SETUP phase done
BEQ pms_controldone
LDRB R0, [R14,#1] @ Get request type
CMP R0, #0
BEQ pms_GET_STATUS
CMP R0, #1
BEQ pms_CLEAR_FEATURE
CMP R0, #3
BEQ pms_SET_FEATURE
CMP R0, #5
BEQ pms_SET_ADDRESS
CMP R0, #6
BEQ pms_GET_DESCRIPTOR
CMP R0, #8
BEQ pms_GET_CONFIGURATION
CMP R0, #9
BEQ pms_SET_CONFIGURATION
pms_ctrlstall:
LDR R0, [R11,#0x900]
ORR R0, R0, #0x00200000
STR R0, [R11,#0x900] @ Stall IN EP0
LDR R0, [R11,#0xB00]
ORR R0, R0, #0x00200000
STR R0, [R11,#0xB00] @ Stall OUT EP0
pms_controldone:
STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet
STR R14, [R11,#0xB14] @ OUT EP0: DMA address
STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK
pms_noep0out:
STR R2, [R11,#0xB08] @ ACK it, whatever it was...
LDR R2, [R11,#0xB88]
MOVS R2, R2 @ Event on OUT EP4
BEQ pms_noep1out
TST R2, #1 @ XFER complete
BEQ pms_datadone
LDR R0, pms_000001FF
LDR R1, pms_recvbuf+4
ADD R0, R0, R1
MOV R0, R0,LSR#9
ORR R1, R1, R0,LSL#19 @ Number of packets
LDR R0, pms_recvbuf
STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size
STR R0, [R11,#0x974] @ EP3 IN: DMA address
STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK
pms_datadone:
STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet
STR R9, [R11,#0xB94] @ Out EP4: DMA address
STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK
pms_noep1out:
STR R2, [R11,#0xB88] @ ACK it, whatever it was...
STR R3, [R11,#0x14] @ ACK global ints
B pms_mainloop
pms_CLEAR_FEATURE:
LDRB R0, [R14]
CMP R0, #2
LDREQ R0, [R14,#2]
BICEQ R0, R0, #0x00800000
CMPEQ R0, #0x00010000
@ fallthrough
pms_SET_CONFIGURATION:
ORREQ R0, R8, #0x10000000
STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID
STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID
B pms_SET_FEATURE @ zero-length ACK
pms_GET_CONFIGURATION:
MOV R1, #1
STR R1, [R14]
@ fallthrough
pms_ctrlsend:
ORR R0, R1, #0x00080000 @ 1 Packet
STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1
STR R14, [R11,#0x914] @ EP0 IN: DMA address
ORR R0, R6, #0x1800
STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK
ADR R14, pms_ctrlbuf
B pms_controldone
pms_GET_DESCRIPTOR:
LDRB R0, [R14,#3] @ Descriptor type
CMP R0, #1
ADREQ R14, pms_devicedescriptor
BEQ pms_senddescriptor
CMP R0, #2
ADREQ R14, pms_configurationdescriptor
MOVEQ R1, #0x20
BEQ pms_senddescriptorcustomsize
CMP R0, #3
BNE pms_ctrlstall
LDRB R0, [R14,#2] @ String descriptor index
CMP R0, #0
LDREQ R0, pms_langstringdescriptor
STREQ R0, [R14]
BEQ pms_senddescriptor
CMP R0, #1
CMPNE R0, #2
ADREQ R14, pms_devnamestringdescriptor
BNE pms_ctrlstall
@ fallthrough
pms_senddescriptor:
LDRB R1, [R14] @ Descriptor length
@ fallthrough
pms_senddescriptorcustomsize:
LDRH R0, pms_ctrlbuf+6 @ Requested length
CMP R0, R1
MOVLO R1, R0
B pms_ctrlsend
pms_SET_ADDRESS:
LDRH R1, [R14,#2] @ new address
LDR R0, [R11,#0x800]
BIC R0, R0, #0x000007F0
ORR R0, R0, R1,LSL#4
STR R0, [R11,#0x800] @ set new address
@ fallthrough
pms_SET_FEATURE:
MOV R1, #0 @ zero-length ACK
B pms_ctrlsend
pms_20803180:
.word 0x20803180
.ltorg
.align 4
pms_configurationdescriptor:
.word 0x00200209
.word 0xC0000101
.word 0x00040932
.word 0xFFFF0200
.word 0x050700FF
.word 0x02000204
.word 0x83050701
.word 0x01020002
pms_devicedescriptor:
.word 0x02000112
.word 0x40FFFFFF
.word 0xA112FFFF
.word 0x02010001
.word 0x00010100
pms_00080200:
.word 0x00080200
pms_20080040:
.word 0x20080040
pms_000001FF:
.word 0x000001FF
pms_devnamestringdescriptor:
.word 0x0052030C
.word 0x00500042
.word 0x0053004D
pms_langstringdescriptor:
.word 0x04090304
pms_ctrlbuf:
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
pms_recvbuf:
.word 0
.word 0
pms_GET_STATUS:
LDRB R0, [R14]
CMP R0, #0x80
STREQ R12, [R14]
STRNE R13, [R14]
MOV R1, #2
B pms_ctrlsend
.size post_mortem_stub, .-post_mortem_stub
.section .text.post_mortem_stub, "ax", %progbits
.align 4
.global post_mortem_stub
.type post_mortem_stub, %function
post_mortem_stub:
MSR CPSR_c, #0xD3 @ Supervisor mode, no IRQs, no FIQs
MRC p15, 0, R0,c1,c0
BIC R0, R0, #5
MCR p15, 0, R0,c1,c0 @ Disable the Protection Unit and DCache
MOV R13, #0
pms_flushcache_loop:
MCR p15, 0, R13,c7,c14,2
ADD R0, R13, #0x10
MCR p15, 0, R0,c7,c14,2
ADD R0, R0, #0x10
MCR p15, 0, R0,c7,c14,2
ADD R0, R0, #0x10
MCR p15, 0, R0,c7,c14,2
ADDS R13, R13, #0x04000000
BNE pms_flushcache_loop
MCR p15, 0, R13,c7,c10,4
LDR R7, pms_00080200
ORR R8, R7, #0x8000
ADR R9, pms_recvbuf
LDR R10, pms_20080040
MOV R11, #0x38800000
MOV R12, #1
MOV R2, #0x3C400000
ADD R1, R2, #0x00100000 @ Enable USB clocks
LDR R0, [R1,#0x28]
BIC R0, R0, #0x4000
STR R0, [R1,#0x28]
LDR R0, [R1,#0x40]
BIC R0, R0, #0x800
STR R0, [R1,#0x40]
LDR R0, pms_20803180 @ Clocking config
STR R0, [R1]
MOV R0, #0x280
STR R0, [R1,#0x3C]
MRC p15, 0, R0,c1,c0
ORR R0, R0, #0xc0000000
MCR p15, 0, R0,c1,c0 @ Asynchronous mode
STR R13, [R11,#0xE00] @ PHY clock enable
MOV R1, #0x800
ORR R0, R2, #2
STR R0, [R11,#0x804] @ USB2 Gadget: Soft disconnect
STR R13, [R2] @ USB2 PHY: Power on
STR R12, [R2,#0x08] @ USB2 PHY: Assert Software Reset
MOV R0, #0x10000
pms_wait:
SUBS R0, R0, #1
BNE pms_wait
STR R13, [R2,#0x08] @ USB2 PHY: Deassert Software Reset
STR R13, [R2,#0x04] @ USB2 PHY: Clock is 48MHz
STR R12, [R11,#0x10] @ USB2 Gadget: Assert Core Software Reset
pms_waitcorereset:
LDR R0, [R11,#0x10] @ USB2 Gadget: Wait for Core to reset
TST R0, #1
BNE pms_waitcorereset
TST R0, #0x80000000 @ USB2 Gadget: Wait for AHB IDLE
BEQ pms_waitcorereset
MOV R0, #0x200
STR R0, [R11,#0x24] @ USB2 Gadget: RX FIFO size: 512 bytes
ORR R0, R0, #0x2000000
STR R0, [R11,#0x28] @ USB2 Gadget: Non-periodic TX FIFO size: 512 bytes
MOV R0, #0x26
STR R0, [R11,#0x08] @ USB2 Gadget: DMA Enable, Burst Length: 4, Mask Interrupts
MOV R0, #0x1400
ADD R0, R0, #8
STR R0, [R11,#0x0C] @ USB2 Gadget: PHY IF is 16bit, Turnaround 5
STR R1, [R11,#0x804] @ USB2 Gadget: Soft reconnect
ADR R14, pms_ctrlbuf
ORR R5, R8, #0x84000000
@ fallthrough
pms_mainloop:
LDR R3, [R11,#0x14] @ Global USB interrupts
TST R3, #0x00001000 @ BUS reset
BEQ pms_noreset
MOV R0, #0x500
STR R0, [R11,#0x804]
MOV R0, #4
STR R0, [R11,#0x800] @ USB2 Gadget: Device Address 0, STALL on non-zero length status stage
MOV R0, #0x8000
STR R0, [R11,#0x900] @ USB2 Gadget: Endpoint 0 IN Control: ACTIVE
STR R10, [R11,#0xB10] @ USB2 Gadget: Endpoint 0 OUT Transfer Size: 64 Bytes, 1 Packet, 1 Setup Packet
STR R14, [R11,#0xB14] @ USB2 Gadget: Endpoint 0 OUT DMA Address: pms_ctrlbuf
ORR R6, R0, #0x84000000
STR R6, [R11,#0xB00] @ USB2 Gadget: Endpoint 0 OUT Control: ENABLE CLEARNAK
STR R8, [R11,#0x960] @ USB2 Gadget: Endpoint 3 IN Control: ACTIVE BULK, 512 byte packets
STR R8, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ACTIVE BULK, 512 byte packets
STR R7, [R11,#0xB90] @ USB2 Gadget: Endpoint 4 OUT Transfer Size: 512 Bytes, 1 Packet
STR R9, [R11,#0xB94] @ USB2 Gadget: Endpoint 4 OUT DMA Address: pms_recvbuf
ORR R4, R5, #0x10000000
STR R4, [R11,#0xB80] @ USB2 Gadget: Endpoint 4 OUT Control: ENABLE CLEARNAK DATA0
pms_noreset:
LDR R0, [R11,#0x908] @ Just ACK all IN events...
STR R0, [R11,#0x908]
LDR R0, [R11,#0x968]
STR R0, [R11,#0x968]
LDR R2, [R11,#0xB08]
MOVS R2, R2 @ Event on OUT EP0
BEQ pms_noep0out
TST R2, #8 @ SETUP phase done
BEQ pms_controldone
LDRB R0, [R14,#1] @ Get request type
CMP R0, #0
BEQ pms_GET_STATUS
CMP R0, #1
BEQ pms_CLEAR_FEATURE
CMP R0, #3
BEQ pms_SET_FEATURE
CMP R0, #5
BEQ pms_SET_ADDRESS
CMP R0, #6
BEQ pms_GET_DESCRIPTOR
CMP R0, #8
BEQ pms_GET_CONFIGURATION
CMP R0, #9
BEQ pms_SET_CONFIGURATION
pms_ctrlstall:
LDR R0, [R11,#0x900]
ORR R0, R0, #0x00200000
STR R0, [R11,#0x900] @ Stall IN EP0
LDR R0, [R11,#0xB00]
ORR R0, R0, #0x00200000
STR R0, [R11,#0xB00] @ Stall OUT EP0
pms_controldone:
STR R10, [R11,#0xB10] @ OUT EP0: 64 Bytes, 1 Packet, 1 Setup Packet
STR R14, [R11,#0xB14] @ OUT EP0: DMA address
STR R6, [R11,#0xB00] @ OUT EP0: Enable ClearNAK
pms_noep0out:
STR R2, [R11,#0xB08] @ ACK it, whatever it was...
LDR R2, [R11,#0xB88]
MOVS R2, R2 @ Event on OUT EP4
BEQ pms_noep1out
TST R2, #1 @ XFER complete
BEQ pms_datadone
LDR R0, pms_000001FF
LDR R1, pms_recvbuf+4
ADD R0, R0, R1
MOV R0, R0,LSR#9
ORR R1, R1, R0,LSL#19 @ Number of packets
LDR R0, pms_recvbuf
STR R1, [R11,#0x970] @ EP3 IN: Number of packets, size
STR R0, [R11,#0x974] @ EP3 IN: DMA address
STR R5, [R11,#0x960] @ EP3 IN: Enable ClearNAK
pms_datadone:
STR R7, [R11,#0xB90] @ OUT EP4: 512 Bytes, 1 Packet
STR R9, [R11,#0xB94] @ Out EP4: DMA address
STR R5, [R11,#0xB80] @ Out EP4: Enable ClearNAK
pms_noep1out:
STR R2, [R11,#0xB88] @ ACK it, whatever it was...
STR R3, [R11,#0x14] @ ACK global ints
B pms_mainloop
pms_CLEAR_FEATURE:
LDRB R0, [R14]
CMP R0, #2
LDREQ R0, [R14,#2]
BICEQ R0, R0, #0x00800000
CMPEQ R0, #0x00010000
@ fallthrough
pms_SET_CONFIGURATION:
ORREQ R0, R8, #0x10000000
STREQ R0, [R11,#0x960] @ EP3 IN: Set DATA0 PID
STREQ R4, [R11,#0xB80] @ EP4 OUT: Set DATA0 PID
B pms_SET_FEATURE @ zero-length ACK
pms_GET_CONFIGURATION:
MOV R1, #1
STR R1, [R14]
@ fallthrough
pms_ctrlsend:
ORR R0, R1, #0x00080000 @ 1 Packet
STR R0, [R11,#0x910] @ EP0 IN: 1 Packet, Size as in R1
STR R14, [R11,#0x914] @ EP0 IN: DMA address
ORR R0, R6, #0x1800
STR R0, [R11,#0x900] @ EP0 IN: Enable ClearNAK
ADR R14, pms_ctrlbuf
B pms_controldone
pms_GET_DESCRIPTOR:
LDRB R0, [R14,#3] @ Descriptor type
CMP R0, #1
ADREQ R14, pms_devicedescriptor
BEQ pms_senddescriptor
CMP R0, #2
ADREQ R14, pms_configurationdescriptor
MOVEQ R1, #0x20
BEQ pms_senddescriptorcustomsize
CMP R0, #3
BNE pms_ctrlstall
LDRB R0, [R14,#2] @ String descriptor index
CMP R0, #0
LDREQ R0, pms_langstringdescriptor
STREQ R0, [R14]
BEQ pms_senddescriptor
CMP R0, #1
CMPNE R0, #2
ADREQ R14, pms_devnamestringdescriptor
BNE pms_ctrlstall
@ fallthrough
pms_senddescriptor:
LDRB R1, [R14] @ Descriptor length
@ fallthrough
pms_senddescriptorcustomsize:
LDRH R0, pms_ctrlbuf+6 @ Requested length
CMP R0, R1
MOVLO R1, R0
B pms_ctrlsend
pms_SET_ADDRESS:
LDRH R1, [R14,#2] @ new address
LDR R0, [R11,#0x800]
BIC R0, R0, #0x000007F0
ORR R0, R0, R1,LSL#4
STR R0, [R11,#0x800] @ set new address
@ fallthrough
pms_SET_FEATURE:
MOV R1, #0 @ zero-length ACK
B pms_ctrlsend
pms_20803180:
.word 0x20803180
.ltorg
.align 4
pms_configurationdescriptor:
.word 0x00200209
.word 0xC0000101
.word 0x00040932
.word 0xFFFF0200
.word 0x050700FF
.word 0x02000204
.word 0x83050701
.word 0x01020002
pms_devicedescriptor:
.word 0x02000112
.word 0x40FFFFFF
.word 0xA112FFFF
.word 0x02010001
.word 0x00010100
pms_00080200:
.word 0x00080200
pms_20080040:
.word 0x20080040
pms_000001FF:
.word 0x000001FF
pms_devnamestringdescriptor:
.word 0x0052030C
.word 0x00500042
.word 0x0053004D
pms_langstringdescriptor:
.word 0x04090304
pms_ctrlbuf:
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
pms_recvbuf:
.word 0
.word 0
pms_GET_STATUS:
LDRB R0, [R14]
CMP R0, #0x80
STREQ R12, [R14]
STRNE R13, [R14]
MOV R1, #2
B pms_ctrlsend
.size post_mortem_stub, .-post_mortem_stub

332
firmware/target/arm/s5l8702/debug-s5l8702.c
View file

@ -1,166 +1,166 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $
*
* Copyright © 2008 Rafaël Carré
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include <stdbool.h>
#include "config.h"
#include "kernel.h"
#include "debug-target.h"
#include "button.h"
#include "lcd.h"
#include "font.h"
#include "storage.h"
#include "power.h"
#include "pmu-target.h"
#include "pcm-target.h"
/* Skeleton for adding target specific debug info to the debug menu
*/
#define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs);
extern int lcd_type;
bool dbg_hw_info(void)
{
int line;
int i;
unsigned int state = 0;
const unsigned int max_states=3;
lcd_clear_display();
lcd_setfont(FONT_SYSFIXED);
state=0;
while(1)
{
lcd_clear_display();
line = 0;
if(state == 0)
{
_DEBUG_PRINTF("CPU:");
_DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick);
line++;
_DEBUG_PRINTF("LCD type: %d", lcd_type);
line++;
}
else if(state==1)
{
_DEBUG_PRINTF("PMU:");
for(i=0;i<7;i++)
{
char *device[] = {"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)"};
_DEBUG_PRINTF("ldo%d %s: %dmV %s",i,
pmu_read(0x2e + (i << 1))?" on":"off",
900 + pmu_read(0x2d + (i << 1))*100,
device[i]);
}
_DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25);
_DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25);
line++;
_DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false");
_DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
_DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
}
else if(state==2)
{
_DEBUG_PRINTF("Audio DMA:");
_DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
for(i = 0; i < PCM_LLICOUNT; i++)
_DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
_DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
}
else
{
state=0;
}
lcd_update();
switch(button_get_w_tmo(HZ/20))
{
case BUTTON_SCROLL_BACK:
if(state!=0) state--;
break;
case BUTTON_SCROLL_FWD:
if(state!=max_states-1)
{
state++;
}
break;
case DEBUG_CANCEL:
case BUTTON_REL:
lcd_setfont(FONT_UI);
return false;
}
}
lcd_setfont(FONT_UI);
return false;
}
bool dbg_ports(void)
{
int line;
lcd_setfont(FONT_SYSFIXED);
while(1)
{
lcd_clear_display();
line = 0;
_DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0));
_DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1));
_DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2));
_DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3));
_DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4));
_DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5));
_DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6));
_DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7));
_DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8));
_DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9));
_DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10));
_DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11));
_DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12));
_DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13));
_DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14));
_DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15));
_DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER);
lcd_update();
if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
break;
}
lcd_setfont(FONT_UI);
return false;
}
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: debug-s5l8700.c 28719 2010-12-01 18:35:01Z Buschel $
*
* Copyright © 2008 Rafaël Carré
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include <stdbool.h>
#include "config.h"
#include "kernel.h"
#include "debug-target.h"
#include "button.h"
#include "lcd.h"
#include "font.h"
#include "storage.h"
#include "power.h"
#include "pmu-target.h"
#include "pcm-target.h"
/* Skeleton for adding target specific debug info to the debug menu
*/
#define _DEBUG_PRINTF(a, varargs...) lcd_putsf(0, line++, (a), ##varargs);
extern int lcd_type;
bool dbg_hw_info(void)
{
int line;
int i;
unsigned int state = 0;
const unsigned int max_states=3;
lcd_clear_display();
lcd_setfont(FONT_SYSFIXED);
state=0;
while(1)
{
lcd_clear_display();
line = 0;
if(state == 0)
{
_DEBUG_PRINTF("CPU:");
_DEBUG_PRINTF("current_tick: %d", (unsigned int)current_tick);
line++;
_DEBUG_PRINTF("LCD type: %d", lcd_type);
line++;
}
else if(state==1)
{
_DEBUG_PRINTF("PMU:");
for(i=0;i<7;i++)
{
char *device[] = {"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)",
"(unknown)"};
_DEBUG_PRINTF("ldo%d %s: %dmV %s",i,
pmu_read(0x2e + (i << 1))?" on":"off",
900 + pmu_read(0x2d + (i << 1))*100,
device[i]);
}
_DEBUG_PRINTF("cpu voltage: %dmV",625 + pmu_read(0x1e)*25);
_DEBUG_PRINTF("memory voltage: %dmV",625 + pmu_read(0x22)*25);
line++;
_DEBUG_PRINTF("charging: %s", charging_state() ? "true" : "false");
_DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
_DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
}
else if(state==2)
{
_DEBUG_PRINTF("Audio DMA:");
_DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
for(i = 0; i < PCM_LLICOUNT; i++)
_DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
_DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
}
else
{
state=0;
}
lcd_update();
switch(button_get_w_tmo(HZ/20))
{
case BUTTON_SCROLL_BACK:
if(state!=0) state--;
break;
case BUTTON_SCROLL_FWD:
if(state!=max_states-1)
{
state++;
}
break;
case DEBUG_CANCEL:
case BUTTON_REL:
lcd_setfont(FONT_UI);
return false;
}
}
lcd_setfont(FONT_UI);
return false;
}
bool dbg_ports(void)
{
int line;
lcd_setfont(FONT_SYSFIXED);
while(1)
{
lcd_clear_display();
line = 0;
_DEBUG_PRINTF("GPIO 0: %08x",(unsigned int)PDAT(0));
_DEBUG_PRINTF("GPIO 1: %08x",(unsigned int)PDAT(1));
_DEBUG_PRINTF("GPIO 2: %08x",(unsigned int)PDAT(2));
_DEBUG_PRINTF("GPIO 3: %08x",(unsigned int)PDAT(3));
_DEBUG_PRINTF("GPIO 4: %08x",(unsigned int)PDAT(4));
_DEBUG_PRINTF("GPIO 5: %08x",(unsigned int)PDAT(5));
_DEBUG_PRINTF("GPIO 6: %08x",(unsigned int)PDAT(6));
_DEBUG_PRINTF("GPIO 7: %08x",(unsigned int)PDAT(7));
_DEBUG_PRINTF("GPIO 8: %08x",(unsigned int)PDAT(8));
_DEBUG_PRINTF("GPIO 9: %08x",(unsigned int)PDAT(9));
_DEBUG_PRINTF("GPIO 10: %08x",(unsigned int)PDAT(10));
_DEBUG_PRINTF("GPIO 11: %08x",(unsigned int)PDAT(11));
_DEBUG_PRINTF("GPIO 12: %08x",(unsigned int)PDAT(12));
_DEBUG_PRINTF("GPIO 13: %08x",(unsigned int)PDAT(13));
_DEBUG_PRINTF("GPIO 14: %08x",(unsigned int)PDAT(14));
_DEBUG_PRINTF("GPIO 15: %08x",(unsigned int)PDAT(15));
_DEBUG_PRINTF("USEC : %08x",(unsigned int)USEC_TIMER);
lcd_update();
if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
break;
}
lcd_setfont(FONT_UI);
return false;
}

66
firmware/target/arm/s5l8702/debug-target.h
View file

@ -1,33 +1,33 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $
*
* Copyright (C) 2007 by Karl Kurbjun
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef _DEBUG_TARGET_H_
#define _DEBUG_TARGET_H_
#include <stdbool.h>
#define DEBUG_CANCEL BUTTON_MENU
bool dbg_hw_info(void);
bool dbg_ports(void);
#endif /* _DEBUG_TARGET_H_ */
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: debug-target.h 28522 2010-11-06 14:24:25Z wodz $
*
* Copyright (C) 2007 by Karl Kurbjun
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef _DEBUG_TARGET_H_
#define _DEBUG_TARGET_H_
#include <stdbool.h>
#define DEBUG_CANCEL BUTTON_MENU
bool dbg_hw_info(void);
bool dbg_ports(void);
#endif /* _DEBUG_TARGET_H_ */

392
firmware/target/arm/s5l8702/i2c-s5l8702.c
View file

@ -1,196 +1,196 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
*
* Copyright (C) 2009 by Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "kernel.h"
#include "i2c-s5l8702.h"
/* Driver for the s5l8700 built-in I2C controller in master mode
Both the i2c_read and i2c_write function take the following arguments:
* slave, the address of the i2c slave device to read from / write to
* address, optional sub-address in the i2c slave (unused if -1)
* len, number of bytes to be transfered
* data, pointer to data to be transfered
A return value < 0 indicates an error.
Note:
* blocks the calling thread for the entire duraton of the i2c transfer but
uses wakeup_wait/wakeup_signal to allow other threads to run.
* ACK from slave is not checked, so functions never return an error
*/
static struct mutex i2c_mtx[2];
static void i2c_on(int bus)
{
/* enable I2C clock */
PWRCON(1) &= ~(1 << 4);
IICCON(bus) = (1 << 7) | /* ACK_GEN */
(0 << 6) | /* CLKSEL = PCLK/16 */
(1 << 5) | /* INT_EN */
(1 << 4) | /* IRQ clear */
(7 << 0); /* CK_REG */
/* serial output on */
IICSTAT(bus) = (1 << 4);
}
static void i2c_off(int bus)
{
/* serial output off */
IICSTAT(bus) = 0;
/* disable I2C clock */
PWRCON(1) |= (1 << 4);
}
void i2c_init()
{
mutex_init(&i2c_mtx[0]);
mutex_init(&i2c_mtx[1]);
}
int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
{
mutex_lock(&i2c_mtx[bus]);
i2c_on(bus);
long timeout = current_tick + HZ / 50;
/* START */
IICDS(bus) = slave & ~1;
IICSTAT(bus) = 0xF0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 1;
}
if (address >= 0) {
/* write address */
IICDS(bus) = address;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 2;
}
}
/* write data */
while (len--) {
IICDS(bus) = *data++;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 4;
}
}
/* STOP */
IICSTAT(bus) = 0xD0;
IICCON(bus) = 0xB3;
while ((IICSTAT(bus) & (1 << 5)) != 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 5;
}
i2c_off(bus);
mutex_unlock(&i2c_mtx[bus]);
return 0;
}
int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
{
mutex_lock(&i2c_mtx[bus]);
i2c_on(bus);
long timeout = current_tick + HZ / 50;
if (address >= 0) {
/* START */
IICDS(bus) = slave & ~1;
IICSTAT(bus) = 0xF0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 1;
}
/* write address */
IICDS(bus) = address;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 2;
}
}
/* (repeated) START */
IICDS(bus) = slave | 1;
IICSTAT(bus) = 0xB0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 3;
}
while (len--) {
IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 4;
}
*data++ = IICDS(bus);
}
/* STOP */
IICSTAT(bus) = 0x90;
IICCON(bus) = 0xB3;
while ((IICSTAT(bus) & (1 << 5)) != 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 5;
}
i2c_off(bus);
mutex_unlock(&i2c_mtx[bus]);
return 0;
}
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
*
* Copyright (C) 2009 by Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "kernel.h"
#include "i2c-s5l8702.h"
/* Driver for the s5l8700 built-in I2C controller in master mode
Both the i2c_read and i2c_write function take the following arguments:
* slave, the address of the i2c slave device to read from / write to
* address, optional sub-address in the i2c slave (unused if -1)
* len, number of bytes to be transfered
* data, pointer to data to be transfered
A return value < 0 indicates an error.
Note:
* blocks the calling thread for the entire duraton of the i2c transfer but
uses wakeup_wait/wakeup_signal to allow other threads to run.
* ACK from slave is not checked, so functions never return an error
*/
static struct mutex i2c_mtx[2];
static void i2c_on(int bus)
{
/* enable I2C clock */
PWRCON(1) &= ~(1 << 4);
IICCON(bus) = (1 << 7) | /* ACK_GEN */
(0 << 6) | /* CLKSEL = PCLK/16 */
(1 << 5) | /* INT_EN */
(1 << 4) | /* IRQ clear */
(7 << 0); /* CK_REG */
/* serial output on */
IICSTAT(bus) = (1 << 4);
}
static void i2c_off(int bus)
{
/* serial output off */
IICSTAT(bus) = 0;
/* disable I2C clock */
PWRCON(1) |= (1 << 4);
}
void i2c_init()
{
mutex_init(&i2c_mtx[0]);
mutex_init(&i2c_mtx[1]);
}
int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
{
mutex_lock(&i2c_mtx[bus]);
i2c_on(bus);
long timeout = current_tick + HZ / 50;
/* START */
IICDS(bus) = slave & ~1;
IICSTAT(bus) = 0xF0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 1;
}
if (address >= 0) {
/* write address */
IICDS(bus) = address;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 2;
}
}
/* write data */
while (len--) {
IICDS(bus) = *data++;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 4;
}
}
/* STOP */
IICSTAT(bus) = 0xD0;
IICCON(bus) = 0xB3;
while ((IICSTAT(bus) & (1 << 5)) != 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 5;
}
i2c_off(bus);
mutex_unlock(&i2c_mtx[bus]);
return 0;
}
int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
{
mutex_lock(&i2c_mtx[bus]);
i2c_on(bus);
long timeout = current_tick + HZ / 50;
if (address >= 0) {
/* START */
IICDS(bus) = slave & ~1;
IICSTAT(bus) = 0xF0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 1;
}
/* write address */
IICDS(bus) = address;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 2;
}
}
/* (repeated) START */
IICDS(bus) = slave | 1;
IICSTAT(bus) = 0xB0;
IICCON(bus) = 0xB3;
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 3;
}
while (len--) {
IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
while ((IICCON(bus) & 0x10) == 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 4;
}
*data++ = IICDS(bus);
}
/* STOP */
IICSTAT(bus) = 0x90;
IICCON(bus) = 0xB3;
while ((IICSTAT(bus) & (1 << 5)) != 0)
if (TIME_AFTER(current_tick, timeout))
{
mutex_unlock(&i2c_mtx[bus]);
return 5;
}
i2c_off(bus);
mutex_unlock(&i2c_mtx[bus]);
return 0;
}

112
firmware/target/arm/s5l8702/kernel-s5l8702.c
View file

@ -1,56 +1,56 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $
*
* Copyright © 2009 Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "kernel.h"
/* S5L8702 driver for the kernel timer
Timer B is configured as a 10 kHz timer
*/
void INT_TIMERB(void)
{
/* clear interrupt */
TBCON = TBCON;
call_tick_tasks(); /* Run through the list of tick tasks */
}
void tick_start(unsigned int interval_in_ms)
{
int cycles = 10 * interval_in_ms;
/* configure timer for 10 kHz */
TBCMD = (1 << 1); /* TB_CLR */
TBPRE = 337 - 1; /* prescaler */
TBCON = (0 << 13) | /* TB_INT1_EN */
(1 << 12) | /* TB_INT0_EN */
(0 << 11) | /* TB_START */
(2 << 8) | /* TB_CS = PCLK / 16 */
(0 << 4); /* TB_MODE_SEL = interval mode */
TBDATA0 = cycles; /* set interval period */
TBCMD = (1 << 0); /* TB_EN */
/* enable timer interrupt */
VIC0INTENABLE = 1 << IRQ_TIMER;
}
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: kernel-s5l8700.c 28795 2010-12-11 17:52:52Z Buschel $
*
* Copyright © 2009 Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "kernel.h"
/* S5L8702 driver for the kernel timer
Timer B is configured as a 10 kHz timer
*/
void INT_TIMERB(void)
{
/* clear interrupt */
TBCON = TBCON;
call_tick_tasks(); /* Run through the list of tick tasks */
}
void tick_start(unsigned int interval_in_ms)
{
int cycles = 10 * interval_in_ms;
/* configure timer for 10 kHz */
TBCMD = (1 << 1); /* TB_CLR */
TBPRE = 337 - 1; /* prescaler */
TBCON = (0 << 13) | /* TB_INT1_EN */
(1 << 12) | /* TB_INT0_EN */
(0 << 11) | /* TB_START */
(2 << 8) | /* TB_CS = PCLK / 16 */
(0 << 4); /* TB_MODE_SEL = interval mode */
TBDATA0 = cycles; /* set interval period */
TBCMD = (1 << 0); /* TB_EN */
/* enable timer interrupt */
VIC0INTENABLE = 1 << IRQ_TIMER;
}

456
firmware/target/arm/s5l8702/pcm-s5l8702.c
View file

@ -1,228 +1,228 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $
*
* Copyright © 2011 Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include <string.h>
#include "config.h"
#include "system.h"
#include "audio.h"
#include "s5l8702.h"
#include "panic.h"
#include "audiohw.h"
#include "pcm.h"
#include "pcm-internal.h"
#include "pcm_sampr.h"
#include "mmu-arm.h"
#include "pcm-target.h"
static volatile int locked = 0;
static const int zerosample = 0;
static unsigned char dblbuf[2][PCM_WATERMARK * 4];
static int active_dblbuf;
struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
static struct dma_lli* lastlli;
static const unsigned char* dataptr;
size_t pcm_remaining;
size_t pcm_chunksize;
/* Mask the DMA interrupt */
void pcm_play_lock(void)
{
if (locked++ == 0) {
//TODO: Urgh, I don't like that at all...
VIC0INTENCLEAR = 1 << IRQ_DMAC0;
}
}
/* Unmask the DMA interrupt if enabled */
void pcm_play_unlock(void)
{
if (--locked == 0) {
VIC0INTENABLE = 1 << IRQ_DMAC0;
}
}
void INT_DMAC0C0(void) ICODE_ATTR;
void INT_DMAC0C0(void)
{
DMAC0INTTCCLR = 1;
if (!pcm_remaining)
{
pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining);
pcm_chunksize = pcm_remaining;
}
if (!pcm_remaining)
{
pcm_lli->nextlli = NULL;
pcm_lli->control = 0x75249000;
clean_dcache();
return;
}
uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
pcm_remaining -= lastsize;
if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
else lastlli = pcm_lli;
uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
chunksize = pcm_remaining - PCM_WATERMARK * 8;
pcm_remaining -= chunksize;
bool last = !chunksize;
int i = 0;
while (chunksize)
{
uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
chunksize -= thislli;
pcm_lli[i].srcaddr = (void*)dataptr;
pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2);
dataptr += thislli;
i++;
}
if (!pcm_remaining)
{
memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
lastlli->srcaddr = dblbuf[active_dblbuf];
active_dblbuf ^= 1;
}
else lastlli->srcaddr = dataptr;
lastlli->dstaddr = (void*)((int)&I2STXDB0);
lastlli->nextlli = last ? NULL : pcm_lli;
lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2);
dataptr += lastsize;
clean_dcache();
if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
{
DMAC0C0LLI = pcm_lli[0];
DMAC0C0CONFIG = 0x8a81;
}
else DMAC0C0NEXTLLI = pcm_lli;
pcm_play_dma_started_callback();
}
void pcm_play_dma_start(const void* addr, size_t size)
{
dataptr = (const unsigned char*)addr;
pcm_remaining = size;
I2STXCOM = 0xe;
DMAC0CONFIG |= 4;
INT_DMAC0C0();
}
void pcm_play_dma_stop(void)
{
DMAC0C0CONFIG = 0x8a80;
I2STXCOM = 0xa;
}
/* pause playback by disabling LRCK */
void pcm_play_dma_pause(bool pause)
{
if (pause) I2STXCOM |= 1;
else I2STXCOM &= ~1;
}
void pcm_play_dma_init(void)
{
PWRCON(0) &= ~(1 << 4);
PWRCON(1) &= ~(1 << 7);
I2S40 = 0x110;
I2STXCON = 0xb100059;
I2SCLKCON = 1;
VIC0INTENABLE = 1 << IRQ_DMAC0;
audiohw_preinit();
}
void pcm_play_dma_postinit(void)
{
audiohw_postinit();
}
void pcm_dma_apply_settings(void)
{
}
size_t pcm_get_bytes_waiting(void)
{
int bytes = pcm_remaining;
const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
while (lli)
{
bytes += (lli->control & 0xfff) * 2;
if (lli == lastlli) break;
lli = lli->nextlli;
}
return bytes;
}
const void* pcm_play_dma_get_peak_buffer(int *count)
{
*count = (DMAC0C0LLI.control & 0xfff) * 2;
return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
}
#ifdef HAVE_PCM_DMA_ADDRESS
void * pcm_dma_addr(void *addr)
{
return addr;
}
#endif
/****************************************************************************
** Recording DMA transfer
**/
#ifdef HAVE_RECORDING
void pcm_rec_lock(void)
{
}
void pcm_rec_unlock(void)
{
}
void pcm_rec_dma_stop(void)
{
}
void pcm_rec_dma_start(void *addr, size_t size)
{
(void)addr;
(void)size;
}
void pcm_rec_dma_close(void)
{
}
void pcm_rec_dma_init(void)
{
}
const void * pcm_rec_dma_get_peak_buffer(void)
{
return NULL;
}
#endif /* HAVE_RECORDING */
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: pcm-s5l8700.c 28600 2010-11-14 19:49:20Z Buschel $
*
* Copyright © 2011 Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include <string.h>
#include "config.h"
#include "system.h"
#include "audio.h"
#include "s5l8702.h"
#include "panic.h"
#include "audiohw.h"
#include "pcm.h"
#include "pcm-internal.h"
#include "pcm_sampr.h"
#include "mmu-arm.h"
#include "pcm-target.h"
static volatile int locked = 0;
static const int zerosample = 0;
static unsigned char dblbuf[2][PCM_WATERMARK * 4];
static int active_dblbuf;
struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
static struct dma_lli* lastlli;
static const unsigned char* dataptr;
size_t pcm_remaining;
size_t pcm_chunksize;
/* Mask the DMA interrupt */
void pcm_play_lock(void)
{
if (locked++ == 0) {
//TODO: Urgh, I don't like that at all...
VIC0INTENCLEAR = 1 << IRQ_DMAC0;
}
}
/* Unmask the DMA interrupt if enabled */
void pcm_play_unlock(void)
{
if (--locked == 0) {
VIC0INTENABLE = 1 << IRQ_DMAC0;
}
}
void INT_DMAC0C0(void) ICODE_ATTR;
void INT_DMAC0C0(void)
{
DMAC0INTTCCLR = 1;
if (!pcm_remaining)
{
pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining);
pcm_chunksize = pcm_remaining;
}
if (!pcm_remaining)
{
pcm_lli->nextlli = NULL;
pcm_lli->control = 0x75249000;
clean_dcache();
return;
}
uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
pcm_remaining -= lastsize;
if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
else lastlli = pcm_lli;
uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
chunksize = pcm_remaining - PCM_WATERMARK * 8;
pcm_remaining -= chunksize;
bool last = !chunksize;
int i = 0;
while (chunksize)
{
uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
chunksize -= thislli;
pcm_lli[i].srcaddr = (void*)dataptr;
pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
pcm_lli[i].control = (chunksize ? 0x75249000 : 0xf5249000) | (thislli / 2);
dataptr += thislli;
i++;
}
if (!pcm_remaining)
{
memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
lastlli->srcaddr = dblbuf[active_dblbuf];
active_dblbuf ^= 1;
}
else lastlli->srcaddr = dataptr;
lastlli->dstaddr = (void*)((int)&I2STXDB0);
lastlli->nextlli = last ? NULL : pcm_lli;
lastlli->control = (last ? 0xf5249000 : 0x75249000) | (lastsize / 2);
dataptr += lastsize;
clean_dcache();
if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
{
DMAC0C0LLI = pcm_lli[0];
DMAC0C0CONFIG = 0x8a81;
}
else DMAC0C0NEXTLLI = pcm_lli;
pcm_play_dma_started_callback();
}
void pcm_play_dma_start(const void* addr, size_t size)
{
dataptr = (const unsigned char*)addr;
pcm_remaining = size;
I2STXCOM = 0xe;
DMAC0CONFIG |= 4;
INT_DMAC0C0();
}
void pcm_play_dma_stop(void)
{
DMAC0C0CONFIG = 0x8a80;
I2STXCOM = 0xa;
}
/* pause playback by disabling LRCK */
void pcm_play_dma_pause(bool pause)
{
if (pause) I2STXCOM |= 1;
else I2STXCOM &= ~1;
}
void pcm_play_dma_init(void)
{
PWRCON(0) &= ~(1 << 4);
PWRCON(1) &= ~(1 << 7);
I2S40 = 0x110;
I2STXCON = 0xb100059;
I2SCLKCON = 1;
VIC0INTENABLE = 1 << IRQ_DMAC0;
audiohw_preinit();
}
void pcm_play_dma_postinit(void)
{
audiohw_postinit();
}
void pcm_dma_apply_settings(void)
{
}
size_t pcm_get_bytes_waiting(void)
{
int bytes = pcm_remaining;
const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
while (lli)
{
bytes += (lli->control & 0xfff) * 2;
if (lli == lastlli) break;
lli = lli->nextlli;
}
return bytes;
}
const void* pcm_play_dma_get_peak_buffer(int *count)
{
*count = (DMAC0C0LLI.control & 0xfff) * 2;
return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
}
#ifdef HAVE_PCM_DMA_ADDRESS
void * pcm_dma_addr(void *addr)
{
return addr;
}
#endif
/****************************************************************************
** Recording DMA transfer
**/
#ifdef HAVE_RECORDING
void pcm_rec_lock(void)
{
}
void pcm_rec_unlock(void)
{
}
void pcm_rec_dma_stop(void)
{
}
void pcm_rec_dma_start(void *addr, size_t size)
{
(void)addr;
(void)size;
}
void pcm_rec_dma_close(void)
{
}
void pcm_rec_dma_init(void)
{
}
const void * pcm_rec_dma_get_peak_buffer(void)
{
return NULL;
}
#endif /* HAVE_RECORDING */

80
firmware/target/arm/s5l8702/pcm-target.h
View file

@ -1,40 +1,40 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
*
* Copyright (C) 2010 by Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __PCM_TARGET_H__
#define __PCM_TARGET_H__
/* S5L8702 PCM driver tunables: */
#define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */
#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
/* (bigger chunks will be segmented internally) */
#define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */
#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
extern struct dma_lli pcm_lli[PCM_LLICOUNT];
extern size_t pcm_remaining;
extern size_t pcm_chunksize;
#endif /* __PCM_TARGET_H__ */
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
*
* Copyright (C) 2010 by Michael Sparmann
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __PCM_TARGET_H__
#define __PCM_TARGET_H__
/* S5L8702 PCM driver tunables: */
#define PCM_LLIMAX (2047) /* Maximum number of samples per LLI */
#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
/* (bigger chunks will be segmented internally) */
#define PCM_WATERMARK (512) /* Number of remaining samples to schedule IRQ at */
#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
extern struct dma_lli pcm_lli[PCM_LLICOUNT];
extern size_t pcm_remaining;
extern size_t pcm_chunksize;
#endif /* __PCM_TARGET_H__ */

94
firmware/target/arm/s5l8702/system-target.h
View file

@ -1,47 +1,47 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
*
* Copyright (C) 2007 by Dave Chapman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef SYSTEM_TARGET_H
#define SYSTEM_TARGET_H
#include "system-arm.h"
#include "mmu-arm.h"
#define CPUFREQ_SLEEP 32768
#define CPUFREQ_MAX 216000000
#define CPUFREQ_DEFAULT 108000000
#define CPUFREQ_NORMAL 108000000
#define STORAGE_WANTS_ALIGN
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a))
#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
#define inw(a) (*(volatile unsigned short*) (a))
#define outw(a,b) (*(volatile unsigned short*) (b) = (a))
static inline void udelay(unsigned usecs)
{
unsigned stop = USEC_TIMER + usecs;
while (TIME_BEFORE(USEC_TIMER, stop));
}
#endif /* SYSTEM_TARGET_H */
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: system-target.h 28791 2010-12-11 09:39:33Z Buschel $
*
* Copyright (C) 2007 by Dave Chapman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef SYSTEM_TARGET_H
#define SYSTEM_TARGET_H
#include "system-arm.h"
#include "mmu-arm.h"
#define CPUFREQ_SLEEP 32768
#define CPUFREQ_MAX 216000000
#define CPUFREQ_DEFAULT 108000000
#define CPUFREQ_NORMAL 108000000
#define STORAGE_WANTS_ALIGN
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a))
#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
#define inw(a) (*(volatile unsigned short*) (a))
#define outw(a,b) (*(volatile unsigned short*) (b) = (a))
static inline void udelay(unsigned usecs)
{
unsigned stop = USEC_TIMER + usecs;
while (TIME_BEFORE(USEC_TIMER, stop));
}
#endif /* SYSTEM_TARGET_H */

188
firmware/target/arm/s5l8702/timer-s5l8702.c
View file

@ -1,94 +1,94 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $
*
* Copyright (C) 2009 Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "inttypes.h"
#include "s5l8702.h"
#include "system.h"
#include "timer.h"
//TODO: This needs calibration once we figure out the clocking
void INT_TIMERC(void)
{
/* clear interrupt */
TCCON = TCCON;
if (pfn_timer != NULL) {
pfn_timer();
}
}
bool timer_set(long cycles, bool start)
{
static const int cs_table[] = {1, 2, 4, 6};
int prescale, cs;
long count;
/* stop and clear timer */
TCCMD = (1 << 1); /* TD_CLR */
/* optionally unregister any previously registered timer user */
if (start) {
if (pfn_unregister != NULL) {
pfn_unregister();
pfn_unregister = NULL;
}
}
/* scale the count down with the clock select */
for (cs = 0; cs < 4; cs++) {
count = cycles >> cs_table[cs];
if ((count < 65536) || (cs == 3)) {
break;
}
}
/* scale the count down with the prescaler */
prescale = 1;
while (count >= 65536) {
count >>= 1;
prescale <<= 1;
}
/* configure timer */
TCCON = (1 << 12) | /* TD_INT0_EN */
(cs << 8) | /* TS_CS */
(0 << 4); /* TD_MODE_SEL, 0 = interval mode */
TCPRE = prescale - 1;
TCDATA0 = count;
TCCMD = (1 << 0); /* TD_ENABLE */
return true;
}
bool timer_start(void)
{
TCCMD = (1 << 0); /* TD_ENABLE */
return true;
}
void timer_stop(void)
{
TCCMD = (0 << 0); /* TD_ENABLE */
}
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: timer-s5l8700.c 23103 2009-10-11 11:35:14Z theseven $
*
* Copyright (C) 2009 Bertrik Sikken
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "inttypes.h"
#include "s5l8702.h"
#include "system.h"
#include "timer.h"
//TODO: This needs calibration once we figure out the clocking
void INT_TIMERC(void)
{
/* clear interrupt */
TCCON = TCCON;
if (pfn_timer != NULL) {
pfn_timer();
}
}
bool timer_set(long cycles, bool start)
{
static const int cs_table[] = {1, 2, 4, 6};
int prescale, cs;
long count;
/* stop and clear timer */
TCCMD = (1 << 1); /* TD_CLR */
/* optionally unregister any previously registered timer user */
if (start) {
if (pfn_unregister != NULL) {
pfn_unregister();
pfn_unregister = NULL;
}
}
/* scale the count down with the clock select */
for (cs = 0; cs < 4; cs++) {
count = cycles >> cs_table[cs];
if ((count < 65536) || (cs == 3)) {
break;
}
}
/* scale the count down with the prescaler */
prescale = 1;
while (count >= 65536) {
count >>= 1;
prescale <<= 1;
}
/* configure timer */
TCCON = (1 << 12) | /* TD_INT0_EN */
(cs << 8) | /* TS_CS */
(0 << 4); /* TD_MODE_SEL, 0 = interval mode */
TCPRE = prescale - 1;
TCDATA0 = count;
TCCMD = (1 << 0); /* TD_ENABLE */
return true;
}
bool timer_start(void)
{
TCCMD = (1 << 0); /* TD_ENABLE */
return true;
}
void timer_stop(void)
{
TCCMD = (0 << 0); /* TD_ENABLE */
}

2
firmware/target/sh/archos/mascodec-archos.c
View file

@ -5,7 +5,7 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id: mas.c 18807 2008-10-14 11:12:20Z zagor $
* $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*