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imx233: fix clkctrl naming
Move to a more consistent naming convention like the other devices Change-Id: I4ddbbee27ee9f5ae775c5776592ec7ce02b30948
This commit is contained in:
Amaury Pouly
parent
9022c69b64
commit
553aeae9c6
8 changed files with 100 additions and 98 deletions
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@ -30,7 +30,7 @@ void imx233_audioout_preinit(void)
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/* Enable AUDIOOUT block */
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imx233_reset_block(&HW_AUDIOOUT_CTRL);
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/* Enable digital filter clock */
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imx233_enable_xtal_clock(XTAL_FILT, true);
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imx233_clkctrl_enable_xtal(XTAL_FILT, true);
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/* Enable DAC */
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__REG_CLR(HW_AUDIOOUT_ANACLKCTRL) = HW_AUDIOOUT_ANACLKCTRL__CLKGATE;
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/* Set capless mode */
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@ -76,7 +76,7 @@ void imx233_audioout_close(void)
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/* Gate off DAC */
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__REG_SET(HW_AUDIOOUT_ANACLKCTRL) = HW_AUDIOOUT_ANACLKCTRL__CLKGATE;
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/* Disable digital filter clock */
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imx233_enable_xtal_clock(XTAL_FILT, false);
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imx233_clkctrl_enable_xtal(XTAL_FILT, false);
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/* will also gate off the module */
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__REG_CLR(HW_AUDIOOUT_CTRL) = HW_AUDIOOUT_CTRL__RUN;
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}
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@ -23,7 +23,7 @@
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#define __CLK_CLKGATE (1 << 31)
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#define __CLK_BUSY (1 << 29)
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void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable)
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void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
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{
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if(enable)
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__REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk;
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@ -31,12 +31,12 @@ void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable)
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__REG_SET(HW_CLKCTRL_XTAL) = xtal_clk;
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}
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bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk)
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bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
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{
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return HW_CLKCTRL_XTAL & clk;
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}
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void imx233_enable_clock(enum imx233_clock_t clk, bool enable)
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void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
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{
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volatile uint32_t *REG;
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switch(clk)
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@ -60,7 +60,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable)
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}
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}
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bool imx233_is_clock_enable(enum imx233_clock_t clk)
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bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
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{
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volatile uint32_t *REG;
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switch(clk)
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@ -74,7 +74,7 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk)
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return !((*REG) & __CLK_CLKGATE);
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}
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void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
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void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
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{
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
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switch(clk)
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@ -101,7 +101,7 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
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}
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}
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int imx233_get_clock_divisor(enum imx233_clock_t clk)
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int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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@ -119,7 +119,7 @@ int imx233_get_clock_divisor(enum imx233_clock_t clk)
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}
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}
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void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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{
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/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
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volatile uint8_t *REG;
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@ -142,7 +142,7 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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*REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;;
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}
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int imx233_get_fractional_divisor(enum imx233_clock_t clk)
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int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
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{
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/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
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volatile uint8_t *REG;
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@ -166,7 +166,7 @@ int imx233_get_fractional_divisor(enum imx233_clock_t clk)
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return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE;
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}
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void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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{
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uint32_t msk;
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switch(clk)
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@ -184,7 +184,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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__REG_CLR(HW_CLKCTRL_CLKSEQ) = msk;
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}
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bool imx233_get_bypass_pll(enum imx233_clock_t clk)
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bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
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{
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uint32_t msk;
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switch(clk)
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@ -199,7 +199,7 @@ bool imx233_get_bypass_pll(enum imx233_clock_t clk)
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return HW_CLKCTRL_CLKSEQ & msk;
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}
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void imx233_enable_usb_pll(bool enable)
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void imx233_clkctrl_enable_usb_pll(bool enable)
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{
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if(enable)
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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@ -207,23 +207,23 @@ void imx233_enable_usb_pll(bool enable)
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__REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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}
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bool imx233_is_usb_pll_enable(void)
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bool imx233_clkctrl_is_usb_pll_enabled(void)
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{
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return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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}
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void imx233_set_auto_slow_divisor(enum imx233_as_div_t div)
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void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
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{
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__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__SLOW_DIV_BM;
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__REG_SET(HW_CLKCTRL_HBUS) = div;
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}
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enum imx233_as_div_t imx233_get_auto_slow_divisor(void)
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enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
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{
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return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV);
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}
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void imx233_enable_auto_slow(bool enable)
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void imx233_clkctrl_enable_auto_slow(bool enable)
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{
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if(enable)
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__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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@ -231,12 +231,12 @@ void imx233_enable_auto_slow(bool enable)
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__REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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}
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bool imx233_is_auto_slow_enable(void)
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bool imx233_clkctrl_is_auto_slow_enabled(void)
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{
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return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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}
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void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
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void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
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{
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if(enable)
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__REG_SET(HW_CLKCTRL_HBUS) = monitor;
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@ -244,17 +244,17 @@ void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enab
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__REG_CLR(HW_CLKCTRL_HBUS) = monitor;
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}
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bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor)
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bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
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{
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return HW_CLKCTRL_HBUS & monitor;
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}
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unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
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unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PLL: /* PLL: 480MHz when enable */
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return imx233_is_clock_enable(CLK_PLL) ? 480000 : 0;
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return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0;
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case CLK_XTAL: /* crystal: 24MHz */
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return 24000;
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case CLK_CPU:
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@ -263,78 +263,78 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
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/* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider
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* otherwise, clk_p derived from clk_cpu via int div and clk_cpu
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* derived from clk_pll fracdiv */
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if(imx233_get_bypass_pll(CLK_CPU))
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if(imx233_clkctrl_get_bypass_pll(CLK_CPU))
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{
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ref = imx233_get_clock_freq(CLK_XTAL);
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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/* Integer divide mode vs fractional divide mode */
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if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN)
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return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32;
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else
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return ref / imx233_get_clock_divisor(CLK_CPU);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
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}
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else
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{
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ref = imx233_get_clock_freq(CLK_PLL);
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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/* fractional divider enable ? */
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if(imx233_get_fractional_divisor(CLK_CPU) != 0)
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ref = (ref * 18) / imx233_get_fractional_divisor(CLK_CPU);
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return ref / imx233_get_clock_divisor(CLK_CPU);
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if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
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}
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}
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case CLK_HBUS:
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{
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/* Derived from clk_p via integer/fractional div */
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unsigned ref = imx233_get_clock_freq(CLK_CPU);
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if(imx233_get_fractional_divisor(CLK_HBUS) != 0)
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ref = (ref * imx233_get_fractional_divisor(CLK_HBUS)) / 32;
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if(imx233_get_clock_divisor(CLK_HBUS) != 0)
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ref /= imx233_get_clock_divisor(CLK_HBUS);
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unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU);
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if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0)
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ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32;
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if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0)
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ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS);
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return ref;
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}
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case CLK_IO:
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{
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/* Derived from clk_pll via fracdiv */
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unsigned ref = imx233_get_clock_freq(CLK_PLL);
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if(imx233_get_fractional_divisor(CLK_IO) != 0)
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ref = (ref * 18) / imx233_get_fractional_divisor(CLK_IO);
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unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO);
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return ref;
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}
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case CLK_PIX:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(!imx233_is_clock_enable(CLK_PIX))
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if(!imx233_clkctrl_is_clock_enabled(CLK_PIX))
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ref = 0;
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else if(imx233_get_bypass_pll(CLK_PIX))
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ref = imx233_get_clock_freq(CLK_XTAL);
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else if(imx233_clkctrl_get_bypass_pll(CLK_PIX))
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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else
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{
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ref = imx233_get_clock_freq(CLK_PLL);
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if(imx233_get_fractional_divisor(CLK_PIX) != 0)
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ref = (ref * 18) / imx233_get_fractional_divisor(CLK_PIX);
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX);
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}
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return ref / imx233_get_clock_divisor(CLK_PIX);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX);
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}
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case CLK_SSP:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(!imx233_is_clock_enable(CLK_SSP))
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if(!imx233_clkctrl_is_clock_enabled(CLK_SSP))
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ref = 0;
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else if(imx233_get_bypass_pll(CLK_SSP))
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ref = imx233_get_clock_freq(CLK_XTAL);
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else if(imx233_clkctrl_get_bypass_pll(CLK_SSP))
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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else
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ref = imx233_get_clock_freq(CLK_IO);
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return ref / imx233_get_clock_divisor(CLK_SSP);
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ref = imx233_clkctrl_get_clock_freq(CLK_IO);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP);
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}
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case CLK_EMI:
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{
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unsigned ref;
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/* Derived from clk_pll or clk_xtal */
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if(imx233_get_bypass_pll(CLK_EMI))
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if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
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{
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ref = imx233_get_clock_freq(CLK_XTAL);
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE)
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return 0;
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else
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@ -342,14 +342,15 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
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}
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else
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{
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ref = imx233_get_clock_freq(CLK_PLL);
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if(imx233_get_fractional_divisor(CLK_EMI) != 0)
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ref = (ref * 18) / imx233_get_fractional_divisor(CLK_EMI);
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return ref / imx233_get_clock_divisor(CLK_EMI);
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ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
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if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0)
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ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI);
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return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI);
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}
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}
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case CLK_XBUS:
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return imx233_get_clock_freq(CLK_XTAL) / imx233_get_clock_divisor(CLK_XBUS);
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return imx233_clkctrl_get_clock_freq(CLK_XTAL) /
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imx233_clkctrl_get_clock_divisor(CLK_XBUS);
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default:
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return 0;
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}
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@ -132,6 +132,7 @@ enum imx233_xtal_clk_t
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XTAL_FILT = 1 << 30,
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XTAL_DRI = 1 << 28,
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XTAL_TIMROT = 1 << 26,
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XTAM_PWM = 1 << 29,
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};
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/* Auto-Slow monitoring */
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@ -158,28 +159,28 @@ enum imx233_as_div_t
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};
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/* can use a mask of clocks */
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void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable);
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bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk);
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void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable);
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void imx233_clkctrl_is_xtal_enabled(enum imx233_xtal_clk_t xtal_clk, bool enable);
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/* only use it for non-fractional clocks (ie not for IO) */
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void imx233_enable_clock(enum imx233_clock_t clk, bool enable);
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bool imx233_is_clock_enable(enum imx233_clock_t cl);
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void imx233_set_clock_divisor(enum imx233_clock_t clk, int div);
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int imx233_get_clock_divisor(enum imx233_clock_t clk);
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void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable);
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bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t cl);
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void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div);
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int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk);
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/* call with fracdiv=0 to disable it */
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void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
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void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
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/* 0 means fractional dividor disable */
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int imx233_get_fractional_divisor(enum imx233_clock_t clk);
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void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
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bool imx233_get_bypass_pll(enum imx233_clock_t clk);
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void imx233_enable_usb_pll(bool enable);
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bool imx233_is_usb_pll_enable(void);
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unsigned imx233_get_clock_freq(enum imx233_clock_t clk);
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int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk);
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void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
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bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk);
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void imx233_clkctrl_enable_usb_pll(bool enable);
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bool imx233_clkctrl_is_usb_pll_enabled(void);
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unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk);
|
||||
|
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void imx233_set_auto_slow_divisor(enum imx233_as_div_t div);
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enum imx233_as_div_t imx233_get_auto_slow_divisor(void);
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void imx233_enable_auto_slow(bool enable);
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bool imx233_is_auto_slow_enable(void);
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void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
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bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor);
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void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div);
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||||
enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void);
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||||
void imx233_clkctrl_enable_auto_slow(bool enable);
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||||
bool imx233_clkctrl_is_auto_slow_enabled(void);
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||||
void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable);
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bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor);
|
||||
|
||||
#endif /* CLKCTRL_IMX233_H */
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||||
|
|
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|||
|
|
@ -235,19 +235,19 @@ bool dbg_hw_info_clkctrl(void)
|
|||
#define c dbg_clk[i]
|
||||
lcd_putsf(0, i + 1, "%4s", c.name);
|
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if(c.has_enable)
|
||||
lcd_putsf(5, i + 1, "%2d", imx233_is_clock_enable(c.clk));
|
||||
lcd_putsf(5, i + 1, "%2d", imx233_clkctrl_is_clock_enabled(c.clk));
|
||||
if(c.has_bypass)
|
||||
lcd_putsf(8, i + 1, "%2d", imx233_get_bypass_pll(c.clk));
|
||||
if(c.has_idiv && imx233_get_clock_divisor(c.clk) != 0)
|
||||
lcd_putsf(10, i + 1, "%4d", imx233_get_clock_divisor(c.clk));
|
||||
if(c.has_fdiv && imx233_get_fractional_divisor(c.clk) != 0)
|
||||
lcd_putsf(16, i + 1, "%4d", imx233_get_fractional_divisor(c.clk));
|
||||
lcd_putsf(8, i + 1, "%2d", imx233_clkctrl_get_bypass_pll(c.clk));
|
||||
if(c.has_idiv && imx233_clkctrl_get_clock_divisor(c.clk) != 0)
|
||||
lcd_putsf(10, i + 1, "%4d", imx233_clkctrl_get_clock_divisor(c.clk));
|
||||
if(c.has_fdiv && imx233_clkctrl_get_fractional_divisor(c.clk) != 0)
|
||||
lcd_putsf(16, i + 1, "%4d", imx233_clkctrl_get_fractional_divisor(c.clk));
|
||||
if(c.has_freq)
|
||||
lcd_putsf(21, i + 1, "%9d", imx233_get_clock_freq(c.clk));
|
||||
lcd_putsf(21, i + 1, "%9d", imx233_clkctrl_get_clock_freq(c.clk));
|
||||
#undef c
|
||||
}
|
||||
int line = ARRAYLEN(dbg_clk) + 1;
|
||||
lcd_putsf(0, line, "auto slow: %d", imx233_is_auto_slow_enable());
|
||||
lcd_putsf(0, line, "auto slow: %d", imx233_clkctrl_is_auto_slow_enabled());
|
||||
line++;
|
||||
lcd_putsf(0, line, "as monitor: ");
|
||||
int x_off = 12;
|
||||
|
|
@ -255,7 +255,7 @@ bool dbg_hw_info_clkctrl(void)
|
|||
unsigned line_w = lcd_getwidth() / font_get_width(font_get(lcd_getfont()), ' ');
|
||||
for(unsigned i = 0; i < ARRAYLEN(dbg_as_monitor); i++)
|
||||
{
|
||||
if(!imx233_is_auto_slow_monitor_enable(dbg_as_monitor[i].monitor))
|
||||
if(!imx233_clkctrl_is_auto_slow_monitor_enabled(dbg_as_monitor[i].monitor))
|
||||
continue;
|
||||
if(!first)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -157,10 +157,10 @@ static inline uint32_t decode_18_to_16(uint32_t a)
|
|||
static void setup_lcdif_clock(void)
|
||||
{
|
||||
/* the LCD seems to work at 24Mhz, so use the xtal clock with no divider */
|
||||
imx233_enable_clock(CLK_PIX, false);
|
||||
imx233_set_clock_divisor(CLK_PIX, 1);
|
||||
imx233_set_bypass_pll(CLK_PIX, true); /* use XTAL */
|
||||
imx233_enable_clock(CLK_PIX, true);
|
||||
imx233_clkctrl_enable_clock(CLK_PIX, false);
|
||||
imx233_clkctrl_set_clock_divisor(CLK_PIX, 1);
|
||||
imx233_clkctrl_set_bypass_pll(CLK_PIX, true); /* use XTAL */
|
||||
imx233_clkctrl_enable_clock(CLK_PIX, true);
|
||||
}
|
||||
|
||||
static uint32_t i80_read_register(uint32_t data_out)
|
||||
|
|
|
|||
|
|
@ -106,11 +106,11 @@ void imx233_ssp_start(int ssp)
|
|||
/** 2.3.1: the clk_ssp maximum frequency is 102.858 MHz */
|
||||
/* fracdiv = 18 => clk_io = pll = 480Mhz
|
||||
* intdiv = 5 => clk_ssp = 96Mhz */
|
||||
imx233_set_fractional_divisor(CLK_IO, 18);
|
||||
imx233_enable_clock(CLK_SSP, false);
|
||||
imx233_set_clock_divisor(CLK_SSP, 5);
|
||||
imx233_set_bypass_pll(CLK_SSP, false); /* use IO */
|
||||
imx233_enable_clock(CLK_SSP, true);
|
||||
imx233_clkctrl_set_fractional_divisor(CLK_IO, 18);
|
||||
imx233_clkctrl_enable_clock(CLK_SSP, false);
|
||||
imx233_clkctrl_set_clock_divisor(CLK_SSP, 5);
|
||||
imx233_clkctrl_set_bypass_pll(CLK_SSP, false); /* use IO */
|
||||
imx233_clkctrl_enable_clock(CLK_SSP, true);
|
||||
}
|
||||
ssp_nr_in_use++;
|
||||
}
|
||||
|
|
@ -128,8 +128,8 @@ void imx233_ssp_stop(int ssp)
|
|||
ssp_nr_in_use--;
|
||||
if(ssp_nr_in_use == 0)
|
||||
{
|
||||
imx233_enable_clock(CLK_SSP, false);
|
||||
imx233_set_fractional_divisor(CLK_IO, 0);
|
||||
imx233_clkctrl_enable_clock(CLK_SSP, false);
|
||||
imx233_clkctrl_set_fractional_divisor(CLK_IO, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -75,5 +75,5 @@ void imx233_timrot_init(void)
|
|||
{
|
||||
imx233_reset_block(&HW_TIMROT_ROTCTRL);
|
||||
/* enable xtal path to timrot */
|
||||
imx233_enable_xtal_clock(XTAL_TIMROT, true);
|
||||
imx233_clkctrl_enable_xtal(XTAL_TIMROT, true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ void usb_enable(bool on)
|
|||
{
|
||||
if(on)
|
||||
{
|
||||
imx233_enable_usb_pll(true);
|
||||
imx233_clkctrl_enable_usb_pll(true);
|
||||
imx233_enable_usb_phy(true);
|
||||
imx233_enable_usb_controller(true);
|
||||
usb_core_init();
|
||||
|
|
@ -79,6 +79,6 @@ void usb_enable(bool on)
|
|||
usb_core_exit();
|
||||
imx233_enable_usb_controller(false);
|
||||
imx233_enable_usb_phy(false);
|
||||
imx233_enable_usb_pll(false);
|
||||
imx233_clkctrl_enable_usb_pll(false);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue