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imx233: fix clkctrl naming

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Move to a more consistent naming convention like the other devices

Change-Id: I4ddbbee27ee9f5ae775c5776592ec7ce02b30948
This commit is contained in:
Amaury Pouly 2012-05-19 13:16:17 +02:00
parent 9022c69b64
commit 553aeae9c6
8 changed files with 100 additions and 98 deletions
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109
firmware/target/arm/imx233/clkctrl-imx233.c
View file

@ -23,7 +23,7 @@
#define __CLK_CLKGATE (1 << 31)
#define __CLK_BUSY (1 << 29)
void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable)
void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
{
if(enable)
__REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk;
@ -31,12 +31,12 @@ void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable)
__REG_SET(HW_CLKCTRL_XTAL) = xtal_clk;
}
bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk)
bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
{
return HW_CLKCTRL_XTAL & clk;
}
void imx233_enable_clock(enum imx233_clock_t clk, bool enable)
void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
{
volatile uint32_t *REG;
switch(clk)
@ -60,7 +60,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable)
}
}
bool imx233_is_clock_enable(enum imx233_clock_t clk)
bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
{
volatile uint32_t *REG;
switch(clk)
@ -74,7 +74,7 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk)
return !((*REG) & __CLK_CLKGATE);
}
void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
{
/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
switch(clk)
@ -101,7 +101,7 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div)
}
}
int imx233_get_clock_divisor(enum imx233_clock_t clk)
int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
{
switch(clk)
{
@ -119,7 +119,7 @@ int imx233_get_clock_divisor(enum imx233_clock_t clk)
}
}
void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
{
/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
volatile uint8_t *REG;
@ -142,7 +142,7 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
*REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;;
}
int imx233_get_fractional_divisor(enum imx233_clock_t clk)
int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
{
/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
volatile uint8_t *REG;
@ -166,7 +166,7 @@ int imx233_get_fractional_divisor(enum imx233_clock_t clk)
return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE;
}
void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
{
uint32_t msk;
switch(clk)
@ -184,7 +184,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
__REG_CLR(HW_CLKCTRL_CLKSEQ) = msk;
}
bool imx233_get_bypass_pll(enum imx233_clock_t clk)
bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
{
uint32_t msk;
switch(clk)
@ -199,7 +199,7 @@ bool imx233_get_bypass_pll(enum imx233_clock_t clk)
return HW_CLKCTRL_CLKSEQ & msk;
}
void imx233_enable_usb_pll(bool enable)
void imx233_clkctrl_enable_usb_pll(bool enable)
{
if(enable)
__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
@ -207,23 +207,23 @@ void imx233_enable_usb_pll(bool enable)
__REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
}
bool imx233_is_usb_pll_enable(void)
bool imx233_clkctrl_is_usb_pll_enabled(void)
{
return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
}
void imx233_set_auto_slow_divisor(enum imx233_as_div_t div)
void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
{
__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__SLOW_DIV_BM;
__REG_SET(HW_CLKCTRL_HBUS) = div;
}
enum imx233_as_div_t imx233_get_auto_slow_divisor(void)
enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
{
return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV);
}
void imx233_enable_auto_slow(bool enable)
void imx233_clkctrl_enable_auto_slow(bool enable)
{
if(enable)
__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
@ -231,12 +231,12 @@ void imx233_enable_auto_slow(bool enable)
__REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
}
bool imx233_is_auto_slow_enable(void)
bool imx233_clkctrl_is_auto_slow_enabled(void)
{
return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
}
void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
{
if(enable)
__REG_SET(HW_CLKCTRL_HBUS) = monitor;
@ -244,17 +244,17 @@ void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enab
__REG_CLR(HW_CLKCTRL_HBUS) = monitor;
}
bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor)
bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
{
return HW_CLKCTRL_HBUS & monitor;
}
unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
{
switch(clk)
{
case CLK_PLL: /* PLL: 480MHz when enable */
return imx233_is_clock_enable(CLK_PLL) ? 480000 : 0;
return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0;
case CLK_XTAL: /* crystal: 24MHz */
return 24000;
case CLK_CPU:
@ -263,78 +263,78 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
/* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider
* otherwise, clk_p derived from clk_cpu via int div and clk_cpu
* derived from clk_pll fracdiv */
if(imx233_get_bypass_pll(CLK_CPU))
if(imx233_clkctrl_get_bypass_pll(CLK_CPU))
{
ref = imx233_get_clock_freq(CLK_XTAL);
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
/* Integer divide mode vs fractional divide mode */
if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN)
return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32;
else
return ref / imx233_get_clock_divisor(CLK_CPU);
return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
}
else
{
ref = imx233_get_clock_freq(CLK_PLL);
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
/* fractional divider enable ? */
if(imx233_get_fractional_divisor(CLK_CPU) != 0)
ref = (ref * 18) / imx233_get_fractional_divisor(CLK_CPU);
return ref / imx233_get_clock_divisor(CLK_CPU);
if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU);
return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
}
}
case CLK_HBUS:
{
/* Derived from clk_p via integer/fractional div */
unsigned ref = imx233_get_clock_freq(CLK_CPU);
if(imx233_get_fractional_divisor(CLK_HBUS) != 0)
ref = (ref * imx233_get_fractional_divisor(CLK_HBUS)) / 32;
if(imx233_get_clock_divisor(CLK_HBUS) != 0)
ref /= imx233_get_clock_divisor(CLK_HBUS);
unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU);
if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0)
ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32;
if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0)
ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS);
return ref;
}
case CLK_IO:
{
/* Derived from clk_pll via fracdiv */
unsigned ref = imx233_get_clock_freq(CLK_PLL);
if(imx233_get_fractional_divisor(CLK_IO) != 0)
ref = (ref * 18) / imx233_get_fractional_divisor(CLK_IO);
unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO);
return ref;
}
case CLK_PIX:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(!imx233_is_clock_enable(CLK_PIX))
if(!imx233_clkctrl_is_clock_enabled(CLK_PIX))
ref = 0;
else if(imx233_get_bypass_pll(CLK_PIX))
ref = imx233_get_clock_freq(CLK_XTAL);
else if(imx233_clkctrl_get_bypass_pll(CLK_PIX))
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
else
{
ref = imx233_get_clock_freq(CLK_PLL);
if(imx233_get_fractional_divisor(CLK_PIX) != 0)
ref = (ref * 18) / imx233_get_fractional_divisor(CLK_PIX);
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX);
}
return ref / imx233_get_clock_divisor(CLK_PIX);
return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX);
}
case CLK_SSP:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(!imx233_is_clock_enable(CLK_SSP))
if(!imx233_clkctrl_is_clock_enabled(CLK_SSP))
ref = 0;
else if(imx233_get_bypass_pll(CLK_SSP))
ref = imx233_get_clock_freq(CLK_XTAL);
else if(imx233_clkctrl_get_bypass_pll(CLK_SSP))
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
else
ref = imx233_get_clock_freq(CLK_IO);
return ref / imx233_get_clock_divisor(CLK_SSP);
ref = imx233_clkctrl_get_clock_freq(CLK_IO);
return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP);
}
case CLK_EMI:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
if(imx233_get_bypass_pll(CLK_EMI))
if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
{
ref = imx233_get_clock_freq(CLK_XTAL);
ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE)
return 0;
else
@ -342,14 +342,15 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk)
}
else
{
ref = imx233_get_clock_freq(CLK_PLL);
if(imx233_get_fractional_divisor(CLK_EMI) != 0)
ref = (ref * 18) / imx233_get_fractional_divisor(CLK_EMI);
return ref / imx233_get_clock_divisor(CLK_EMI);
ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0)
ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI);
return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI);
}
}
case CLK_XBUS:
return imx233_get_clock_freq(CLK_XTAL) / imx233_get_clock_divisor(CLK_XBUS);
return imx233_clkctrl_get_clock_freq(CLK_XTAL) /
imx233_clkctrl_get_clock_divisor(CLK_XBUS);
default:
return 0;
}