len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-11 06:05:21 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

sd-as3525v2: detail MCI_CTRL bits

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24826 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-02-21 22:01:09 +00:00
parent 48ed5ad66e
commit 4be56226c1
1 changed files with 28 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

41
firmware/target/arm/as3525/sd-as3525v2.c
View file

@ -138,6 +138,20 @@ static void printf(const char *format, ...)
#define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x)) #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
#define MCI_CTRL SD_REG(0x00) #define MCI_CTRL SD_REG(0x00)
#define CTRL_RESET (1<<0)
#define FIFO_RESET (1<<1)
#define DMA_RESET (1<<2)
#define INT_ENABLE (1<<4)
#define DMA_ENABLE (1<<5)
#define READ_WAIT (1<<6)
#define SEND_IRQ_RESP (1<<7)
#define ABRT_READ_DATA (1<<8)
#define SEND_CCSD (1<<9)
#define SEND_AS_CCSD (1<<10)
#define EN_OD_PULLUP (1<<24)
#define MCI_PWREN SD_REG(0x04) /* power enable */ #define MCI_PWREN SD_REG(0x04) /* power enable */
#define MCI_CLKDIV SD_REG(0x08) /* clock divider */ #define MCI_CLKDIV SD_REG(0x08) /* clock divider */
#define MCI_CLKSRC SD_REG(0x0C) /* clock source */ #define MCI_CLKSRC SD_REG(0x0C) /* clock source */
@ -217,7 +231,7 @@ static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
void INT_NAND(void) void INT_NAND(void)
{ {
MCI_CTRL &= ~0x10; // ? MCI_CTRL &= INT_ENABLE;
const int status = MCI_STATUS; const int status = MCI_STATUS;
#if 0 #if 0
@ -265,7 +279,7 @@ void INT_NAND(void)
//while(!button_read_device()); //while(!button_read_device());
//while(button_read_device()); //while(button_read_device());
MCI_CTRL |= 0x10; // ? MCI_CTRL |= INT_ENABLE;
} }
static bool send_cmd(const int cmd, const int arg, const int flags, static bool send_cmd(const int cmd, const int arg, const int flags,
@ -313,7 +327,7 @@ static bool send_cmd(const int cmd, const int arg, const int flags,
MCI_ARGUMENT = arg; MCI_ARGUMENT = arg;
MCI_COMMAND = val; MCI_COMMAND = val;
MCI_CTRL |= 0x10; MCI_CTRL |= INT_ENABLE;
max = 1000; max = 1000;
while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */ while(max-- && MCI_COMMAND & MCI_COMMAND_ACTIVE); /* wait for cmd completion */
@ -479,22 +493,21 @@ static void init_controller(void)
mci_delay(); mci_delay();
MCI_CTRL |= 1; MCI_CTRL |= CTRL_RESET; /* FIXME: FIFO & DMA reset? */
int max = 1000; while(MCI_CTRL & CTRL_RESET)
while(max-- && !(MCI_CTRL & 1))
; ;
MCI_RAW_STATUS = 0xffffffff; MCI_RAW_STATUS = 0xffffffff;
MCI_MASK = 0xffffbffe; MCI_MASK = 0xffffbffe;
MCI_CTRL |= 0x10; MCI_CTRL |= INT_ENABLE;
MCI_TMOUT = 0xffffffff; MCI_TMOUT = 0xffffffff;
MCI_CLKENA = (1<<shift) - 1; MCI_CLKENA = (1<<shift) - 1;
MCI_ARGUMENT = 0; MCI_ARGUMENT = 0;
MCI_COMMAND = 0x80202000; MCI_COMMAND = 0x80202000;
max = 10; int max = 10;
while(max-- && (MCI_COMMAND & (1<<31))) ; while(max-- && (MCI_COMMAND & (1<<31))) ;
MCI_DEBNCE = 0xfffff; MCI_DEBNCE = 0xfffff;
@ -654,18 +667,20 @@ static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool w
write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK; write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
MCI_CTRL |= 2; MCI_CTRL |= FIFO_RESET;
while(MCI_CTRL & 2) ; while(MCI_CTRL & FIFO_RESET)
;
//MCI_BLKSIZ = 512; //MCI_BLKSIZ = 512;
MCI_BYTCNT = transfer * 512; MCI_BYTCNT = transfer * 512;
MCI_CTRL |= 2; MCI_CTRL |= FIFO_RESET;
while(MCI_CTRL & 2) ; while(MCI_CTRL & FIFO_RESET)
;
MCI_FIFOTH &= ~0x7fff0fff; MCI_FIFOTH &= ~0x7fff0fff;
MCI_CTRL |= 0x20; MCI_CTRL |= DMA_ENABLE;
MCI_MASK = 0xBE8C; MCI_MASK = 0xBE8C;
MCI_FIFOTH |= 0x503f0080; MCI_FIFOTH |= 0x503f0080;