test_cyc: AS3525v2 cache and write testing

The rows that calibrated the Clip+ model in utils/perfsim, timed on
AS3525v2 with the tick timer's count for a 2/3 microsecond clock:

  - calls, returns and loads into pc, interlocks after a load and
    after a multiply, multiplies by operand size
  - a miss with work after it, on each word of its line, back to
    back, and evicting a dirty line; a load or store to the line
    still filling
  - stores to lines not cached: one stream, a word a line, four
    words at a time, two streams turn about
  - copies between uncached buffers, within a memory and across
  - fetch misses in code written where it runs
  - loops of adds and of branches by how many lines they cover, and
    a cached pointer chase likewise
  - the TTA filter stage by stage and Tremor's window loop

On AS3525v2 the miss rows run in DRAM and again in the RAM inside
the SoC, where codecs are loaded.

Rows that turned out to say nothing, or that a later row replaced,
stay in the file under TEST_CYC_ARCHIVE, each with why.
TEST_CYC_QUICK runs only the newest rows.

With these rows the plugin is about 140 KB on ARMv5, so it is left
out where the plugin buffer is 128 KB or less: the Clip, the m200v4
and the c200v2.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Change-Id: I4ec45da514d0abaa02e1e041fd1a0387490994ed
This commit is contained in:
Michael Giacomelli 2026-10-04 19:21:50 -04:00
parent 73b1afabd3
commit 49b4d8f2c9
2 changed files with 1793 additions and 27 deletions

View file

@ -218,7 +218,8 @@ test_codec.c
test_core_jpeg.c test_core_jpeg.c
#endif #endif
#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM) \ #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM) \
&& !defined(CPU_ARM_MICRO) && !defined(CPU_ARM_MICRO) \
&& PLUGIN_BUFFER_SIZE > 0x20000 /* about 140 KB on ARMv5 */
test_cyc.c test_cyc.c
#endif #endif
test_disk.c test_disk.c

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