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Sansa AMS: centralize clock settings in clock-target.h

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Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2008-12-04 20:04:31 +00:00
parent 7ea9e31658
commit 45711ac286
9 changed files with 98 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

3
firmware/target/arm/as3525/as3525-codec.c
View file

@ -38,6 +38,7 @@
*/
#include "ascodec-target.h"
#include "clock-target.h"
#include "kernel.h"
#include "as3525.h"
@ -68,7 +69,7 @@ void ascodec_init(void)
CGU_PERI |= CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE;
/* prescaler for i2c clock */
I2C2_CPSR0 = 60; /* 24 MHz / 400 kHz */
I2C2_CPSR0 = CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ);
I2C2_CPSR1 = 0; /* MSB */
/* set i2c slave address of codec part */

7
firmware/target/arm/as3525/ata_sd_as3525.c
View file

@ -35,6 +35,7 @@
#include "pl180.h" /* SD controller */
#include "pl081.h" /* DMA controller */
#include "dma-target.h" /* DMA request lines */
#include "clock-target.h"
#include "panic.h"
#include "stdbool.h"
#include "ata_idle_notify.h"
@ -375,7 +376,9 @@ static void init_pl180_controller(const int drive)
MCI_CLOCK(drive) &= ~MCI_CLOCK_POWERSAVE;
/* set MCLK divider */
mci_set_clock_divider(drive, 200);
mci_set_clock_divider(drive,
CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ));
}
int sd_init(void)
@ -384,7 +387,7 @@ int sd_init(void)
CGU_IDE = (1<<7) /* AHB interface enable */ |
(1<<6) /* interface enable */ |
(2<<2) /* clock didiver = 2+1 */ |
((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
1 /* clock source = PLLA */;
CGU_PERI |= CGU_NAF_CLOCK_ENABLE;

64
firmware/target/arm/as3525/clock-target.h Normal file
View file

@ -0,0 +1,64 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright © 2008 Rafaël Carré
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef CLOCK_TARGET_H
#define CLOCK_TARGET_H
/* PLL */
#define AS3525_PLLA_FREQ 248000000
#define AS3525_PLLA_SETTING 0x261F
/* CPU */
/* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */
#define AS3525_CPU_PREDIV 0 /* div = 1/1 */
#define CPUFREQ_MAX 248000000
#define CPUFREQ_DEFAULT 24800000
#define CPUFREQ_NORMAL 31000000
/* peripherals */
#define AS3525_PCLK_FREQ 65000000
#define AS3525_IDE_FREQ 90000000
#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
#define AS3525_I2C_FREQ 400000
/* LCD controller : varies on the models */
#if defined(SANSA_CLIP)
#define AS3525_DBOP_FREQ 6000000
#elif defined(SANSA_M200V4)
#define AS3525_DBOP_FREQ 8000000
#elif defined(SANSA_FUZE)
#define AS3525_DBOP_FREQ 24000000
#elif defined(SANSA_E200V2)
#define AS3525_DBOP_FREQ 8000000
#endif
/* macro for not giving a target clock > at the one provided */
#define CLK_DIV(ref, target) ((ref + target - 1) / target)
#endif /* CLOCK_TARGET_H */

2
firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
View file

@ -72,7 +72,7 @@ static void ams3525_dbop_init(void)
{
int clkdiv = 4 - 1;
CGU_DBOP |= (1<<3) /* clk enable */ | clkdiv /* clkdiv: 3 bits */ ;
CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */
GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */

3
firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
View file

@ -31,6 +31,7 @@
#include "system.h"
#include "font.h"
#include "bidi.h"
#include "clock-target.h"
static bool display_on = false; /* is the display turned on? */
static bool display_flipped = false;
@ -94,7 +95,7 @@ static void lcd_delay(int x)
/* DBOP initialisation, do what OF does */
static void ams3525_dbop_init(void)
{
CGU_DBOP = (1<<3) | (3-1);
CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e;

4
firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
View file

@ -24,6 +24,7 @@
#include "cpu.h"
#include "lcd.h"
#include "clock-target.h"
/* The controller is unknown, but some registers appear to be the same as the
HD66789R */
@ -49,7 +50,8 @@ static void lcd_delay(int x)
static void as3525_dbop_init(void)
{
CGU_DBOP = (1<<3);
CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e;
DBOP_CTRL = 0x41008;

32
firmware/target/arm/as3525/system-as3525.c
View file

@ -25,6 +25,7 @@
#include "panic.h"
#include "ascodec-target.h"
#include "dma-target.h"
#include "clock-target.h"
#define default_interrupt(name) \
extern __attribute__((weak,alias("UIRQ"))) void name (void)
@ -135,9 +136,6 @@ static void sdram_delay(void)
/* Use the same initialization than OF */
static void sdram_init(void)
{
CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */
CGU_PERI |= (1<<2); /* divider = 2 */
CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */
MPMC_CONTROL = 0x1; /* enable MPMC */
@ -201,11 +199,8 @@ static void sdram_init(void)
void system_init(void)
{
#ifdef BOOTLOADER
#if 0 /* the GPIO clock is already enabled by the dualboot function */
CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
#endif
#ifdef BOOTLOADER /* TODO: makes this work in the main build */
CGU_PROC = 0; /* fclk 24 MHz */
CGU_PERI &= ~0x7f; /* pclk 24 MHz */
@ -215,10 +210,13 @@ void system_init(void)
"mcr p15, 0, r0, c1, c0 \n"
: : : "r0" );
CGU_PLLA = 0x261F; /* PLLA 248 MHz */
CGU_PLLA = AS3525_PLLA_SETTING;
while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
CGU_PROC = 1; /* fclk = PLLA = 248 MHz */
CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1;
CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
| 1; /* clk_in = PLLA */
asm volatile(
"mov r0, #0 \n"
@ -230,26 +228,32 @@ void system_init(void)
: : : "r0" );
sdram_init();
#endif /* BOOTLOADER */
#if 0 /* the GPIO clock is already enabled by the dualboot function */
CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
#endif
/* enable timer interface for TIMER1 & TIMER2 */
CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
/* enable VIC */
VIC_INT_ENABLE = 0; /* disable all interrupt lines */
VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
CGU_PERI |= CGU_VIC_CLOCK_ENABLE;
VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
#else
dma_init();
#ifndef BOOTLOADER
/* Disable fast hardware power-off, to use power button normally
* We don't need the power button in the bootloader. */
ascodec_init();
ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2));
#endif /* BOOTLOADER */
#endif /* !BOOTLOADER */
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
set_cpu_frequency(CPUFREQ_DEFAULT);
#endif
dma_init();
}
void system_reboot(void)

4
firmware/target/arm/as3525/system-target.h
View file

@ -23,8 +23,6 @@
#include "system-arm.h"
#define CPUFREQ_MAX 248000000
#define CPUFREQ_DEFAULT 24800000
#define CPUFREQ_NORMAL 31000000
#include "clock-target.h" /* CPUFREQ_* are defined here */
#endif /* SYSTEM_TARGET_H */

3
firmware/target/arm/lcd-ssd1815.c
View file

@ -71,6 +71,7 @@
#if CONFIG_CPU == AS3525
#include "as3525.h"
#include "clock-target.h"
void lcd_write_command(int byte)
{
@ -102,7 +103,7 @@ void lcd_write_data(const fb_data* p_bytes, int count)
static inline void ams3525_dbop_init(void)
{
CGU_DBOP |= (1<<3) /* clk enable */ | (3 - 1) /* clkdiv: 3 bits */ ;
CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
GPIOB_AFSEL = 0x0f; /* DBOP on pin 3:0 */
GPIOC_AFSEL = 0xff; /* DBOP on pins 7:0 */