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imx233: rework frequency scaling
Move to a table based approach (scales better) and distinguish between upward changes (increase frequency) and downward changes (decrease frequency). This provides a better ordering of operations and in particular it allows to avoid changing the regulator while running at low speed since it takes a long time ! This should result in a much smoother scaling. Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
This commit is contained in:
Amaury Pouly
parent
29e51a1777
commit
4307f95a1f
1 changed files with 71 additions and 69 deletions
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@ -128,6 +128,8 @@ void system_init(void)
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imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8);
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imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8);
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imx233_clkctrl_enable_auto_slow(true);
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imx233_clkctrl_enable_auto_slow(true);
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cpu_frequency = imx233_clkctrl_get_clock_freq(CLK_CPU);
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#if !defined(BOOTLOADER) &&(defined(SANSA_FUZEPLUS) || \
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#if !defined(BOOTLOADER) &&(defined(SANSA_FUZEPLUS) || \
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defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
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defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
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fmradio_i2c_init();
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fmradio_i2c_init();
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@ -174,88 +176,88 @@ void imx233_digctl_set_arm_cache_timings(unsigned timings)
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}
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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struct cpufreq_profile_t
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{
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/* key */
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long cpu_freq;
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/* parameters */
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int vddd, vddd_bo;
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int hbus_div;
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int cpu_idiv, cpu_fdiv;
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long emi_freq;
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int arm_cache_timings;
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};
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static struct cpufreq_profile_t cpu_profiles[] =
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{
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/* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */
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{IMX233_CPUFREQ_454_MHz, 1550, 1450, 3, 1, 19, IMX233_EMIFREQ_130_MHz, 0},
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/* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */
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{IMX233_CPUFREQ_261_MHz, 1275, 1175, 2, 1, 33, IMX233_EMIFREQ_130_MHz, 0},
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/* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz */
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{IMX233_CPUFREQ_64_MHz, 1050, 975, 1, 5, 27, IMX233_EMIFREQ_64_MHz, 0},
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/* dummy */
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{0, 0, 0, 0, 0, 0, 0, 0}
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};
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#define NR_CPU_PROFILES ((int)(sizeof(cpu_profiles)/sizeof(cpu_profiles[0])))
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void set_cpu_frequency(long frequency)
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void set_cpu_frequency(long frequency)
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{
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{
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/* don't change the frequency if it is useless (changes are expensive) */
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/* don't change the frequency if it is useless (changes are expensive) */
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if(cpu_frequency == frequency)
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if(cpu_frequency == frequency)
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return;
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return;
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cpu_frequency = frequency;
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struct cpufreq_profile_t *prof = cpu_profiles;
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while(prof->cpu_freq != 0 && prof->cpu_freq != frequency)
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prof++;
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if(prof->cpu_freq == 0)
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return;
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/* disable auto-slow (enable back afterwards) */
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/* disable auto-slow (enable back afterwards) */
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bool as = imx233_clkctrl_is_auto_slow_enabled();
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bool as = imx233_clkctrl_is_auto_slow_enabled();
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imx233_clkctrl_enable_auto_slow(false);
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imx233_clkctrl_enable_auto_slow(false);
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/* go back to a known state in safe way:
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* clk_p@24 MHz
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* clk_h@6 MHz
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* WARNING: we must absolutely avoid that clk_h be too low or too high
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* during the change. We first change the clk_p/clk_h ratio to 4 so
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* that it cannot be too high (480/4=120 MHz max) or too low
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* (24/4=6 MHz min). Then we switch clk_p to bypass. We chose a ratio of 4
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* which is greater than all clk_p/clk_h ratios used below so that further
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* changes are safe too */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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imx233_digctl_set_arm_cache_timings(0);
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switch(frequency)
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/* WARNING watch out the order ! */
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if(frequency > cpu_frequency)
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{
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{
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case IMX233_CPUFREQ_454_MHz:
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/* Change VDDD regulator */
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/* set VDDD to 1.550 mV (brownout at 1.450 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
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imx233_power_set_regulator(REGULATOR_VDDD, 1550, 1450);
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/* Change ARM cache timings */
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/* clk_h@clk_p/3 */
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imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 3);
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/* Switch CPU to crystal at 24MHz */
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/* clk_p@ref_cpu/1*18/19 */
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 19);
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/* Program CPU divider for PLL */
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv);
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/* Change the HBUS divider to its final value */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div);
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/* Switch back CPU to PLL */
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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/* Set the new EMI frequency */
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imx233_emi_set_frequency(IMX233_EMIFREQ_130_MHz);
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imx233_emi_set_frequency(prof->emi_freq);
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/* ref_cpu@480 MHz
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}
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* ref_emi@480 MHz
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else
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* clk_emi@130.91 MHz
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{
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* clk_p@454.74 MHz
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/* Switch CPU to crystal at 24MHz */
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* clk_h@130.91 MHz */
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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break;
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/* Program HBUS divider to its final value */
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case IMX233_CPUFREQ_261_MHz:
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, prof->hbus_div);
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/* set VDDD to 1.275 mV (brownout at 1.175 mV) */
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/* Program CPU divider for PLL */
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imx233_power_set_regulator(REGULATOR_VDDD, 1275, 1175);
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, prof->cpu_fdiv);
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/* clk_h@clk_p/2 */
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imx233_clkctrl_set_clock_divisor(CLK_CPU, prof->cpu_idiv);
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 2);
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/* Switch back CPU to PLL */
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/* clk_p@ref_cpu/1*18/33 */
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 33);
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/* Set the new EMI frequency */
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_emi_set_frequency(prof->emi_freq);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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/* Change ARM cache timings */
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imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
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imx233_emi_set_frequency(IMX233_EMIFREQ_130_MHz);
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/* Change VDDD regulator */
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/* ref_cpu@480 MHz
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imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
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* ref_emi@480 MHz
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* clk_emi@130.91 MHz
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* clk_p@261.82 MHz
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* clk_h@130.91 MHz */
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break;
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case IMX233_CPUFREQ_64_MHz:
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/* set VDDD to 1.050 mV (brownout at 0.975 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1050, 975);
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/* clk_h@clk_p */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 1);
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/* clk_p@ref_cpu/5*18/27 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 27);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 5);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz);
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imx233_digctl_set_arm_cache_timings(3);
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/* ref_cpu@480 MHz
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* ref_emi@480 MHz
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* clk_emi@64 MHz
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* clk_p@64 MHz
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* clk_h@64 MHz */
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default:
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break;
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}
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}
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/* enable auto slow again */
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/* enable auto slow again */
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imx233_clkctrl_enable_auto_slow(as);
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imx233_clkctrl_enable_auto_slow(as);
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/* update frequency */
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cpu_frequency = frequency;
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}
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}
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#endif
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#endif
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