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x1000: simplify NAND command macros

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There is actually no need to parameterize most commands with row
or column cycles, usually the opcode and row/column address width
are linked. When this is not the case we can use raw SFC commands
or define new macros.

Change-Id: I22459d732dc01012e6a8ae026c4fb85495d372b4
This commit is contained in:
Aidan MacDonald 2022-07-11 21:08:40 +01:00
parent 9ab5d311cb
commit 4101aeac54
3 changed files with 22 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

10
bootloader/x1000/utils.c
View file

@ -375,22 +375,22 @@ static void probe_flash(int log_fd)
mdelay(10);
/* Try various read ID commands (cf. Linux's SPI NAND identify routine) */
sfc_exec(NANDCMD_READID(0, 0), 0, buffer, readid_len|SFC_READ);
sfc_exec(NANDCMD_READID_OPCODE, 0, buffer, readid_len|SFC_READ);
fdprintf(log_fd, "readID opcode = %02x %02x %02x %02x\n",
buffer[0], buffer[1], buffer[2], buffer[3]);
sfc_exec(NANDCMD_READID(1, 0), 0, buffer, readid_len|SFC_READ);
sfc_exec(NANDCMD_READID_ADDR, 0, buffer, readid_len|SFC_READ);
fdprintf(log_fd, "readID address = %02x %02x %02x %02x\n",
buffer[0], buffer[1], buffer[2], buffer[3]);
sfc_exec(NANDCMD_READID(0, 8), 0, buffer, readid_len|SFC_READ);
sfc_exec(NANDCMD_READID_DUMMY, 0, buffer, readid_len|SFC_READ);
fdprintf(log_fd, "readID dummy = %02x %02x %02x %02x\n",
buffer[0], buffer[1], buffer[2], buffer[3]);
/* Try reading Ingenic SFC boot block */
sfc_exec(NANDCMD_PAGE_READ(3), 0, NULL, 0);
sfc_exec(NANDCMD_PAGE_READ, 0, NULL, 0);
mdelay(500);
sfc_exec(NANDCMD_READ_CACHE_SLOW(2), 0, buffer, 16|SFC_READ);
sfc_exec(NANDCMD_READ_CACHE_SLOW, 0, buffer, 16|SFC_READ);
fdprintf(log_fd, "sfc params0 = %02x %02x %02x %02x\n",
buffer[ 0], buffer[ 1], buffer[ 2], buffer[ 3]);

12
firmware/target/mips/ingenic_x1000/nand-x1000.c
View file

@ -44,11 +44,11 @@ const struct nand_chip supported_nand_chips[] = {
STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS),
SMP_DELAY(1)),
.flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT,
.cmd_page_read = NANDCMD_PAGE_READ(3),
.cmd_program_execute = NANDCMD_PROGRAM_EXECUTE(3),
.cmd_block_erase = NANDCMD_BLOCK_ERASE(3),
.cmd_read_cache = NANDCMD_READ_CACHE_x4(2),
.cmd_program_load = NANDCMD_PROGRAM_LOAD_x4(2),
.cmd_page_read = NANDCMD_PAGE_READ,
.cmd_program_execute = NANDCMD_PROGRAM_EXECUTE,
.cmd_block_erase = NANDCMD_BLOCK_ERASE,
.cmd_read_cache = NANDCMD_READ_CACHE_x4,
.cmd_program_load = NANDCMD_PROGRAM_LOAD_x4,
},
#else
{ 0 },
@ -103,7 +103,7 @@ static bool identify_chip(struct nand_drv* drv)
*
* Currently we use the 2nd method, aka. address read ID.
*/
sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 4|SFC_READ);
sfc_exec(NANDCMD_READID_ADDR, 0, drv->scratch_buf, 4|SFC_READ);
drv->mf_id = drv->scratch_buf[0];
drv->dev_id = drv->scratch_buf[1];
drv->dev_id2 = drv->scratch_buf[2];

20
firmware/target/mips/ingenic_x1000/nand-x1000.h
View file

@ -49,18 +49,20 @@
/* cmd mode a d phase format has data */
#define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_READID(x,y) SFC_CMD(0x9f, SFC_TMODE_1_1_1, x, y, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READID_OPCODE SFC_CMD(0x9f, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READID_ADDR SFC_CMD(0x9f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READID_DUMMY SFC_CMD(0x9f, SFC_TMODE_1_1_1, 0, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_WR_EN SFC_CMD(0x06, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_GET_FEATURE SFC_CMD(0x0f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_SET_FEATURE SFC_CMD(0x1f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PAGE_READ(x) SFC_CMD(0x13, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_READ_CACHE_SLOW(x) SFC_CMD(0x03, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READ_CACHE(x) SFC_CMD(0x0b, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READ_CACHE_x4(x) SFC_CMD(0x6b, SFC_TMODE_1_1_4, x, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PROGRAM_LOAD(x) SFC_CMD(0x02, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PROGRAM_LOAD_x4(x) SFC_CMD(0x32, SFC_TMODE_1_1_4, x, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PROGRAM_EXECUTE(x) SFC_CMD(0x10, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_BLOCK_ERASE(x) SFC_CMD(0xd8, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_PAGE_READ SFC_CMD(0x13, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_READ_CACHE_SLOW SFC_CMD(0x03, SFC_TMODE_1_1_1, 2, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READ_CACHE SFC_CMD(0x0b, SFC_TMODE_1_1_1, 2, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_READ_CACHE_x4 SFC_CMD(0x6b, SFC_TMODE_1_1_4, 2, 8, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PROGRAM_EXECUTE SFC_CMD(0x10, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0)
#define NANDCMD_PROGRAM_LOAD SFC_CMD(0x02, SFC_TMODE_1_1_1, 2, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_PROGRAM_LOAD_x4 SFC_CMD(0x32, SFC_TMODE_1_1_4, 2, 0, SFC_PFMT_ADDR_FIRST, 1)
#define NANDCMD_BLOCK_ERASE SFC_CMD(0xd8, SFC_TMODE_1_1_1, 3, 0, SFC_PFMT_ADDR_FIRST, 0)
/* Feature registers are found in linux/mtd/spinand.h,
* apparently these are pretty standardized */