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Meizu M6SP: initialise and use SDRAM
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23544 a1c6a512-1295-4272-9138-f99709370657
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b6cd045767
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2 changed files with 66 additions and 5 deletions
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@ -104,7 +104,7 @@ SECTIONS
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*(COMMON);
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*(COMMON);
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. = ALIGN(0x4);
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. = ALIGN(0x4);
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_end = .;
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_end = .;
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#ifdef IPOD_NANO2G
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#if defined(IPOD_NANO2G) || defined(MEIZU_M6SP)
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} > DRAM
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} > DRAM
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#else /* other targets don't have DRAM set up yet */
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#else /* other targets don't have DRAM set up yet */
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} > IRAM
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} > IRAM
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@ -107,7 +107,7 @@ start_loc:
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#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
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#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
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ldr r1, =0x3c500000
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ldr r1, =0x3c500000
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ldr r0, =0x00800080
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ldr r0, =0x00800080
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str r0, [r1] // CLKCON
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str r0, [r1] // CLKCON
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mov r0, #0
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mov r0, #0
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str r0, [r1,#0x24] // PLLCON
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str r0, [r1,#0x24] // PLLCON
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#ifdef IPOD_NANO2G
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#ifdef IPOD_NANO2G
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@ -236,6 +236,67 @@ start_loc:
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mov r0, #0 // 0x0
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mov r0, #0 // 0x0
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str r0, [r1, #44] // do not enter any power saving mode
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str r0, [r1, #44] // do not enter any power saving mode
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#ifdef MEIZU_M6SP
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/* setup SDRAM for Meizu M6SP */
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ldr r1, =0x38200000
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// configure SDR drive strength and pad settings
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mov r0, #5
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str r0, [r1, #0x4C] // MIU_DSS_SEL_B
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mov r0, #2
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str r0, [r1, #0x50] // MIU_DSS_SEL_O
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str r0, [r1, #0x54] // MIU_DSS_SEL_C
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mov r0, #2
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str r0, [r1, #0x60] // SSTL2_PAD_ON
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// select SDR mode
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ldr r0, [r1, #0x40]
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mov r2, #0xFFFDFFFF
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and r0, r0, r2
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orr r0, r0, #1
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str r0, [r1, #0x40] // MIUORG
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// set controller configuration
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mov r0, #0x700
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str r0, [r1] // MIUCON
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// set SDRAM timing
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ldr r0, =0x6A4965
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str r0, [r1, #0x10] // MIUSDPARA
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// set refresh rate
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mov r0, #0x1080
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str r0, [r1, #0x08] // MIUAREF
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// initialise SDRAM
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mov r0, #0x003
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str r0, [r1, #0x04] // MIUCOM = nop
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ldr r0, =0x203
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str r0, [r1, #0x04] // MIUCOM = precharge all banks
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nop
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nop
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nop
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ldr r0, =0x303
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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// set mode register
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mov r0, #0x33
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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ldr r0, =0x4033
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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#endif /* MEIZU_M6SP */
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mov r1, #0x1
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mov r1, #0x1
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mrc 15, 0, r0, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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bic r0, r0, r1
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