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New port: FiiO M3K on bare metal

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Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
This commit is contained in:
Aidan MacDonald 2021-02-27 22:08:58 +00:00
parent 83fcbedc65
commit 3ec66893e3
143 changed files with 16585 additions and 24 deletions
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359
firmware/target/mips/ingenic_x1000/x1000/aic.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_AIC_H__
#define __HEADERGEN_AIC_H__
#include "macro.h"
#define REG_AIC_CFG jz_reg(AIC_CFG)
#define JA_AIC_CFG (0xb0020000 + 0x0)
#define JT_AIC_CFG JIO_32_RW
#define JN_AIC_CFG AIC_CFG
#define JI_AIC_CFG
#define BP_AIC_CFG_RFTH 24
#define BM_AIC_CFG_RFTH 0xf000000
#define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24)
#define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH
#define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e)
#define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH
#define BP_AIC_CFG_TFTH 16
#define BM_AIC_CFG_TFTH 0x1f0000
#define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16)
#define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH
#define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e)
#define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH
#define BP_AIC_CFG_MSB 12
#define BM_AIC_CFG_MSB 0x1000
#define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12)
#define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB
#define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e)
#define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB
#define BP_AIC_CFG_IBCKD 10
#define BM_AIC_CFG_IBCKD 0x400
#define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10)
#define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD
#define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e)
#define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD
#define BP_AIC_CFG_ISYNCD 9
#define BM_AIC_CFG_ISYNCD 0x200
#define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9)
#define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD
#define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e)
#define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD
#define BP_AIC_CFG_DMODE 8
#define BM_AIC_CFG_DMODE 0x100
#define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8)
#define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE
#define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e)
#define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE
#define BP_AIC_CFG_CDC_SLAVE 7
#define BM_AIC_CFG_CDC_SLAVE 0x80
#define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7)
#define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE
#define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e)
#define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE
#define BP_AIC_CFG_LSMP 6
#define BM_AIC_CFG_LSMP 0x40
#define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6)
#define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP
#define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e)
#define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP
#define BP_AIC_CFG_ICDC 5
#define BM_AIC_CFG_ICDC 0x20
#define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5)
#define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC
#define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e)
#define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC
#define BP_AIC_CFG_AUSEL 4
#define BM_AIC_CFG_AUSEL 0x10
#define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4)
#define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL
#define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e)
#define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL
#define BP_AIC_CFG_RST 3
#define BM_AIC_CFG_RST 0x8
#define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3)
#define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST
#define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e)
#define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST
#define BP_AIC_CFG_BCKD 2
#define BM_AIC_CFG_BCKD 0x4
#define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2)
#define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD
#define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e)
#define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD
#define BP_AIC_CFG_SYNCD 1
#define BM_AIC_CFG_SYNCD 0x2
#define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1)
#define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD
#define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e)
#define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD
#define BP_AIC_CFG_ENABLE 0
#define BM_AIC_CFG_ENABLE 0x1
#define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0)
#define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE
#define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e)
#define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE
#define REG_AIC_CCR jz_reg(AIC_CCR)
#define JA_AIC_CCR (0xb0020000 + 0x4)
#define JT_AIC_CCR JIO_32_RW
#define JN_AIC_CCR AIC_CCR
#define JI_AIC_CCR
#define BP_AIC_CCR_CHANNEL 24
#define BM_AIC_CCR_CHANNEL 0x7000000
#define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24)
#define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL
#define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e)
#define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL
#define BP_AIC_CCR_OSS 19
#define BM_AIC_CCR_OSS 0x380000
#define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19)
#define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS
#define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e)
#define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS
#define BP_AIC_CCR_ISS 16
#define BM_AIC_CCR_ISS 0x70000
#define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16)
#define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS
#define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e)
#define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS
#define BP_AIC_CCR_PACK16 28
#define BM_AIC_CCR_PACK16 0x10000000
#define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28)
#define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16
#define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e)
#define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16
#define BP_AIC_CCR_RDMS 15
#define BM_AIC_CCR_RDMS 0x8000
#define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15)
#define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS
#define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e)
#define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS
#define BP_AIC_CCR_TDMS 14
#define BM_AIC_CCR_TDMS 0x4000
#define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14)
#define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS
#define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e)
#define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS
#define BP_AIC_CCR_M2S 11
#define BM_AIC_CCR_M2S 0x800
#define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11)
#define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S
#define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e)
#define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S
#define BP_AIC_CCR_ENDSW 10
#define BM_AIC_CCR_ENDSW 0x400
#define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10)
#define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW
#define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e)
#define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW
#define BP_AIC_CCR_ASVTSU 9
#define BM_AIC_CCR_ASVTSU 0x200
#define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9)
#define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU
#define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e)
#define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU
#define BP_AIC_CCR_TFLUSH 8
#define BM_AIC_CCR_TFLUSH 0x100
#define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8)
#define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH
#define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e)
#define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH
#define BP_AIC_CCR_RFLUSH 7
#define BM_AIC_CCR_RFLUSH 0x80
#define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7)
#define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH
#define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e)
#define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH
#define BP_AIC_CCR_EROR 6
#define BM_AIC_CCR_EROR 0x40
#define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6)
#define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR
#define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e)
#define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR
#define BP_AIC_CCR_ETUR 5
#define BM_AIC_CCR_ETUR 0x20
#define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5)
#define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR
#define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e)
#define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR
#define BP_AIC_CCR_ERFS 4
#define BM_AIC_CCR_ERFS 0x10
#define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4)
#define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS
#define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e)
#define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS
#define BP_AIC_CCR_ETFS 3
#define BM_AIC_CCR_ETFS 0x8
#define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3)
#define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS
#define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e)
#define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS
#define BP_AIC_CCR_ENLBF 2
#define BM_AIC_CCR_ENLBF 0x4
#define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2)
#define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF
#define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e)
#define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF
#define BP_AIC_CCR_ERPL 1
#define BM_AIC_CCR_ERPL 0x2
#define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1)
#define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL
#define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e)
#define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL
#define BP_AIC_CCR_EREC 0
#define BM_AIC_CCR_EREC 0x1
#define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0)
#define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC
#define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e)
#define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC
#define REG_AIC_I2SCR jz_reg(AIC_I2SCR)
#define JA_AIC_I2SCR (0xb0020000 + 0x10)
#define JT_AIC_I2SCR JIO_32_RW
#define JN_AIC_I2SCR AIC_I2SCR
#define JI_AIC_I2SCR
#define BP_AIC_I2SCR_RFIRST 17
#define BM_AIC_I2SCR_RFIRST 0x20000
#define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17)
#define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST
#define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e)
#define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST
#define BP_AIC_I2SCR_SWLH 16
#define BM_AIC_I2SCR_SWLH 0x10000
#define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16)
#define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH
#define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e)
#define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH
#define BP_AIC_I2SCR_ISTPBK 13
#define BM_AIC_I2SCR_ISTPBK 0x2000
#define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13)
#define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK
#define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e)
#define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK
#define BP_AIC_I2SCR_STPBK 12
#define BM_AIC_I2SCR_STPBK 0x1000
#define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12)
#define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK
#define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e)
#define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK
#define BP_AIC_I2SCR_ESCLK 4
#define BM_AIC_I2SCR_ESCLK 0x10
#define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4)
#define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK
#define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e)
#define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK
#define BP_AIC_I2SCR_AMSL 0
#define BM_AIC_I2SCR_AMSL 0x1
#define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0)
#define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL
#define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e)
#define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL
#define REG_AIC_SR jz_reg(AIC_SR)
#define JA_AIC_SR (0xb0020000 + 0x14)
#define JT_AIC_SR JIO_32_RW
#define JN_AIC_SR AIC_SR
#define JI_AIC_SR
#define BP_AIC_SR_RFL 24
#define BM_AIC_SR_RFL 0x3f000000
#define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24)
#define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL
#define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e)
#define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL
#define BP_AIC_SR_TFL 8
#define BM_AIC_SR_TFL 0x3f00
#define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8)
#define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL
#define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e)
#define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL
#define BP_AIC_SR_ROR 6
#define BM_AIC_SR_ROR 0x40
#define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6)
#define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR
#define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e)
#define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR
#define BP_AIC_SR_TUR 5
#define BM_AIC_SR_TUR 0x20
#define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5)
#define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR
#define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e)
#define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR
#define BP_AIC_SR_RFS 4
#define BM_AIC_SR_RFS 0x10
#define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4)
#define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS
#define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e)
#define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS
#define BP_AIC_SR_TFS 3
#define BM_AIC_SR_TFS 0x8
#define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3)
#define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS
#define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e)
#define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS
#define REG_AIC_I2SSR jz_reg(AIC_I2SSR)
#define JA_AIC_I2SSR (0xb0020000 + 0x1c)
#define JT_AIC_I2SSR JIO_32_RW
#define JN_AIC_I2SSR AIC_I2SSR
#define JI_AIC_I2SSR
#define BP_AIC_I2SSR_CHBSY 5
#define BM_AIC_I2SSR_CHBSY 0x20
#define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5)
#define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY
#define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e)
#define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY
#define BP_AIC_I2SSR_TBSY 4
#define BM_AIC_I2SSR_TBSY 0x10
#define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4)
#define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY
#define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e)
#define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY
#define BP_AIC_I2SSR_RBSY 3
#define BM_AIC_I2SSR_RBSY 0x8
#define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3)
#define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY
#define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e)
#define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY
#define BP_AIC_I2SSR_BSY 2
#define BM_AIC_I2SSR_BSY 0x4
#define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2)
#define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY
#define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e)
#define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY
#define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV)
#define JA_AIC_I2SDIV (0xb0020000 + 0x30)
#define JT_AIC_I2SDIV JIO_32_RW
#define JN_AIC_I2SDIV AIC_I2SDIV
#define JI_AIC_I2SDIV
#define REG_AIC_DR jz_reg(AIC_DR)
#define JA_AIC_DR (0xb0020000 + 0x34)
#define JT_AIC_DR JIO_32_RW
#define JN_AIC_DR AIC_DR
#define JI_AIC_DR
#endif /* __HEADERGEN_AIC_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_CPM_H__
#define __HEADERGEN_CPM_H__
#include "macro.h"
#define REG_CPM_CCR jz_reg(CPM_CCR)
#define JA_CPM_CCR (0xb0000000 + 0x0)
#define JT_CPM_CCR JIO_32_RW
#define JN_CPM_CCR CPM_CCR
#define JI_CPM_CCR
#define BP_CPM_CCR_SEL_SRC 30
#define BM_CPM_CCR_SEL_SRC 0xc0000000
#define BV_CPM_CCR_SEL_SRC__STOP 0x0
#define BV_CPM_CCR_SEL_SRC__EXCLK 0x1
#define BV_CPM_CCR_SEL_SRC__APLL 0x2
#define BF_CPM_CCR_SEL_SRC(v) (((v) & 0x3) << 30)
#define BFM_CPM_CCR_SEL_SRC(v) BM_CPM_CCR_SEL_SRC
#define BF_CPM_CCR_SEL_SRC_V(e) BF_CPM_CCR_SEL_SRC(BV_CPM_CCR_SEL_SRC__##e)
#define BFM_CPM_CCR_SEL_SRC_V(v) BM_CPM_CCR_SEL_SRC
#define BP_CPM_CCR_SEL_CPLL 28
#define BM_CPM_CCR_SEL_CPLL 0x30000000
#define BV_CPM_CCR_SEL_CPLL__STOP 0x0
#define BV_CPM_CCR_SEL_CPLL__SCLK_A 0x1
#define BV_CPM_CCR_SEL_CPLL__MPLL 0x2
#define BF_CPM_CCR_SEL_CPLL(v) (((v) & 0x3) << 28)
#define BFM_CPM_CCR_SEL_CPLL(v) BM_CPM_CCR_SEL_CPLL
#define BF_CPM_CCR_SEL_CPLL_V(e) BF_CPM_CCR_SEL_CPLL(BV_CPM_CCR_SEL_CPLL__##e)
#define BFM_CPM_CCR_SEL_CPLL_V(v) BM_CPM_CCR_SEL_CPLL
#define BP_CPM_CCR_SEL_H0PLL 26
#define BM_CPM_CCR_SEL_H0PLL 0xc000000
#define BV_CPM_CCR_SEL_H0PLL__STOP 0x0
#define BV_CPM_CCR_SEL_H0PLL__SCLK_A 0x1
#define BV_CPM_CCR_SEL_H0PLL__MPLL 0x2
#define BF_CPM_CCR_SEL_H0PLL(v) (((v) & 0x3) << 26)
#define BFM_CPM_CCR_SEL_H0PLL(v) BM_CPM_CCR_SEL_H0PLL
#define BF_CPM_CCR_SEL_H0PLL_V(e) BF_CPM_CCR_SEL_H0PLL(BV_CPM_CCR_SEL_H0PLL__##e)
#define BFM_CPM_CCR_SEL_H0PLL_V(v) BM_CPM_CCR_SEL_H0PLL
#define BP_CPM_CCR_SEL_H2PLL 24
#define BM_CPM_CCR_SEL_H2PLL 0x3000000
#define BV_CPM_CCR_SEL_H2PLL__STOP 0x0
#define BV_CPM_CCR_SEL_H2PLL__SCLK_A 0x1
#define BV_CPM_CCR_SEL_H2PLL__MPLL 0x2
#define BF_CPM_CCR_SEL_H2PLL(v) (((v) & 0x3) << 24)
#define BFM_CPM_CCR_SEL_H2PLL(v) BM_CPM_CCR_SEL_H2PLL
#define BF_CPM_CCR_SEL_H2PLL_V(e) BF_CPM_CCR_SEL_H2PLL(BV_CPM_CCR_SEL_H2PLL__##e)
#define BFM_CPM_CCR_SEL_H2PLL_V(v) BM_CPM_CCR_SEL_H2PLL
#define BP_CPM_CCR_PDIV 16
#define BM_CPM_CCR_PDIV 0xf0000
#define BF_CPM_CCR_PDIV(v) (((v) & 0xf) << 16)
#define BFM_CPM_CCR_PDIV(v) BM_CPM_CCR_PDIV
#define BF_CPM_CCR_PDIV_V(e) BF_CPM_CCR_PDIV(BV_CPM_CCR_PDIV__##e)
#define BFM_CPM_CCR_PDIV_V(v) BM_CPM_CCR_PDIV
#define BP_CPM_CCR_H2DIV 12
#define BM_CPM_CCR_H2DIV 0xf000
#define BF_CPM_CCR_H2DIV(v) (((v) & 0xf) << 12)
#define BFM_CPM_CCR_H2DIV(v) BM_CPM_CCR_H2DIV
#define BF_CPM_CCR_H2DIV_V(e) BF_CPM_CCR_H2DIV(BV_CPM_CCR_H2DIV__##e)
#define BFM_CPM_CCR_H2DIV_V(v) BM_CPM_CCR_H2DIV
#define BP_CPM_CCR_H0DIV 8
#define BM_CPM_CCR_H0DIV 0xf00
#define BF_CPM_CCR_H0DIV(v) (((v) & 0xf) << 8)
#define BFM_CPM_CCR_H0DIV(v) BM_CPM_CCR_H0DIV
#define BF_CPM_CCR_H0DIV_V(e) BF_CPM_CCR_H0DIV(BV_CPM_CCR_H0DIV__##e)
#define BFM_CPM_CCR_H0DIV_V(v) BM_CPM_CCR_H0DIV
#define BP_CPM_CCR_L2DIV 4
#define BM_CPM_CCR_L2DIV 0xf0
#define BF_CPM_CCR_L2DIV(v) (((v) & 0xf) << 4)
#define BFM_CPM_CCR_L2DIV(v) BM_CPM_CCR_L2DIV
#define BF_CPM_CCR_L2DIV_V(e) BF_CPM_CCR_L2DIV(BV_CPM_CCR_L2DIV__##e)
#define BFM_CPM_CCR_L2DIV_V(v) BM_CPM_CCR_L2DIV
#define BP_CPM_CCR_CDIV 0
#define BM_CPM_CCR_CDIV 0xf
#define BF_CPM_CCR_CDIV(v) (((v) & 0xf) << 0)
#define BFM_CPM_CCR_CDIV(v) BM_CPM_CCR_CDIV
#define BF_CPM_CCR_CDIV_V(e) BF_CPM_CCR_CDIV(BV_CPM_CCR_CDIV__##e)
#define BFM_CPM_CCR_CDIV_V(v) BM_CPM_CCR_CDIV
#define BP_CPM_CCR_GATE_SCLKA 23
#define BM_CPM_CCR_GATE_SCLKA 0x800000
#define BF_CPM_CCR_GATE_SCLKA(v) (((v) & 0x1) << 23)
#define BFM_CPM_CCR_GATE_SCLKA(v) BM_CPM_CCR_GATE_SCLKA
#define BF_CPM_CCR_GATE_SCLKA_V(e) BF_CPM_CCR_GATE_SCLKA(BV_CPM_CCR_GATE_SCLKA__##e)
#define BFM_CPM_CCR_GATE_SCLKA_V(v) BM_CPM_CCR_GATE_SCLKA
#define BP_CPM_CCR_CE_CPU 22
#define BM_CPM_CCR_CE_CPU 0x400000
#define BF_CPM_CCR_CE_CPU(v) (((v) & 0x1) << 22)
#define BFM_CPM_CCR_CE_CPU(v) BM_CPM_CCR_CE_CPU
#define BF_CPM_CCR_CE_CPU_V(e) BF_CPM_CCR_CE_CPU(BV_CPM_CCR_CE_CPU__##e)
#define BFM_CPM_CCR_CE_CPU_V(v) BM_CPM_CCR_CE_CPU
#define BP_CPM_CCR_CE_AHB0 21
#define BM_CPM_CCR_CE_AHB0 0x200000
#define BF_CPM_CCR_CE_AHB0(v) (((v) & 0x1) << 21)
#define BFM_CPM_CCR_CE_AHB0(v) BM_CPM_CCR_CE_AHB0
#define BF_CPM_CCR_CE_AHB0_V(e) BF_CPM_CCR_CE_AHB0(BV_CPM_CCR_CE_AHB0__##e)
#define BFM_CPM_CCR_CE_AHB0_V(v) BM_CPM_CCR_CE_AHB0
#define BP_CPM_CCR_CE_AHB2 20
#define BM_CPM_CCR_CE_AHB2 0x100000
#define BF_CPM_CCR_CE_AHB2(v) (((v) & 0x1) << 20)
#define BFM_CPM_CCR_CE_AHB2(v) BM_CPM_CCR_CE_AHB2
#define BF_CPM_CCR_CE_AHB2_V(e) BF_CPM_CCR_CE_AHB2(BV_CPM_CCR_CE_AHB2__##e)
#define BFM_CPM_CCR_CE_AHB2_V(v) BM_CPM_CCR_CE_AHB2
#define REG_CPM_CSR jz_reg(CPM_CSR)
#define JA_CPM_CSR (0xb0000000 + 0xd4)
#define JT_CPM_CSR JIO_32_RW
#define JN_CPM_CSR CPM_CSR
#define JI_CPM_CSR
#define BP_CPM_CSR_SRC_MUX 31
#define BM_CPM_CSR_SRC_MUX 0x80000000
#define BF_CPM_CSR_SRC_MUX(v) (((v) & 0x1) << 31)
#define BFM_CPM_CSR_SRC_MUX(v) BM_CPM_CSR_SRC_MUX
#define BF_CPM_CSR_SRC_MUX_V(e) BF_CPM_CSR_SRC_MUX(BV_CPM_CSR_SRC_MUX__##e)
#define BFM_CPM_CSR_SRC_MUX_V(v) BM_CPM_CSR_SRC_MUX
#define BP_CPM_CSR_CPU_MUX 30
#define BM_CPM_CSR_CPU_MUX 0x40000000
#define BF_CPM_CSR_CPU_MUX(v) (((v) & 0x1) << 30)
#define BFM_CPM_CSR_CPU_MUX(v) BM_CPM_CSR_CPU_MUX
#define BF_CPM_CSR_CPU_MUX_V(e) BF_CPM_CSR_CPU_MUX(BV_CPM_CSR_CPU_MUX__##e)
#define BFM_CPM_CSR_CPU_MUX_V(v) BM_CPM_CSR_CPU_MUX
#define BP_CPM_CSR_AHB0_MUX 29
#define BM_CPM_CSR_AHB0_MUX 0x20000000
#define BF_CPM_CSR_AHB0_MUX(v) (((v) & 0x1) << 29)
#define BFM_CPM_CSR_AHB0_MUX(v) BM_CPM_CSR_AHB0_MUX
#define BF_CPM_CSR_AHB0_MUX_V(e) BF_CPM_CSR_AHB0_MUX(BV_CPM_CSR_AHB0_MUX__##e)
#define BFM_CPM_CSR_AHB0_MUX_V(v) BM_CPM_CSR_AHB0_MUX
#define BP_CPM_CSR_AHB2_MUX 28
#define BM_CPM_CSR_AHB2_MUX 0x10000000
#define BF_CPM_CSR_AHB2_MUX(v) (((v) & 0x1) << 28)
#define BFM_CPM_CSR_AHB2_MUX(v) BM_CPM_CSR_AHB2_MUX
#define BF_CPM_CSR_AHB2_MUX_V(e) BF_CPM_CSR_AHB2_MUX(BV_CPM_CSR_AHB2_MUX__##e)
#define BFM_CPM_CSR_AHB2_MUX_V(v) BM_CPM_CSR_AHB2_MUX
#define BP_CPM_CSR_DDR_MUX 27
#define BM_CPM_CSR_DDR_MUX 0x8000000
#define BF_CPM_CSR_DDR_MUX(v) (((v) & 0x1) << 27)
#define BFM_CPM_CSR_DDR_MUX(v) BM_CPM_CSR_DDR_MUX
#define BF_CPM_CSR_DDR_MUX_V(e) BF_CPM_CSR_DDR_MUX(BV_CPM_CSR_DDR_MUX__##e)
#define BFM_CPM_CSR_DDR_MUX_V(v) BM_CPM_CSR_DDR_MUX
#define BP_CPM_CSR_H2DIV_BUSY 2
#define BM_CPM_CSR_H2DIV_BUSY 0x4
#define BF_CPM_CSR_H2DIV_BUSY(v) (((v) & 0x1) << 2)
#define BFM_CPM_CSR_H2DIV_BUSY(v) BM_CPM_CSR_H2DIV_BUSY
#define BF_CPM_CSR_H2DIV_BUSY_V(e) BF_CPM_CSR_H2DIV_BUSY(BV_CPM_CSR_H2DIV_BUSY__##e)
#define BFM_CPM_CSR_H2DIV_BUSY_V(v) BM_CPM_CSR_H2DIV_BUSY
#define BP_CPM_CSR_H0DIV_BUSY 1
#define BM_CPM_CSR_H0DIV_BUSY 0x2
#define BF_CPM_CSR_H0DIV_BUSY(v) (((v) & 0x1) << 1)
#define BFM_CPM_CSR_H0DIV_BUSY(v) BM_CPM_CSR_H0DIV_BUSY
#define BF_CPM_CSR_H0DIV_BUSY_V(e) BF_CPM_CSR_H0DIV_BUSY(BV_CPM_CSR_H0DIV_BUSY__##e)
#define BFM_CPM_CSR_H0DIV_BUSY_V(v) BM_CPM_CSR_H0DIV_BUSY
#define BP_CPM_CSR_CDIV_BUSY 0
#define BM_CPM_CSR_CDIV_BUSY 0x1
#define BF_CPM_CSR_CDIV_BUSY(v) (((v) & 0x1) << 0)
#define BFM_CPM_CSR_CDIV_BUSY(v) BM_CPM_CSR_CDIV_BUSY
#define BF_CPM_CSR_CDIV_BUSY_V(e) BF_CPM_CSR_CDIV_BUSY(BV_CPM_CSR_CDIV_BUSY__##e)
#define BFM_CPM_CSR_CDIV_BUSY_V(v) BM_CPM_CSR_CDIV_BUSY
#define REG_CPM_DDRCDR jz_reg(CPM_DDRCDR)
#define JA_CPM_DDRCDR (0xb0000000 + 0x2c)
#define JT_CPM_DDRCDR JIO_32_RW
#define JN_CPM_DDRCDR CPM_DDRCDR
#define JI_CPM_DDRCDR
#define BP_CPM_DDRCDR_CLKSRC 30
#define BM_CPM_DDRCDR_CLKSRC 0xc0000000
#define BV_CPM_DDRCDR_CLKSRC__STOP 0x0
#define BV_CPM_DDRCDR_CLKSRC__SCLK_A 0x1
#define BV_CPM_DDRCDR_CLKSRC__MPLL 0x2
#define BF_CPM_DDRCDR_CLKSRC(v) (((v) & 0x3) << 30)
#define BFM_CPM_DDRCDR_CLKSRC(v) BM_CPM_DDRCDR_CLKSRC
#define BF_CPM_DDRCDR_CLKSRC_V(e) BF_CPM_DDRCDR_CLKSRC(BV_CPM_DDRCDR_CLKSRC__##e)
#define BFM_CPM_DDRCDR_CLKSRC_V(v) BM_CPM_DDRCDR_CLKSRC
#define BP_CPM_DDRCDR_CLKDIV 0
#define BM_CPM_DDRCDR_CLKDIV 0xf
#define BF_CPM_DDRCDR_CLKDIV(v) (((v) & 0xf) << 0)
#define BFM_CPM_DDRCDR_CLKDIV(v) BM_CPM_DDRCDR_CLKDIV
#define BF_CPM_DDRCDR_CLKDIV_V(e) BF_CPM_DDRCDR_CLKDIV(BV_CPM_DDRCDR_CLKDIV__##e)
#define BFM_CPM_DDRCDR_CLKDIV_V(v) BM_CPM_DDRCDR_CLKDIV
#define BP_CPM_DDRCDR_CE 29
#define BM_CPM_DDRCDR_CE 0x20000000
#define BF_CPM_DDRCDR_CE(v) (((v) & 0x1) << 29)
#define BFM_CPM_DDRCDR_CE(v) BM_CPM_DDRCDR_CE
#define BF_CPM_DDRCDR_CE_V(e) BF_CPM_DDRCDR_CE(BV_CPM_DDRCDR_CE__##e)
#define BFM_CPM_DDRCDR_CE_V(v) BM_CPM_DDRCDR_CE
#define BP_CPM_DDRCDR_BUSY 28
#define BM_CPM_DDRCDR_BUSY 0x10000000
#define BF_CPM_DDRCDR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CPM_DDRCDR_BUSY(v) BM_CPM_DDRCDR_BUSY
#define BF_CPM_DDRCDR_BUSY_V(e) BF_CPM_DDRCDR_BUSY(BV_CPM_DDRCDR_BUSY__##e)
#define BFM_CPM_DDRCDR_BUSY_V(v) BM_CPM_DDRCDR_BUSY
#define BP_CPM_DDRCDR_STOP 27
#define BM_CPM_DDRCDR_STOP 0x8000000
#define BF_CPM_DDRCDR_STOP(v) (((v) & 0x1) << 27)
#define BFM_CPM_DDRCDR_STOP(v) BM_CPM_DDRCDR_STOP
#define BF_CPM_DDRCDR_STOP_V(e) BF_CPM_DDRCDR_STOP(BV_CPM_DDRCDR_STOP__##e)
#define BFM_CPM_DDRCDR_STOP_V(v) BM_CPM_DDRCDR_STOP
#define BP_CPM_DDRCDR_GATE_EN 26
#define BM_CPM_DDRCDR_GATE_EN 0x4000000
#define BF_CPM_DDRCDR_GATE_EN(v) (((v) & 0x1) << 26)
#define BFM_CPM_DDRCDR_GATE_EN(v) BM_CPM_DDRCDR_GATE_EN
#define BF_CPM_DDRCDR_GATE_EN_V(e) BF_CPM_DDRCDR_GATE_EN(BV_CPM_DDRCDR_GATE_EN__##e)
#define BFM_CPM_DDRCDR_GATE_EN_V(v) BM_CPM_DDRCDR_GATE_EN
#define BP_CPM_DDRCDR_CHANGE_EN 25
#define BM_CPM_DDRCDR_CHANGE_EN 0x2000000
#define BF_CPM_DDRCDR_CHANGE_EN(v) (((v) & 0x1) << 25)
#define BFM_CPM_DDRCDR_CHANGE_EN(v) BM_CPM_DDRCDR_CHANGE_EN
#define BF_CPM_DDRCDR_CHANGE_EN_V(e) BF_CPM_DDRCDR_CHANGE_EN(BV_CPM_DDRCDR_CHANGE_EN__##e)
#define BFM_CPM_DDRCDR_CHANGE_EN_V(v) BM_CPM_DDRCDR_CHANGE_EN
#define BP_CPM_DDRCDR_FLAG 24
#define BM_CPM_DDRCDR_FLAG 0x1000000
#define BF_CPM_DDRCDR_FLAG(v) (((v) & 0x1) << 24)
#define BFM_CPM_DDRCDR_FLAG(v) BM_CPM_DDRCDR_FLAG
#define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e)
#define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG
#define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR)
#define JA_CPM_I2SCDR (0xb0000000 + 0x60)
#define JT_CPM_I2SCDR JIO_32_RW
#define JN_CPM_I2SCDR CPM_I2SCDR
#define JI_CPM_I2SCDR
#define BP_CPM_I2SCDR_DIV_M 13
#define BM_CPM_I2SCDR_DIV_M 0x3fe000
#define BF_CPM_I2SCDR_DIV_M(v) (((v) & 0x1ff) << 13)
#define BFM_CPM_I2SCDR_DIV_M(v) BM_CPM_I2SCDR_DIV_M
#define BF_CPM_I2SCDR_DIV_M_V(e) BF_CPM_I2SCDR_DIV_M(BV_CPM_I2SCDR_DIV_M__##e)
#define BFM_CPM_I2SCDR_DIV_M_V(v) BM_CPM_I2SCDR_DIV_M
#define BP_CPM_I2SCDR_DIV_N 0
#define BM_CPM_I2SCDR_DIV_N 0x1fff
#define BF_CPM_I2SCDR_DIV_N(v) (((v) & 0x1fff) << 0)
#define BFM_CPM_I2SCDR_DIV_N(v) BM_CPM_I2SCDR_DIV_N
#define BF_CPM_I2SCDR_DIV_N_V(e) BF_CPM_I2SCDR_DIV_N(BV_CPM_I2SCDR_DIV_N__##e)
#define BFM_CPM_I2SCDR_DIV_N_V(v) BM_CPM_I2SCDR_DIV_N
#define BP_CPM_I2SCDR_PCS 31
#define BM_CPM_I2SCDR_PCS 0x80000000
#define BV_CPM_I2SCDR_PCS__SCLK_A 0x0
#define BV_CPM_I2SCDR_PCS__MPLL 0x1
#define BF_CPM_I2SCDR_PCS(v) (((v) & 0x1) << 31)
#define BFM_CPM_I2SCDR_PCS(v) BM_CPM_I2SCDR_PCS
#define BF_CPM_I2SCDR_PCS_V(e) BF_CPM_I2SCDR_PCS(BV_CPM_I2SCDR_PCS__##e)
#define BFM_CPM_I2SCDR_PCS_V(v) BM_CPM_I2SCDR_PCS
#define BP_CPM_I2SCDR_CS 30
#define BM_CPM_I2SCDR_CS 0x40000000
#define BV_CPM_I2SCDR_CS__EXCLK 0x0
#define BV_CPM_I2SCDR_CS__PLL 0x1
#define BF_CPM_I2SCDR_CS(v) (((v) & 0x1) << 30)
#define BFM_CPM_I2SCDR_CS(v) BM_CPM_I2SCDR_CS
#define BF_CPM_I2SCDR_CS_V(e) BF_CPM_I2SCDR_CS(BV_CPM_I2SCDR_CS__##e)
#define BFM_CPM_I2SCDR_CS_V(v) BM_CPM_I2SCDR_CS
#define BP_CPM_I2SCDR_CE 29
#define BM_CPM_I2SCDR_CE 0x20000000
#define BF_CPM_I2SCDR_CE(v) (((v) & 0x1) << 29)
#define BFM_CPM_I2SCDR_CE(v) BM_CPM_I2SCDR_CE
#define BF_CPM_I2SCDR_CE_V(e) BF_CPM_I2SCDR_CE(BV_CPM_I2SCDR_CE__##e)
#define BFM_CPM_I2SCDR_CE_V(v) BM_CPM_I2SCDR_CE
#define REG_CPM_I2SCDR1 jz_reg(CPM_I2SCDR1)
#define JA_CPM_I2SCDR1 (0xb0000000 + 0x70)
#define JT_CPM_I2SCDR1 JIO_32_RW
#define JN_CPM_I2SCDR1 CPM_I2SCDR1
#define JI_CPM_I2SCDR1
#define REG_CPM_LPCDR jz_reg(CPM_LPCDR)
#define JA_CPM_LPCDR (0xb0000000 + 0x64)
#define JT_CPM_LPCDR JIO_32_RW
#define JN_CPM_LPCDR CPM_LPCDR
#define JI_CPM_LPCDR
#define BP_CPM_LPCDR_CLKDIV 0
#define BM_CPM_LPCDR_CLKDIV 0xff
#define BF_CPM_LPCDR_CLKDIV(v) (((v) & 0xff) << 0)
#define BFM_CPM_LPCDR_CLKDIV(v) BM_CPM_LPCDR_CLKDIV
#define BF_CPM_LPCDR_CLKDIV_V(e) BF_CPM_LPCDR_CLKDIV(BV_CPM_LPCDR_CLKDIV__##e)
#define BFM_CPM_LPCDR_CLKDIV_V(v) BM_CPM_LPCDR_CLKDIV
#define BP_CPM_LPCDR_CLKSRC 31
#define BM_CPM_LPCDR_CLKSRC 0x80000000
#define BV_CPM_LPCDR_CLKSRC__SCLK_A 0x0
#define BV_CPM_LPCDR_CLKSRC__MPLL 0x1
#define BF_CPM_LPCDR_CLKSRC(v) (((v) & 0x1) << 31)
#define BFM_CPM_LPCDR_CLKSRC(v) BM_CPM_LPCDR_CLKSRC
#define BF_CPM_LPCDR_CLKSRC_V(e) BF_CPM_LPCDR_CLKSRC(BV_CPM_LPCDR_CLKSRC__##e)
#define BFM_CPM_LPCDR_CLKSRC_V(v) BM_CPM_LPCDR_CLKSRC
#define BP_CPM_LPCDR_CE 28
#define BM_CPM_LPCDR_CE 0x10000000
#define BF_CPM_LPCDR_CE(v) (((v) & 0x1) << 28)
#define BFM_CPM_LPCDR_CE(v) BM_CPM_LPCDR_CE
#define BF_CPM_LPCDR_CE_V(e) BF_CPM_LPCDR_CE(BV_CPM_LPCDR_CE__##e)
#define BFM_CPM_LPCDR_CE_V(v) BM_CPM_LPCDR_CE
#define BP_CPM_LPCDR_BUSY 27
#define BM_CPM_LPCDR_BUSY 0x8000000
#define BF_CPM_LPCDR_BUSY(v) (((v) & 0x1) << 27)
#define BFM_CPM_LPCDR_BUSY(v) BM_CPM_LPCDR_BUSY
#define BF_CPM_LPCDR_BUSY_V(e) BF_CPM_LPCDR_BUSY(BV_CPM_LPCDR_BUSY__##e)
#define BFM_CPM_LPCDR_BUSY_V(v) BM_CPM_LPCDR_BUSY
#define BP_CPM_LPCDR_STOP 26
#define BM_CPM_LPCDR_STOP 0x4000000
#define BF_CPM_LPCDR_STOP(v) (((v) & 0x1) << 26)
#define BFM_CPM_LPCDR_STOP(v) BM_CPM_LPCDR_STOP
#define BF_CPM_LPCDR_STOP_V(e) BF_CPM_LPCDR_STOP(BV_CPM_LPCDR_STOP__##e)
#define BFM_CPM_LPCDR_STOP_V(v) BM_CPM_LPCDR_STOP
#define REG_CPM_MSC0CDR jz_reg(CPM_MSC0CDR)
#define JA_CPM_MSC0CDR (0xb0000000 + 0x68)
#define JT_CPM_MSC0CDR JIO_32_RW
#define JN_CPM_MSC0CDR CPM_MSC0CDR
#define JI_CPM_MSC0CDR
#define BP_CPM_MSC0CDR_CLKDIV 0
#define BM_CPM_MSC0CDR_CLKDIV 0xff
#define BF_CPM_MSC0CDR_CLKDIV(v) (((v) & 0xff) << 0)
#define BFM_CPM_MSC0CDR_CLKDIV(v) BM_CPM_MSC0CDR_CLKDIV
#define BF_CPM_MSC0CDR_CLKDIV_V(e) BF_CPM_MSC0CDR_CLKDIV(BV_CPM_MSC0CDR_CLKDIV__##e)
#define BFM_CPM_MSC0CDR_CLKDIV_V(v) BM_CPM_MSC0CDR_CLKDIV
#define BP_CPM_MSC0CDR_CLKSRC 31
#define BM_CPM_MSC0CDR_CLKSRC 0x80000000
#define BV_CPM_MSC0CDR_CLKSRC__SCLK_A 0x0
#define BV_CPM_MSC0CDR_CLKSRC__MPLL 0x1
#define BF_CPM_MSC0CDR_CLKSRC(v) (((v) & 0x1) << 31)
#define BFM_CPM_MSC0CDR_CLKSRC(v) BM_CPM_MSC0CDR_CLKSRC
#define BF_CPM_MSC0CDR_CLKSRC_V(e) BF_CPM_MSC0CDR_CLKSRC(BV_CPM_MSC0CDR_CLKSRC__##e)
#define BFM_CPM_MSC0CDR_CLKSRC_V(v) BM_CPM_MSC0CDR_CLKSRC
#define BP_CPM_MSC0CDR_CE 29
#define BM_CPM_MSC0CDR_CE 0x20000000
#define BF_CPM_MSC0CDR_CE(v) (((v) & 0x1) << 29)
#define BFM_CPM_MSC0CDR_CE(v) BM_CPM_MSC0CDR_CE
#define BF_CPM_MSC0CDR_CE_V(e) BF_CPM_MSC0CDR_CE(BV_CPM_MSC0CDR_CE__##e)
#define BFM_CPM_MSC0CDR_CE_V(v) BM_CPM_MSC0CDR_CE
#define BP_CPM_MSC0CDR_BUSY 28
#define BM_CPM_MSC0CDR_BUSY 0x10000000
#define BF_CPM_MSC0CDR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CPM_MSC0CDR_BUSY(v) BM_CPM_MSC0CDR_BUSY
#define BF_CPM_MSC0CDR_BUSY_V(e) BF_CPM_MSC0CDR_BUSY(BV_CPM_MSC0CDR_BUSY__##e)
#define BFM_CPM_MSC0CDR_BUSY_V(v) BM_CPM_MSC0CDR_BUSY
#define BP_CPM_MSC0CDR_STOP 27
#define BM_CPM_MSC0CDR_STOP 0x8000000
#define BF_CPM_MSC0CDR_STOP(v) (((v) & 0x1) << 27)
#define BFM_CPM_MSC0CDR_STOP(v) BM_CPM_MSC0CDR_STOP
#define BF_CPM_MSC0CDR_STOP_V(e) BF_CPM_MSC0CDR_STOP(BV_CPM_MSC0CDR_STOP__##e)
#define BFM_CPM_MSC0CDR_STOP_V(v) BM_CPM_MSC0CDR_STOP
#define BP_CPM_MSC0CDR_S_CLK0_SEL 15
#define BM_CPM_MSC0CDR_S_CLK0_SEL 0x8000
#define BV_CPM_MSC0CDR_S_CLK0_SEL__90DEG 0x0
#define BV_CPM_MSC0CDR_S_CLK0_SEL__180DEG 0x1
#define BF_CPM_MSC0CDR_S_CLK0_SEL(v) (((v) & 0x1) << 15)
#define BFM_CPM_MSC0CDR_S_CLK0_SEL(v) BM_CPM_MSC0CDR_S_CLK0_SEL
#define BF_CPM_MSC0CDR_S_CLK0_SEL_V(e) BF_CPM_MSC0CDR_S_CLK0_SEL(BV_CPM_MSC0CDR_S_CLK0_SEL__##e)
#define BFM_CPM_MSC0CDR_S_CLK0_SEL_V(v) BM_CPM_MSC0CDR_S_CLK0_SEL
#define REG_CPM_MSC1CDR jz_reg(CPM_MSC1CDR)
#define JA_CPM_MSC1CDR (0xb0000000 + 0xa4)
#define JT_CPM_MSC1CDR JIO_32_RW
#define JN_CPM_MSC1CDR CPM_MSC1CDR
#define JI_CPM_MSC1CDR
#define BP_CPM_MSC1CDR_CLKDIV 0
#define BM_CPM_MSC1CDR_CLKDIV 0xff
#define BF_CPM_MSC1CDR_CLKDIV(v) (((v) & 0xff) << 0)
#define BFM_CPM_MSC1CDR_CLKDIV(v) BM_CPM_MSC1CDR_CLKDIV
#define BF_CPM_MSC1CDR_CLKDIV_V(e) BF_CPM_MSC1CDR_CLKDIV(BV_CPM_MSC1CDR_CLKDIV__##e)
#define BFM_CPM_MSC1CDR_CLKDIV_V(v) BM_CPM_MSC1CDR_CLKDIV
#define BP_CPM_MSC1CDR_CE 29
#define BM_CPM_MSC1CDR_CE 0x20000000
#define BF_CPM_MSC1CDR_CE(v) (((v) & 0x1) << 29)
#define BFM_CPM_MSC1CDR_CE(v) BM_CPM_MSC1CDR_CE
#define BF_CPM_MSC1CDR_CE_V(e) BF_CPM_MSC1CDR_CE(BV_CPM_MSC1CDR_CE__##e)
#define BFM_CPM_MSC1CDR_CE_V(v) BM_CPM_MSC1CDR_CE
#define BP_CPM_MSC1CDR_BUSY 28
#define BM_CPM_MSC1CDR_BUSY 0x10000000
#define BF_CPM_MSC1CDR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CPM_MSC1CDR_BUSY(v) BM_CPM_MSC1CDR_BUSY
#define BF_CPM_MSC1CDR_BUSY_V(e) BF_CPM_MSC1CDR_BUSY(BV_CPM_MSC1CDR_BUSY__##e)
#define BFM_CPM_MSC1CDR_BUSY_V(v) BM_CPM_MSC1CDR_BUSY
#define BP_CPM_MSC1CDR_STOP 27
#define BM_CPM_MSC1CDR_STOP 0x8000000
#define BF_CPM_MSC1CDR_STOP(v) (((v) & 0x1) << 27)
#define BFM_CPM_MSC1CDR_STOP(v) BM_CPM_MSC1CDR_STOP
#define BF_CPM_MSC1CDR_STOP_V(e) BF_CPM_MSC1CDR_STOP(BV_CPM_MSC1CDR_STOP__##e)
#define BFM_CPM_MSC1CDR_STOP_V(v) BM_CPM_MSC1CDR_STOP
#define BP_CPM_MSC1CDR_S_CLK1_SEL 15
#define BM_CPM_MSC1CDR_S_CLK1_SEL 0x8000
#define BV_CPM_MSC1CDR_S_CLK1_SEL__90DEG 0x0
#define BV_CPM_MSC1CDR_S_CLK1_SEL__180DEG 0x1
#define BF_CPM_MSC1CDR_S_CLK1_SEL(v) (((v) & 0x1) << 15)
#define BFM_CPM_MSC1CDR_S_CLK1_SEL(v) BM_CPM_MSC1CDR_S_CLK1_SEL
#define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e)
#define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL
#define REG_CPM_SSICDR jz_reg(CPM_SSICDR)
#define JA_CPM_SSICDR (0xb0000000 + 0x74)
#define JT_CPM_SSICDR JIO_32_RW
#define JN_CPM_SSICDR CPM_SSICDR
#define JI_CPM_SSICDR
#define BP_CPM_SSICDR_CLKDIV 0
#define BM_CPM_SSICDR_CLKDIV 0xff
#define BF_CPM_SSICDR_CLKDIV(v) (((v) & 0xff) << 0)
#define BFM_CPM_SSICDR_CLKDIV(v) BM_CPM_SSICDR_CLKDIV
#define BF_CPM_SSICDR_CLKDIV_V(e) BF_CPM_SSICDR_CLKDIV(BV_CPM_SSICDR_CLKDIV__##e)
#define BFM_CPM_SSICDR_CLKDIV_V(v) BM_CPM_SSICDR_CLKDIV
#define BP_CPM_SSICDR_SFC_CS 31
#define BM_CPM_SSICDR_SFC_CS 0x80000000
#define BV_CPM_SSICDR_SFC_CS__SCLK_A 0x0
#define BV_CPM_SSICDR_SFC_CS__MPLL 0x1
#define BF_CPM_SSICDR_SFC_CS(v) (((v) & 0x1) << 31)
#define BFM_CPM_SSICDR_SFC_CS(v) BM_CPM_SSICDR_SFC_CS
#define BF_CPM_SSICDR_SFC_CS_V(e) BF_CPM_SSICDR_SFC_CS(BV_CPM_SSICDR_SFC_CS__##e)
#define BFM_CPM_SSICDR_SFC_CS_V(v) BM_CPM_SSICDR_SFC_CS
#define BP_CPM_SSICDR_SSI_CS 30
#define BM_CPM_SSICDR_SSI_CS 0x40000000
#define BV_CPM_SSICDR_SSI_CS__EXCLK 0x0
#define BV_CPM_SSICDR_SSI_CS__HALF_SFC 0x1
#define BF_CPM_SSICDR_SSI_CS(v) (((v) & 0x1) << 30)
#define BFM_CPM_SSICDR_SSI_CS(v) BM_CPM_SSICDR_SSI_CS
#define BF_CPM_SSICDR_SSI_CS_V(e) BF_CPM_SSICDR_SSI_CS(BV_CPM_SSICDR_SSI_CS__##e)
#define BFM_CPM_SSICDR_SSI_CS_V(v) BM_CPM_SSICDR_SSI_CS
#define BP_CPM_SSICDR_CE 29
#define BM_CPM_SSICDR_CE 0x20000000
#define BF_CPM_SSICDR_CE(v) (((v) & 0x1) << 29)
#define BFM_CPM_SSICDR_CE(v) BM_CPM_SSICDR_CE
#define BF_CPM_SSICDR_CE_V(e) BF_CPM_SSICDR_CE(BV_CPM_SSICDR_CE__##e)
#define BFM_CPM_SSICDR_CE_V(v) BM_CPM_SSICDR_CE
#define BP_CPM_SSICDR_BUSY 28
#define BM_CPM_SSICDR_BUSY 0x10000000
#define BF_CPM_SSICDR_BUSY(v) (((v) & 0x1) << 28)
#define BFM_CPM_SSICDR_BUSY(v) BM_CPM_SSICDR_BUSY
#define BF_CPM_SSICDR_BUSY_V(e) BF_CPM_SSICDR_BUSY(BV_CPM_SSICDR_BUSY__##e)
#define BFM_CPM_SSICDR_BUSY_V(v) BM_CPM_SSICDR_BUSY
#define BP_CPM_SSICDR_STOP 27
#define BM_CPM_SSICDR_STOP 0x8000000
#define BF_CPM_SSICDR_STOP(v) (((v) & 0x1) << 27)
#define BFM_CPM_SSICDR_STOP(v) BM_CPM_SSICDR_STOP
#define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e)
#define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP
#define REG_CPM_DRCG jz_reg(CPM_DRCG)
#define JA_CPM_DRCG (0xb0000000 + 0xd0)
#define JT_CPM_DRCG JIO_32_RW
#define JN_CPM_DRCG CPM_DRCG
#define JI_CPM_DRCG
#define REG_CPM_APCR jz_reg(CPM_APCR)
#define JA_CPM_APCR (0xb0000000 + 0x10)
#define JT_CPM_APCR JIO_32_RW
#define JN_CPM_APCR CPM_APCR
#define JI_CPM_APCR
#define BP_CPM_APCR_PLLM 24
#define BM_CPM_APCR_PLLM 0x7f000000
#define BF_CPM_APCR_PLLM(v) (((v) & 0x7f) << 24)
#define BFM_CPM_APCR_PLLM(v) BM_CPM_APCR_PLLM
#define BF_CPM_APCR_PLLM_V(e) BF_CPM_APCR_PLLM(BV_CPM_APCR_PLLM__##e)
#define BFM_CPM_APCR_PLLM_V(v) BM_CPM_APCR_PLLM
#define BP_CPM_APCR_PLLN 18
#define BM_CPM_APCR_PLLN 0x7c0000
#define BF_CPM_APCR_PLLN(v) (((v) & 0x1f) << 18)
#define BFM_CPM_APCR_PLLN(v) BM_CPM_APCR_PLLN
#define BF_CPM_APCR_PLLN_V(e) BF_CPM_APCR_PLLN(BV_CPM_APCR_PLLN__##e)
#define BFM_CPM_APCR_PLLN_V(v) BM_CPM_APCR_PLLN
#define BP_CPM_APCR_PLLOD 16
#define BM_CPM_APCR_PLLOD 0x30000
#define BF_CPM_APCR_PLLOD(v) (((v) & 0x3) << 16)
#define BFM_CPM_APCR_PLLOD(v) BM_CPM_APCR_PLLOD
#define BF_CPM_APCR_PLLOD_V(e) BF_CPM_APCR_PLLOD(BV_CPM_APCR_PLLOD__##e)
#define BFM_CPM_APCR_PLLOD_V(v) BM_CPM_APCR_PLLOD
#define BP_CPM_APCR_PLLST 0
#define BM_CPM_APCR_PLLST 0xff
#define BF_CPM_APCR_PLLST(v) (((v) & 0xff) << 0)
#define BFM_CPM_APCR_PLLST(v) BM_CPM_APCR_PLLST
#define BF_CPM_APCR_PLLST_V(e) BF_CPM_APCR_PLLST(BV_CPM_APCR_PLLST__##e)
#define BFM_CPM_APCR_PLLST_V(v) BM_CPM_APCR_PLLST
#define BP_CPM_APCR_BS 31
#define BM_CPM_APCR_BS 0x80000000
#define BF_CPM_APCR_BS(v) (((v) & 0x1) << 31)
#define BFM_CPM_APCR_BS(v) BM_CPM_APCR_BS
#define BF_CPM_APCR_BS_V(e) BF_CPM_APCR_BS(BV_CPM_APCR_BS__##e)
#define BFM_CPM_APCR_BS_V(v) BM_CPM_APCR_BS
#define BP_CPM_APCR_LOCK 15
#define BM_CPM_APCR_LOCK 0x8000
#define BF_CPM_APCR_LOCK(v) (((v) & 0x1) << 15)
#define BFM_CPM_APCR_LOCK(v) BM_CPM_APCR_LOCK
#define BF_CPM_APCR_LOCK_V(e) BF_CPM_APCR_LOCK(BV_CPM_APCR_LOCK__##e)
#define BFM_CPM_APCR_LOCK_V(v) BM_CPM_APCR_LOCK
#define BP_CPM_APCR_ON 10
#define BM_CPM_APCR_ON 0x400
#define BF_CPM_APCR_ON(v) (((v) & 0x1) << 10)
#define BFM_CPM_APCR_ON(v) BM_CPM_APCR_ON
#define BF_CPM_APCR_ON_V(e) BF_CPM_APCR_ON(BV_CPM_APCR_ON__##e)
#define BFM_CPM_APCR_ON_V(v) BM_CPM_APCR_ON
#define BP_CPM_APCR_BYPASS 9
#define BM_CPM_APCR_BYPASS 0x200
#define BF_CPM_APCR_BYPASS(v) (((v) & 0x1) << 9)
#define BFM_CPM_APCR_BYPASS(v) BM_CPM_APCR_BYPASS
#define BF_CPM_APCR_BYPASS_V(e) BF_CPM_APCR_BYPASS(BV_CPM_APCR_BYPASS__##e)
#define BFM_CPM_APCR_BYPASS_V(v) BM_CPM_APCR_BYPASS
#define BP_CPM_APCR_ENABLE 8
#define BM_CPM_APCR_ENABLE 0x100
#define BF_CPM_APCR_ENABLE(v) (((v) & 0x1) << 8)
#define BFM_CPM_APCR_ENABLE(v) BM_CPM_APCR_ENABLE
#define BF_CPM_APCR_ENABLE_V(e) BF_CPM_APCR_ENABLE(BV_CPM_APCR_ENABLE__##e)
#define BFM_CPM_APCR_ENABLE_V(v) BM_CPM_APCR_ENABLE
#define REG_CPM_MPCR jz_reg(CPM_MPCR)
#define JA_CPM_MPCR (0xb0000000 + 0x14)
#define JT_CPM_MPCR JIO_32_RW
#define JN_CPM_MPCR CPM_MPCR
#define JI_CPM_MPCR
#define BP_CPM_MPCR_PLLM 24
#define BM_CPM_MPCR_PLLM 0x7f000000
#define BF_CPM_MPCR_PLLM(v) (((v) & 0x7f) << 24)
#define BFM_CPM_MPCR_PLLM(v) BM_CPM_MPCR_PLLM
#define BF_CPM_MPCR_PLLM_V(e) BF_CPM_MPCR_PLLM(BV_CPM_MPCR_PLLM__##e)
#define BFM_CPM_MPCR_PLLM_V(v) BM_CPM_MPCR_PLLM
#define BP_CPM_MPCR_PLLN 18
#define BM_CPM_MPCR_PLLN 0x7c0000
#define BF_CPM_MPCR_PLLN(v) (((v) & 0x1f) << 18)
#define BFM_CPM_MPCR_PLLN(v) BM_CPM_MPCR_PLLN
#define BF_CPM_MPCR_PLLN_V(e) BF_CPM_MPCR_PLLN(BV_CPM_MPCR_PLLN__##e)
#define BFM_CPM_MPCR_PLLN_V(v) BM_CPM_MPCR_PLLN
#define BP_CPM_MPCR_PLLOD 16
#define BM_CPM_MPCR_PLLOD 0x30000
#define BF_CPM_MPCR_PLLOD(v) (((v) & 0x3) << 16)
#define BFM_CPM_MPCR_PLLOD(v) BM_CPM_MPCR_PLLOD
#define BF_CPM_MPCR_PLLOD_V(e) BF_CPM_MPCR_PLLOD(BV_CPM_MPCR_PLLOD__##e)
#define BFM_CPM_MPCR_PLLOD_V(v) BM_CPM_MPCR_PLLOD
#define BP_CPM_MPCR_BS 31
#define BM_CPM_MPCR_BS 0x80000000
#define BF_CPM_MPCR_BS(v) (((v) & 0x1) << 31)
#define BFM_CPM_MPCR_BS(v) BM_CPM_MPCR_BS
#define BF_CPM_MPCR_BS_V(e) BF_CPM_MPCR_BS(BV_CPM_MPCR_BS__##e)
#define BFM_CPM_MPCR_BS_V(v) BM_CPM_MPCR_BS
#define BP_CPM_MPCR_ENABLE 7
#define BM_CPM_MPCR_ENABLE 0x80
#define BF_CPM_MPCR_ENABLE(v) (((v) & 0x1) << 7)
#define BFM_CPM_MPCR_ENABLE(v) BM_CPM_MPCR_ENABLE
#define BF_CPM_MPCR_ENABLE_V(e) BF_CPM_MPCR_ENABLE(BV_CPM_MPCR_ENABLE__##e)
#define BFM_CPM_MPCR_ENABLE_V(v) BM_CPM_MPCR_ENABLE
#define BP_CPM_MPCR_BYPASS 6
#define BM_CPM_MPCR_BYPASS 0x40
#define BF_CPM_MPCR_BYPASS(v) (((v) & 0x1) << 6)
#define BFM_CPM_MPCR_BYPASS(v) BM_CPM_MPCR_BYPASS
#define BF_CPM_MPCR_BYPASS_V(e) BF_CPM_MPCR_BYPASS(BV_CPM_MPCR_BYPASS__##e)
#define BFM_CPM_MPCR_BYPASS_V(v) BM_CPM_MPCR_BYPASS
#define BP_CPM_MPCR_LOCK 1
#define BM_CPM_MPCR_LOCK 0x2
#define BF_CPM_MPCR_LOCK(v) (((v) & 0x1) << 1)
#define BFM_CPM_MPCR_LOCK(v) BM_CPM_MPCR_LOCK
#define BF_CPM_MPCR_LOCK_V(e) BF_CPM_MPCR_LOCK(BV_CPM_MPCR_LOCK__##e)
#define BFM_CPM_MPCR_LOCK_V(v) BM_CPM_MPCR_LOCK
#define BP_CPM_MPCR_ON 0
#define BM_CPM_MPCR_ON 0x1
#define BF_CPM_MPCR_ON(v) (((v) & 0x1) << 0)
#define BFM_CPM_MPCR_ON(v) BM_CPM_MPCR_ON
#define BF_CPM_MPCR_ON_V(e) BF_CPM_MPCR_ON(BV_CPM_MPCR_ON__##e)
#define BFM_CPM_MPCR_ON_V(v) BM_CPM_MPCR_ON
#define REG_CPM_LCR jz_reg(CPM_LCR)
#define JA_CPM_LCR (0xb0000000 + 0x4)
#define JT_CPM_LCR JIO_32_RW
#define JN_CPM_LCR CPM_LCR
#define JI_CPM_LCR
#define BP_CPM_LCR_PST 8
#define BM_CPM_LCR_PST 0xfff00
#define BF_CPM_LCR_PST(v) (((v) & 0xfff) << 8)
#define BFM_CPM_LCR_PST(v) BM_CPM_LCR_PST
#define BF_CPM_LCR_PST_V(e) BF_CPM_LCR_PST(BV_CPM_LCR_PST__##e)
#define BFM_CPM_LCR_PST_V(v) BM_CPM_LCR_PST
#define BP_CPM_LCR_LPM 0
#define BM_CPM_LCR_LPM 0x3
#define BV_CPM_LCR_LPM__IDLE 0x0
#define BV_CPM_LCR_LPM__SLEEP 0x1
#define BF_CPM_LCR_LPM(v) (((v) & 0x3) << 0)
#define BFM_CPM_LCR_LPM(v) BM_CPM_LCR_LPM
#define BF_CPM_LCR_LPM_V(e) BF_CPM_LCR_LPM(BV_CPM_LCR_LPM__##e)
#define BFM_CPM_LCR_LPM_V(v) BM_CPM_LCR_LPM
#define REG_CPM_PSWC0ST jz_reg(CPM_PSWC0ST)
#define JA_CPM_PSWC0ST (0xb0000000 + 0x90)
#define JT_CPM_PSWC0ST JIO_32_RW
#define JN_CPM_PSWC0ST CPM_PSWC0ST
#define JI_CPM_PSWC0ST
#define REG_CPM_PSWC1ST jz_reg(CPM_PSWC1ST)
#define JA_CPM_PSWC1ST (0xb0000000 + 0x94)
#define JT_CPM_PSWC1ST JIO_32_RW
#define JN_CPM_PSWC1ST CPM_PSWC1ST
#define JI_CPM_PSWC1ST
#define REG_CPM_PSWC2ST jz_reg(CPM_PSWC2ST)
#define JA_CPM_PSWC2ST (0xb0000000 + 0x98)
#define JT_CPM_PSWC2ST JIO_32_RW
#define JN_CPM_PSWC2ST CPM_PSWC2ST
#define JI_CPM_PSWC2ST
#define REG_CPM_PSWC3ST jz_reg(CPM_PSWC3ST)
#define JA_CPM_PSWC3ST (0xb0000000 + 0x9c)
#define JT_CPM_PSWC3ST JIO_32_RW
#define JN_CPM_PSWC3ST CPM_PSWC3ST
#define JI_CPM_PSWC3ST
#define REG_CPM_CLKGR jz_reg(CPM_CLKGR)
#define JA_CPM_CLKGR (0xb0000000 + 0x20)
#define JT_CPM_CLKGR JIO_32_RW
#define JN_CPM_CLKGR CPM_CLKGR
#define JI_CPM_CLKGR
#define BP_CPM_CLKGR_DDR 31
#define BM_CPM_CLKGR_DDR 0x80000000
#define BF_CPM_CLKGR_DDR(v) (((v) & 0x1) << 31)
#define BFM_CPM_CLKGR_DDR(v) BM_CPM_CLKGR_DDR
#define BF_CPM_CLKGR_DDR_V(e) BF_CPM_CLKGR_DDR(BV_CPM_CLKGR_DDR__##e)
#define BFM_CPM_CLKGR_DDR_V(v) BM_CPM_CLKGR_DDR
#define BP_CPM_CLKGR_CPU_BIT 30
#define BM_CPM_CLKGR_CPU_BIT 0x40000000
#define BF_CPM_CLKGR_CPU_BIT(v) (((v) & 0x1) << 30)
#define BFM_CPM_CLKGR_CPU_BIT(v) BM_CPM_CLKGR_CPU_BIT
#define BF_CPM_CLKGR_CPU_BIT_V(e) BF_CPM_CLKGR_CPU_BIT(BV_CPM_CLKGR_CPU_BIT__##e)
#define BFM_CPM_CLKGR_CPU_BIT_V(v) BM_CPM_CLKGR_CPU_BIT
#define BP_CPM_CLKGR_AHB0 29
#define BM_CPM_CLKGR_AHB0 0x20000000
#define BF_CPM_CLKGR_AHB0(v) (((v) & 0x1) << 29)
#define BFM_CPM_CLKGR_AHB0(v) BM_CPM_CLKGR_AHB0
#define BF_CPM_CLKGR_AHB0_V(e) BF_CPM_CLKGR_AHB0(BV_CPM_CLKGR_AHB0__##e)
#define BFM_CPM_CLKGR_AHB0_V(v) BM_CPM_CLKGR_AHB0
#define BP_CPM_CLKGR_APB0 28
#define BM_CPM_CLKGR_APB0 0x10000000
#define BF_CPM_CLKGR_APB0(v) (((v) & 0x1) << 28)
#define BFM_CPM_CLKGR_APB0(v) BM_CPM_CLKGR_APB0
#define BF_CPM_CLKGR_APB0_V(e) BF_CPM_CLKGR_APB0(BV_CPM_CLKGR_APB0__##e)
#define BFM_CPM_CLKGR_APB0_V(v) BM_CPM_CLKGR_APB0
#define BP_CPM_CLKGR_RTC 27
#define BM_CPM_CLKGR_RTC 0x8000000
#define BF_CPM_CLKGR_RTC(v) (((v) & 0x1) << 27)
#define BFM_CPM_CLKGR_RTC(v) BM_CPM_CLKGR_RTC
#define BF_CPM_CLKGR_RTC_V(e) BF_CPM_CLKGR_RTC(BV_CPM_CLKGR_RTC__##e)
#define BFM_CPM_CLKGR_RTC_V(v) BM_CPM_CLKGR_RTC
#define BP_CPM_CLKGR_PCM 26
#define BM_CPM_CLKGR_PCM 0x4000000
#define BF_CPM_CLKGR_PCM(v) (((v) & 0x1) << 26)
#define BFM_CPM_CLKGR_PCM(v) BM_CPM_CLKGR_PCM
#define BF_CPM_CLKGR_PCM_V(e) BF_CPM_CLKGR_PCM(BV_CPM_CLKGR_PCM__##e)
#define BFM_CPM_CLKGR_PCM_V(v) BM_CPM_CLKGR_PCM
#define BP_CPM_CLKGR_MAC 25
#define BM_CPM_CLKGR_MAC 0x2000000
#define BF_CPM_CLKGR_MAC(v) (((v) & 0x1) << 25)
#define BFM_CPM_CLKGR_MAC(v) BM_CPM_CLKGR_MAC
#define BF_CPM_CLKGR_MAC_V(e) BF_CPM_CLKGR_MAC(BV_CPM_CLKGR_MAC__##e)
#define BFM_CPM_CLKGR_MAC_V(v) BM_CPM_CLKGR_MAC
#define BP_CPM_CLKGR_AES 24
#define BM_CPM_CLKGR_AES 0x1000000
#define BF_CPM_CLKGR_AES(v) (((v) & 0x1) << 24)
#define BFM_CPM_CLKGR_AES(v) BM_CPM_CLKGR_AES
#define BF_CPM_CLKGR_AES_V(e) BF_CPM_CLKGR_AES(BV_CPM_CLKGR_AES__##e)
#define BFM_CPM_CLKGR_AES_V(v) BM_CPM_CLKGR_AES
#define BP_CPM_CLKGR_LCD 23
#define BM_CPM_CLKGR_LCD 0x800000
#define BF_CPM_CLKGR_LCD(v) (((v) & 0x1) << 23)
#define BFM_CPM_CLKGR_LCD(v) BM_CPM_CLKGR_LCD
#define BF_CPM_CLKGR_LCD_V(e) BF_CPM_CLKGR_LCD(BV_CPM_CLKGR_LCD__##e)
#define BFM_CPM_CLKGR_LCD_V(v) BM_CPM_CLKGR_LCD
#define BP_CPM_CLKGR_CIM 22
#define BM_CPM_CLKGR_CIM 0x400000
#define BF_CPM_CLKGR_CIM(v) (((v) & 0x1) << 22)
#define BFM_CPM_CLKGR_CIM(v) BM_CPM_CLKGR_CIM
#define BF_CPM_CLKGR_CIM_V(e) BF_CPM_CLKGR_CIM(BV_CPM_CLKGR_CIM__##e)
#define BFM_CPM_CLKGR_CIM_V(v) BM_CPM_CLKGR_CIM
#define BP_CPM_CLKGR_PDMA 21
#define BM_CPM_CLKGR_PDMA 0x200000
#define BF_CPM_CLKGR_PDMA(v) (((v) & 0x1) << 21)
#define BFM_CPM_CLKGR_PDMA(v) BM_CPM_CLKGR_PDMA
#define BF_CPM_CLKGR_PDMA_V(e) BF_CPM_CLKGR_PDMA(BV_CPM_CLKGR_PDMA__##e)
#define BFM_CPM_CLKGR_PDMA_V(v) BM_CPM_CLKGR_PDMA
#define BP_CPM_CLKGR_OST 20
#define BM_CPM_CLKGR_OST 0x100000
#define BF_CPM_CLKGR_OST(v) (((v) & 0x1) << 20)
#define BFM_CPM_CLKGR_OST(v) BM_CPM_CLKGR_OST
#define BF_CPM_CLKGR_OST_V(e) BF_CPM_CLKGR_OST(BV_CPM_CLKGR_OST__##e)
#define BFM_CPM_CLKGR_OST_V(v) BM_CPM_CLKGR_OST
#define BP_CPM_CLKGR_SSI 19
#define BM_CPM_CLKGR_SSI 0x80000
#define BF_CPM_CLKGR_SSI(v) (((v) & 0x1) << 19)
#define BFM_CPM_CLKGR_SSI(v) BM_CPM_CLKGR_SSI
#define BF_CPM_CLKGR_SSI_V(e) BF_CPM_CLKGR_SSI(BV_CPM_CLKGR_SSI__##e)
#define BFM_CPM_CLKGR_SSI_V(v) BM_CPM_CLKGR_SSI
#define BP_CPM_CLKGR_TCU 18
#define BM_CPM_CLKGR_TCU 0x40000
#define BF_CPM_CLKGR_TCU(v) (((v) & 0x1) << 18)
#define BFM_CPM_CLKGR_TCU(v) BM_CPM_CLKGR_TCU
#define BF_CPM_CLKGR_TCU_V(e) BF_CPM_CLKGR_TCU(BV_CPM_CLKGR_TCU__##e)
#define BFM_CPM_CLKGR_TCU_V(v) BM_CPM_CLKGR_TCU
#define BP_CPM_CLKGR_DMIC 17
#define BM_CPM_CLKGR_DMIC 0x20000
#define BF_CPM_CLKGR_DMIC(v) (((v) & 0x1) << 17)
#define BFM_CPM_CLKGR_DMIC(v) BM_CPM_CLKGR_DMIC
#define BF_CPM_CLKGR_DMIC_V(e) BF_CPM_CLKGR_DMIC(BV_CPM_CLKGR_DMIC__##e)
#define BFM_CPM_CLKGR_DMIC_V(v) BM_CPM_CLKGR_DMIC
#define BP_CPM_CLKGR_UART2 16
#define BM_CPM_CLKGR_UART2 0x10000
#define BF_CPM_CLKGR_UART2(v) (((v) & 0x1) << 16)
#define BFM_CPM_CLKGR_UART2(v) BM_CPM_CLKGR_UART2
#define BF_CPM_CLKGR_UART2_V(e) BF_CPM_CLKGR_UART2(BV_CPM_CLKGR_UART2__##e)
#define BFM_CPM_CLKGR_UART2_V(v) BM_CPM_CLKGR_UART2
#define BP_CPM_CLKGR_UART1 15
#define BM_CPM_CLKGR_UART1 0x8000
#define BF_CPM_CLKGR_UART1(v) (((v) & 0x1) << 15)
#define BFM_CPM_CLKGR_UART1(v) BM_CPM_CLKGR_UART1
#define BF_CPM_CLKGR_UART1_V(e) BF_CPM_CLKGR_UART1(BV_CPM_CLKGR_UART1__##e)
#define BFM_CPM_CLKGR_UART1_V(v) BM_CPM_CLKGR_UART1
#define BP_CPM_CLKGR_UART0 14
#define BM_CPM_CLKGR_UART0 0x4000
#define BF_CPM_CLKGR_UART0(v) (((v) & 0x1) << 14)
#define BFM_CPM_CLKGR_UART0(v) BM_CPM_CLKGR_UART0
#define BF_CPM_CLKGR_UART0_V(e) BF_CPM_CLKGR_UART0(BV_CPM_CLKGR_UART0__##e)
#define BFM_CPM_CLKGR_UART0_V(v) BM_CPM_CLKGR_UART0
#define BP_CPM_CLKGR_JPEG 12
#define BM_CPM_CLKGR_JPEG 0x1000
#define BF_CPM_CLKGR_JPEG(v) (((v) & 0x1) << 12)
#define BFM_CPM_CLKGR_JPEG(v) BM_CPM_CLKGR_JPEG
#define BF_CPM_CLKGR_JPEG_V(e) BF_CPM_CLKGR_JPEG(BV_CPM_CLKGR_JPEG__##e)
#define BFM_CPM_CLKGR_JPEG_V(v) BM_CPM_CLKGR_JPEG
#define BP_CPM_CLKGR_AIC 11
#define BM_CPM_CLKGR_AIC 0x800
#define BF_CPM_CLKGR_AIC(v) (((v) & 0x1) << 11)
#define BFM_CPM_CLKGR_AIC(v) BM_CPM_CLKGR_AIC
#define BF_CPM_CLKGR_AIC_V(e) BF_CPM_CLKGR_AIC(BV_CPM_CLKGR_AIC__##e)
#define BFM_CPM_CLKGR_AIC_V(v) BM_CPM_CLKGR_AIC
#define BP_CPM_CLKGR_I2C2 9
#define BM_CPM_CLKGR_I2C2 0x200
#define BF_CPM_CLKGR_I2C2(v) (((v) & 0x1) << 9)
#define BFM_CPM_CLKGR_I2C2(v) BM_CPM_CLKGR_I2C2
#define BF_CPM_CLKGR_I2C2_V(e) BF_CPM_CLKGR_I2C2(BV_CPM_CLKGR_I2C2__##e)
#define BFM_CPM_CLKGR_I2C2_V(v) BM_CPM_CLKGR_I2C2
#define BP_CPM_CLKGR_I2C1 8
#define BM_CPM_CLKGR_I2C1 0x100
#define BF_CPM_CLKGR_I2C1(v) (((v) & 0x1) << 8)
#define BFM_CPM_CLKGR_I2C1(v) BM_CPM_CLKGR_I2C1
#define BF_CPM_CLKGR_I2C1_V(e) BF_CPM_CLKGR_I2C1(BV_CPM_CLKGR_I2C1__##e)
#define BFM_CPM_CLKGR_I2C1_V(v) BM_CPM_CLKGR_I2C1
#define BP_CPM_CLKGR_I2C0 7
#define BM_CPM_CLKGR_I2C0 0x80
#define BF_CPM_CLKGR_I2C0(v) (((v) & 0x1) << 7)
#define BFM_CPM_CLKGR_I2C0(v) BM_CPM_CLKGR_I2C0
#define BF_CPM_CLKGR_I2C0_V(e) BF_CPM_CLKGR_I2C0(BV_CPM_CLKGR_I2C0__##e)
#define BFM_CPM_CLKGR_I2C0_V(v) BM_CPM_CLKGR_I2C0
#define BP_CPM_CLKGR_SCC 6
#define BM_CPM_CLKGR_SCC 0x40
#define BF_CPM_CLKGR_SCC(v) (((v) & 0x1) << 6)
#define BFM_CPM_CLKGR_SCC(v) BM_CPM_CLKGR_SCC
#define BF_CPM_CLKGR_SCC_V(e) BF_CPM_CLKGR_SCC(BV_CPM_CLKGR_SCC__##e)
#define BFM_CPM_CLKGR_SCC_V(v) BM_CPM_CLKGR_SCC
#define BP_CPM_CLKGR_MSC1 5
#define BM_CPM_CLKGR_MSC1 0x20
#define BF_CPM_CLKGR_MSC1(v) (((v) & 0x1) << 5)
#define BFM_CPM_CLKGR_MSC1(v) BM_CPM_CLKGR_MSC1
#define BF_CPM_CLKGR_MSC1_V(e) BF_CPM_CLKGR_MSC1(BV_CPM_CLKGR_MSC1__##e)
#define BFM_CPM_CLKGR_MSC1_V(v) BM_CPM_CLKGR_MSC1
#define BP_CPM_CLKGR_MSC0 4
#define BM_CPM_CLKGR_MSC0 0x10
#define BF_CPM_CLKGR_MSC0(v) (((v) & 0x1) << 4)
#define BFM_CPM_CLKGR_MSC0(v) BM_CPM_CLKGR_MSC0
#define BF_CPM_CLKGR_MSC0_V(e) BF_CPM_CLKGR_MSC0(BV_CPM_CLKGR_MSC0__##e)
#define BFM_CPM_CLKGR_MSC0_V(v) BM_CPM_CLKGR_MSC0
#define BP_CPM_CLKGR_OTG 3
#define BM_CPM_CLKGR_OTG 0x8
#define BF_CPM_CLKGR_OTG(v) (((v) & 0x1) << 3)
#define BFM_CPM_CLKGR_OTG(v) BM_CPM_CLKGR_OTG
#define BF_CPM_CLKGR_OTG_V(e) BF_CPM_CLKGR_OTG(BV_CPM_CLKGR_OTG__##e)
#define BFM_CPM_CLKGR_OTG_V(v) BM_CPM_CLKGR_OTG
#define BP_CPM_CLKGR_SFC 2
#define BM_CPM_CLKGR_SFC 0x4
#define BF_CPM_CLKGR_SFC(v) (((v) & 0x1) << 2)
#define BFM_CPM_CLKGR_SFC(v) BM_CPM_CLKGR_SFC
#define BF_CPM_CLKGR_SFC_V(e) BF_CPM_CLKGR_SFC(BV_CPM_CLKGR_SFC__##e)
#define BFM_CPM_CLKGR_SFC_V(v) BM_CPM_CLKGR_SFC
#define BP_CPM_CLKGR_EFUSE 1
#define BM_CPM_CLKGR_EFUSE 0x2
#define BF_CPM_CLKGR_EFUSE(v) (((v) & 0x1) << 1)
#define BFM_CPM_CLKGR_EFUSE(v) BM_CPM_CLKGR_EFUSE
#define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e)
#define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE
#define REG_CPM_OPCR jz_reg(CPM_OPCR)
#define JA_CPM_OPCR (0xb0000000 + 0x24)
#define JT_CPM_OPCR JIO_32_RW
#define JN_CPM_OPCR CPM_OPCR
#define JI_CPM_OPCR
#define BP_CPM_OPCR_O1ST 8
#define BM_CPM_OPCR_O1ST 0xfff00
#define BF_CPM_OPCR_O1ST(v) (((v) & 0xfff) << 8)
#define BFM_CPM_OPCR_O1ST(v) BM_CPM_OPCR_O1ST
#define BF_CPM_OPCR_O1ST_V(e) BF_CPM_OPCR_O1ST(BV_CPM_OPCR_O1ST__##e)
#define BFM_CPM_OPCR_O1ST_V(v) BM_CPM_OPCR_O1ST
#define BP_CPM_OPCR_IDLE_DIS 31
#define BM_CPM_OPCR_IDLE_DIS 0x80000000
#define BF_CPM_OPCR_IDLE_DIS(v) (((v) & 0x1) << 31)
#define BFM_CPM_OPCR_IDLE_DIS(v) BM_CPM_OPCR_IDLE_DIS
#define BF_CPM_OPCR_IDLE_DIS_V(e) BF_CPM_OPCR_IDLE_DIS(BV_CPM_OPCR_IDLE_DIS__##e)
#define BFM_CPM_OPCR_IDLE_DIS_V(v) BM_CPM_OPCR_IDLE_DIS
#define BP_CPM_OPCR_MASK_INT 30
#define BM_CPM_OPCR_MASK_INT 0x40000000
#define BF_CPM_OPCR_MASK_INT(v) (((v) & 0x1) << 30)
#define BFM_CPM_OPCR_MASK_INT(v) BM_CPM_OPCR_MASK_INT
#define BF_CPM_OPCR_MASK_INT_V(e) BF_CPM_OPCR_MASK_INT(BV_CPM_OPCR_MASK_INT__##e)
#define BFM_CPM_OPCR_MASK_INT_V(v) BM_CPM_OPCR_MASK_INT
#define BP_CPM_OPCR_MASK_VPU 29
#define BM_CPM_OPCR_MASK_VPU 0x20000000
#define BF_CPM_OPCR_MASK_VPU(v) (((v) & 0x1) << 29)
#define BFM_CPM_OPCR_MASK_VPU(v) BM_CPM_OPCR_MASK_VPU
#define BF_CPM_OPCR_MASK_VPU_V(e) BF_CPM_OPCR_MASK_VPU(BV_CPM_OPCR_MASK_VPU__##e)
#define BFM_CPM_OPCR_MASK_VPU_V(v) BM_CPM_OPCR_MASK_VPU
#define BP_CPM_OPCR_GATE_SCLK_A_BUS 28
#define BM_CPM_OPCR_GATE_SCLK_A_BUS 0x10000000
#define BF_CPM_OPCR_GATE_SCLK_A_BUS(v) (((v) & 0x1) << 28)
#define BFM_CPM_OPCR_GATE_SCLK_A_BUS(v) BM_CPM_OPCR_GATE_SCLK_A_BUS
#define BF_CPM_OPCR_GATE_SCLK_A_BUS_V(e) BF_CPM_OPCR_GATE_SCLK_A_BUS(BV_CPM_OPCR_GATE_SCLK_A_BUS__##e)
#define BFM_CPM_OPCR_GATE_SCLK_A_BUS_V(v) BM_CPM_OPCR_GATE_SCLK_A_BUS
#define BP_CPM_OPCR_L2C_PD 25
#define BM_CPM_OPCR_L2C_PD 0x2000000
#define BF_CPM_OPCR_L2C_PD(v) (((v) & 0x1) << 25)
#define BFM_CPM_OPCR_L2C_PD(v) BM_CPM_OPCR_L2C_PD
#define BF_CPM_OPCR_L2C_PD_V(e) BF_CPM_OPCR_L2C_PD(BV_CPM_OPCR_L2C_PD__##e)
#define BFM_CPM_OPCR_L2C_PD_V(v) BM_CPM_OPCR_L2C_PD
#define BP_CPM_OPCR_REQ_MODE 24
#define BM_CPM_OPCR_REQ_MODE 0x1000000
#define BF_CPM_OPCR_REQ_MODE(v) (((v) & 0x1) << 24)
#define BFM_CPM_OPCR_REQ_MODE(v) BM_CPM_OPCR_REQ_MODE
#define BF_CPM_OPCR_REQ_MODE_V(e) BF_CPM_OPCR_REQ_MODE(BV_CPM_OPCR_REQ_MODE__##e)
#define BFM_CPM_OPCR_REQ_MODE_V(v) BM_CPM_OPCR_REQ_MODE
#define BP_CPM_OPCR_GATE_USBPHY_CLK 23
#define BM_CPM_OPCR_GATE_USBPHY_CLK 0x800000
#define BF_CPM_OPCR_GATE_USBPHY_CLK(v) (((v) & 0x1) << 23)
#define BFM_CPM_OPCR_GATE_USBPHY_CLK(v) BM_CPM_OPCR_GATE_USBPHY_CLK
#define BF_CPM_OPCR_GATE_USBPHY_CLK_V(e) BF_CPM_OPCR_GATE_USBPHY_CLK(BV_CPM_OPCR_GATE_USBPHY_CLK__##e)
#define BFM_CPM_OPCR_GATE_USBPHY_CLK_V(v) BM_CPM_OPCR_GATE_USBPHY_CLK
#define BP_CPM_OPCR_DIS_STOP_MUX 22
#define BM_CPM_OPCR_DIS_STOP_MUX 0x400000
#define BF_CPM_OPCR_DIS_STOP_MUX(v) (((v) & 0x1) << 22)
#define BFM_CPM_OPCR_DIS_STOP_MUX(v) BM_CPM_OPCR_DIS_STOP_MUX
#define BF_CPM_OPCR_DIS_STOP_MUX_V(e) BF_CPM_OPCR_DIS_STOP_MUX(BV_CPM_OPCR_DIS_STOP_MUX__##e)
#define BFM_CPM_OPCR_DIS_STOP_MUX_V(v) BM_CPM_OPCR_DIS_STOP_MUX
#define BP_CPM_OPCR_SPENDN0 7
#define BM_CPM_OPCR_SPENDN0 0x80
#define BF_CPM_OPCR_SPENDN0(v) (((v) & 0x1) << 7)
#define BFM_CPM_OPCR_SPENDN0(v) BM_CPM_OPCR_SPENDN0
#define BF_CPM_OPCR_SPENDN0_V(e) BF_CPM_OPCR_SPENDN0(BV_CPM_OPCR_SPENDN0__##e)
#define BFM_CPM_OPCR_SPENDN0_V(v) BM_CPM_OPCR_SPENDN0
#define BP_CPM_OPCR_SPENDN1 6
#define BM_CPM_OPCR_SPENDN1 0x40
#define BF_CPM_OPCR_SPENDN1(v) (((v) & 0x1) << 6)
#define BFM_CPM_OPCR_SPENDN1(v) BM_CPM_OPCR_SPENDN1
#define BF_CPM_OPCR_SPENDN1_V(e) BF_CPM_OPCR_SPENDN1(BV_CPM_OPCR_SPENDN1__##e)
#define BFM_CPM_OPCR_SPENDN1_V(v) BM_CPM_OPCR_SPENDN1
#define BP_CPM_OPCR_CPU_MODE 5
#define BM_CPM_OPCR_CPU_MODE 0x20
#define BF_CPM_OPCR_CPU_MODE(v) (((v) & 0x1) << 5)
#define BFM_CPM_OPCR_CPU_MODE(v) BM_CPM_OPCR_CPU_MODE
#define BF_CPM_OPCR_CPU_MODE_V(e) BF_CPM_OPCR_CPU_MODE(BV_CPM_OPCR_CPU_MODE__##e)
#define BFM_CPM_OPCR_CPU_MODE_V(v) BM_CPM_OPCR_CPU_MODE
#define BP_CPM_OPCR_O1SE 4
#define BM_CPM_OPCR_O1SE 0x10
#define BF_CPM_OPCR_O1SE(v) (((v) & 0x1) << 4)
#define BFM_CPM_OPCR_O1SE(v) BM_CPM_OPCR_O1SE
#define BF_CPM_OPCR_O1SE_V(e) BF_CPM_OPCR_O1SE(BV_CPM_OPCR_O1SE__##e)
#define BFM_CPM_OPCR_O1SE_V(v) BM_CPM_OPCR_O1SE
#define BP_CPM_OPCR_PD 3
#define BM_CPM_OPCR_PD 0x8
#define BF_CPM_OPCR_PD(v) (((v) & 0x1) << 3)
#define BFM_CPM_OPCR_PD(v) BM_CPM_OPCR_PD
#define BF_CPM_OPCR_PD_V(e) BF_CPM_OPCR_PD(BV_CPM_OPCR_PD__##e)
#define BFM_CPM_OPCR_PD_V(v) BM_CPM_OPCR_PD
#define BP_CPM_OPCR_ERCS 2
#define BM_CPM_OPCR_ERCS 0x4
#define BF_CPM_OPCR_ERCS(v) (((v) & 0x1) << 2)
#define BFM_CPM_OPCR_ERCS(v) BM_CPM_OPCR_ERCS
#define BF_CPM_OPCR_ERCS_V(e) BF_CPM_OPCR_ERCS(BV_CPM_OPCR_ERCS__##e)
#define BFM_CPM_OPCR_ERCS_V(v) BM_CPM_OPCR_ERCS
#define BP_CPM_OPCR_BUS_MODE 1
#define BM_CPM_OPCR_BUS_MODE 0x2
#define BF_CPM_OPCR_BUS_MODE(v) (((v) & 0x1) << 1)
#define BFM_CPM_OPCR_BUS_MODE(v) BM_CPM_OPCR_BUS_MODE
#define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e)
#define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE
#endif /* __HEADERGEN_CPM_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_DDRC_H__
#define __HEADERGEN_DDRC_H__
#include "macro.h"
#define REG_DDRC_STATUS jz_reg(DDRC_STATUS)
#define JA_DDRC_STATUS (0xb34f0000 + 0x0)
#define JT_DDRC_STATUS JIO_32_RW
#define JN_DDRC_STATUS DDRC_STATUS
#define JI_DDRC_STATUS
#define REG_DDRC_CFG jz_reg(DDRC_CFG)
#define JA_DDRC_CFG (0xb34f0000 + 0x4)
#define JT_DDRC_CFG JIO_32_RW
#define JN_DDRC_CFG DDRC_CFG
#define JI_DDRC_CFG
#define REG_DDRC_CTRL jz_reg(DDRC_CTRL)
#define JA_DDRC_CTRL (0xb34f0000 + 0x8)
#define JT_DDRC_CTRL JIO_32_RW
#define JN_DDRC_CTRL DDRC_CTRL
#define JI_DDRC_CTRL
#define REG_DDRC_TIMING1 jz_reg(DDRC_TIMING1)
#define JA_DDRC_TIMING1 (0xb34f0000 + 0x60)
#define JT_DDRC_TIMING1 JIO_32_RW
#define JN_DDRC_TIMING1 DDRC_TIMING1
#define JI_DDRC_TIMING1
#define REG_DDRC_TIMING2 jz_reg(DDRC_TIMING2)
#define JA_DDRC_TIMING2 (0xb34f0000 + 0x64)
#define JT_DDRC_TIMING2 JIO_32_RW
#define JN_DDRC_TIMING2 DDRC_TIMING2
#define JI_DDRC_TIMING2
#define REG_DDRC_TIMING3 jz_reg(DDRC_TIMING3)
#define JA_DDRC_TIMING3 (0xb34f0000 + 0x68)
#define JT_DDRC_TIMING3 JIO_32_RW
#define JN_DDRC_TIMING3 DDRC_TIMING3
#define JI_DDRC_TIMING3
#define REG_DDRC_TIMING4 jz_reg(DDRC_TIMING4)
#define JA_DDRC_TIMING4 (0xb34f0000 + 0x6c)
#define JT_DDRC_TIMING4 JIO_32_RW
#define JN_DDRC_TIMING4 DDRC_TIMING4
#define JI_DDRC_TIMING4
#define REG_DDRC_TIMING5 jz_reg(DDRC_TIMING5)
#define JA_DDRC_TIMING5 (0xb34f0000 + 0x70)
#define JT_DDRC_TIMING5 JIO_32_RW
#define JN_DDRC_TIMING5 DDRC_TIMING5
#define JI_DDRC_TIMING5
#define REG_DDRC_TIMING6 jz_reg(DDRC_TIMING6)
#define JA_DDRC_TIMING6 (0xb34f0000 + 0x74)
#define JT_DDRC_TIMING6 JIO_32_RW
#define JN_DDRC_TIMING6 DDRC_TIMING6
#define JI_DDRC_TIMING6
#define REG_DDRC_REFCNT jz_reg(DDRC_REFCNT)
#define JA_DDRC_REFCNT (0xb34f0000 + 0x18)
#define JT_DDRC_REFCNT JIO_32_RW
#define JN_DDRC_REFCNT DDRC_REFCNT
#define JI_DDRC_REFCNT
#define REG_DDRC_MMAP0 jz_reg(DDRC_MMAP0)
#define JA_DDRC_MMAP0 (0xb34f0000 + 0x24)
#define JT_DDRC_MMAP0 JIO_32_RW
#define JN_DDRC_MMAP0 DDRC_MMAP0
#define JI_DDRC_MMAP0
#define REG_DDRC_MMAP1 jz_reg(DDRC_MMAP1)
#define JA_DDRC_MMAP1 (0xb34f0000 + 0x28)
#define JT_DDRC_MMAP1 JIO_32_RW
#define JN_DDRC_MMAP1 DDRC_MMAP1
#define JI_DDRC_MMAP1
#define REG_DDRC_DLP jz_reg(DDRC_DLP)
#define JA_DDRC_DLP (0xb34f0000 + 0xbc)
#define JT_DDRC_DLP JIO_32_RW
#define JN_DDRC_DLP DDRC_DLP
#define JI_DDRC_DLP
#define REG_DDRC_REMAP1 jz_reg(DDRC_REMAP1)
#define JA_DDRC_REMAP1 (0xb34f0000 + 0x9c)
#define JT_DDRC_REMAP1 JIO_32_RW
#define JN_DDRC_REMAP1 DDRC_REMAP1
#define JI_DDRC_REMAP1
#define REG_DDRC_REMAP2 jz_reg(DDRC_REMAP2)
#define JA_DDRC_REMAP2 (0xb34f0000 + 0xa0)
#define JT_DDRC_REMAP2 JIO_32_RW
#define JN_DDRC_REMAP2 DDRC_REMAP2
#define JI_DDRC_REMAP2
#define REG_DDRC_REMAP3 jz_reg(DDRC_REMAP3)
#define JA_DDRC_REMAP3 (0xb34f0000 + 0xa4)
#define JT_DDRC_REMAP3 JIO_32_RW
#define JN_DDRC_REMAP3 DDRC_REMAP3
#define JI_DDRC_REMAP3
#define REG_DDRC_REMAP4 jz_reg(DDRC_REMAP4)
#define JA_DDRC_REMAP4 (0xb34f0000 + 0xa8)
#define JT_DDRC_REMAP4 JIO_32_RW
#define JN_DDRC_REMAP4 DDRC_REMAP4
#define JI_DDRC_REMAP4
#define REG_DDRC_REMAP5 jz_reg(DDRC_REMAP5)
#define JA_DDRC_REMAP5 (0xb34f0000 + 0xac)
#define JT_DDRC_REMAP5 JIO_32_RW
#define JN_DDRC_REMAP5 DDRC_REMAP5
#define JI_DDRC_REMAP5
#define REG_DDRC_AUTOSR_CNT jz_reg(DDRC_AUTOSR_CNT)
#define JA_DDRC_AUTOSR_CNT (0xb34f0000 + 0x308)
#define JT_DDRC_AUTOSR_CNT JIO_32_RW
#define JN_DDRC_AUTOSR_CNT DDRC_AUTOSR_CNT
#define JI_DDRC_AUTOSR_CNT
#define REG_DDRC_AUTOSR_EN jz_reg(DDRC_AUTOSR_EN)
#define JA_DDRC_AUTOSR_EN (0xb34f0000 + 0x304)
#define JT_DDRC_AUTOSR_EN JIO_32_RW
#define JN_DDRC_AUTOSR_EN DDRC_AUTOSR_EN
#define JI_DDRC_AUTOSR_EN
#endif /* __HEADERGEN_DDRC_H__*/

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firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_DDRC_APB_H__
#define __HEADERGEN_DDRC_APB_H__
#include "macro.h"
#define REG_DDRC_APB_CLKSTP_CFG jz_reg(DDRC_APB_CLKSTP_CFG)
#define JA_DDRC_APB_CLKSTP_CFG (0xb3012000 + 0x68)
#define JT_DDRC_APB_CLKSTP_CFG JIO_32_RW
#define JN_DDRC_APB_CLKSTP_CFG DDRC_APB_CLKSTP_CFG
#define JI_DDRC_APB_CLKSTP_CFG
#define REG_DDRC_APB_PHYRST_CFG jz_reg(DDRC_APB_PHYRST_CFG)
#define JA_DDRC_APB_PHYRST_CFG (0xb3012000 + 0x80)
#define JT_DDRC_APB_PHYRST_CFG JIO_32_RW
#define JN_DDRC_APB_PHYRST_CFG DDRC_APB_PHYRST_CFG
#define JI_DDRC_APB_PHYRST_CFG
#endif /* __HEADERGEN_DDRC_APB_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_DDRPHY_H__
#define __HEADERGEN_DDRPHY_H__
#include "macro.h"
#define REG_DDRPHY_PIR jz_reg(DDRPHY_PIR)
#define JA_DDRPHY_PIR (0xb3011000 + 0x4)
#define JT_DDRPHY_PIR JIO_32_RW
#define JN_DDRPHY_PIR DDRPHY_PIR
#define JI_DDRPHY_PIR
#define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR)
#define JA_DDRPHY_PGCR (0xb3011000 + 0x8)
#define JT_DDRPHY_PGCR JIO_32_RW
#define JN_DDRPHY_PGCR DDRPHY_PGCR
#define JI_DDRPHY_PGCR
#define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR)
#define JA_DDRPHY_PGSR (0xb3011000 + 0xc)
#define JT_DDRPHY_PGSR JIO_32_RW
#define JN_DDRPHY_PGSR DDRPHY_PGSR
#define JI_DDRPHY_PGSR
#define REG_DDRPHY_DLLGCR jz_reg(DDRPHY_DLLGCR)
#define JA_DDRPHY_DLLGCR (0xb3011000 + 0x10)
#define JT_DDRPHY_DLLGCR JIO_32_RW
#define JN_DDRPHY_DLLGCR DDRPHY_DLLGCR
#define JI_DDRPHY_DLLGCR
#define REG_DDRPHY_ACDLLCR jz_reg(DDRPHY_ACDLLCR)
#define JA_DDRPHY_ACDLLCR (0xb3011000 + 0x14)
#define JT_DDRPHY_ACDLLCR JIO_32_RW
#define JN_DDRPHY_ACDLLCR DDRPHY_ACDLLCR
#define JI_DDRPHY_ACDLLCR
#define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0)
#define JA_DDRPHY_PTR0 (0xb3011000 + 0x18)
#define JT_DDRPHY_PTR0 JIO_32_RW
#define JN_DDRPHY_PTR0 DDRPHY_PTR0
#define JI_DDRPHY_PTR0
#define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1)
#define JA_DDRPHY_PTR1 (0xb3011000 + 0x1c)
#define JT_DDRPHY_PTR1 JIO_32_RW
#define JN_DDRPHY_PTR1 DDRPHY_PTR1
#define JI_DDRPHY_PTR1
#define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2)
#define JA_DDRPHY_PTR2 (0xb3011000 + 0x20)
#define JT_DDRPHY_PTR2 JIO_32_RW
#define JN_DDRPHY_PTR2 DDRPHY_PTR2
#define JI_DDRPHY_PTR2
#define REG_DDRPHY_ACIOCR jz_reg(DDRPHY_ACIOCR)
#define JA_DDRPHY_ACIOCR (0xb3011000 + 0x24)
#define JT_DDRPHY_ACIOCR JIO_32_RW
#define JN_DDRPHY_ACIOCR DDRPHY_ACIOCR
#define JI_DDRPHY_ACIOCR
#define REG_DDRPHY_DXCCR jz_reg(DDRPHY_DXCCR)
#define JA_DDRPHY_DXCCR (0xb3011000 + 0x28)
#define JT_DDRPHY_DXCCR JIO_32_RW
#define JN_DDRPHY_DXCCR DDRPHY_DXCCR
#define JI_DDRPHY_DXCCR
#define REG_DDRPHY_DSGCR jz_reg(DDRPHY_DSGCR)
#define JA_DDRPHY_DSGCR (0xb3011000 + 0x2c)
#define JT_DDRPHY_DSGCR JIO_32_RW
#define JN_DDRPHY_DSGCR DDRPHY_DSGCR
#define JI_DDRPHY_DSGCR
#define REG_DDRPHY_DCR jz_reg(DDRPHY_DCR)
#define JA_DDRPHY_DCR (0xb3011000 + 0x30)
#define JT_DDRPHY_DCR JIO_32_RW
#define JN_DDRPHY_DCR DDRPHY_DCR
#define JI_DDRPHY_DCR
#define REG_DDRPHY_DTPR0 jz_reg(DDRPHY_DTPR0)
#define JA_DDRPHY_DTPR0 (0xb3011000 + 0x34)
#define JT_DDRPHY_DTPR0 JIO_32_RW
#define JN_DDRPHY_DTPR0 DDRPHY_DTPR0
#define JI_DDRPHY_DTPR0
#define REG_DDRPHY_DTPR1 jz_reg(DDRPHY_DTPR1)
#define JA_DDRPHY_DTPR1 (0xb3011000 + 0x38)
#define JT_DDRPHY_DTPR1 JIO_32_RW
#define JN_DDRPHY_DTPR1 DDRPHY_DTPR1
#define JI_DDRPHY_DTPR1
#define REG_DDRPHY_DTPR2 jz_reg(DDRPHY_DTPR2)
#define JA_DDRPHY_DTPR2 (0xb3011000 + 0x3c)
#define JT_DDRPHY_DTPR2 JIO_32_RW
#define JN_DDRPHY_DTPR2 DDRPHY_DTPR2
#define JI_DDRPHY_DTPR2
#define REG_DDRPHY_MR0 jz_reg(DDRPHY_MR0)
#define JA_DDRPHY_MR0 (0xb3011000 + 0x40)
#define JT_DDRPHY_MR0 JIO_32_RW
#define JN_DDRPHY_MR0 DDRPHY_MR0
#define JI_DDRPHY_MR0
#define REG_DDRPHY_MR1 jz_reg(DDRPHY_MR1)
#define JA_DDRPHY_MR1 (0xb3011000 + 0x44)
#define JT_DDRPHY_MR1 JIO_32_RW
#define JN_DDRPHY_MR1 DDRPHY_MR1
#define JI_DDRPHY_MR1
#define REG_DDRPHY_MR2 jz_reg(DDRPHY_MR2)
#define JA_DDRPHY_MR2 (0xb3011000 + 0x48)
#define JT_DDRPHY_MR2 JIO_32_RW
#define JN_DDRPHY_MR2 DDRPHY_MR2
#define JI_DDRPHY_MR2
#define REG_DDRPHY_MR3 jz_reg(DDRPHY_MR3)
#define JA_DDRPHY_MR3 (0xb3011000 + 0x4c)
#define JT_DDRPHY_MR3 JIO_32_RW
#define JN_DDRPHY_MR3 DDRPHY_MR3
#define JI_DDRPHY_MR3
#define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR)
#define JA_DDRPHY_DTAR (0xb3011000 + 0x54)
#define JT_DDRPHY_DTAR JIO_32_RW
#define JN_DDRPHY_DTAR DDRPHY_DTAR
#define JI_DDRPHY_DTAR
#define REG_DDRPHY_DXGCR(_n1) jz_reg(DDRPHY_DXGCR(_n1))
#define JA_DDRPHY_DXGCR(_n1) (0xb3011000 + 0x1c0 + (_n1) * 0x40)
#define JT_DDRPHY_DXGCR(_n1) JIO_32_RW
#define JN_DDRPHY_DXGCR(_n1) DDRPHY_DXGCR
#define JI_DDRPHY_DXGCR(_n1) (_n1)
#endif /* __HEADERGEN_DDRPHY_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_DMA_H__
#define __HEADERGEN_DMA_H__
#include "macro.h"
#define REG_DMA_CTRL jz_reg(DMA_CTRL)
#define JA_DMA_CTRL (0xb3421000 + 0x0)
#define JT_DMA_CTRL JIO_32_RW
#define JN_DMA_CTRL DMA_CTRL
#define JI_DMA_CTRL
#define BP_DMA_CTRL_FMSC 31
#define BM_DMA_CTRL_FMSC 0x80000000
#define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31)
#define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC
#define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e)
#define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC
#define BP_DMA_CTRL_FSSI 30
#define BM_DMA_CTRL_FSSI 0x40000000
#define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30)
#define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI
#define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e)
#define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI
#define BP_DMA_CTRL_FTSSI 29
#define BM_DMA_CTRL_FTSSI 0x20000000
#define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29)
#define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI
#define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e)
#define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI
#define BP_DMA_CTRL_FUART 28
#define BM_DMA_CTRL_FUART 0x10000000
#define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28)
#define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART
#define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e)
#define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART
#define BP_DMA_CTRL_FAIC 27
#define BM_DMA_CTRL_FAIC 0x8000000
#define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27)
#define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC
#define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e)
#define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC
#define BP_DMA_CTRL_HALT 3
#define BM_DMA_CTRL_HALT 0x8
#define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3)
#define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT
#define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e)
#define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT
#define BP_DMA_CTRL_AR 2
#define BM_DMA_CTRL_AR 0x4
#define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2)
#define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR
#define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e)
#define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR
#define BP_DMA_CTRL_ENABLE 0
#define BM_DMA_CTRL_ENABLE 0x1
#define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0)
#define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE
#define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e)
#define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE
#define REG_DMA_IRQP jz_reg(DMA_IRQP)
#define JA_DMA_IRQP (0xb3421000 + 0x4)
#define JT_DMA_IRQP JIO_32_RW
#define JN_DMA_IRQP DMA_IRQP
#define JI_DMA_IRQP
#define REG_DMA_DB jz_reg(DMA_DB)
#define JA_DMA_DB (0xb3421000 + 0x8)
#define JT_DMA_DB JIO_32_RW
#define JN_DMA_DB DMA_DB
#define JI_DMA_DB
#define REG_DMA_DB_SET jz_reg(DMA_DB_SET)
#define JA_DMA_DB_SET (JA_DMA_DB + 0x4)
#define JT_DMA_DB_SET JIO_32_WO
#define JN_DMA_DB_SET DMA_DB
#define JI_DMA_DB_SET
#define REG_DMA_DIP jz_reg(DMA_DIP)
#define JA_DMA_DIP (0xb3421000 + 0x10)
#define JT_DMA_DIP JIO_32_RW
#define JN_DMA_DIP DMA_DIP
#define JI_DMA_DIP
#define REG_DMA_DIC jz_reg(DMA_DIC)
#define JA_DMA_DIC (0xb3421000 + 0x14)
#define JT_DMA_DIC JIO_32_RW
#define JN_DMA_DIC DMA_DIC
#define JI_DMA_DIC
#endif /* __HEADERGEN_DMA_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_DMA_CHN_H__
#define __HEADERGEN_DMA_CHN_H__
#include "macro.h"
#define REG_DMA_CHN_SA(_n1) jz_reg(DMA_CHN_SA(_n1))
#define JA_DMA_CHN_SA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x0)
#define JT_DMA_CHN_SA(_n1) JIO_32_RW
#define JN_DMA_CHN_SA(_n1) DMA_CHN_SA
#define JI_DMA_CHN_SA(_n1) (_n1)
#define REG_DMA_CHN_TA(_n1) jz_reg(DMA_CHN_TA(_n1))
#define JA_DMA_CHN_TA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x4)
#define JT_DMA_CHN_TA(_n1) JIO_32_RW
#define JN_DMA_CHN_TA(_n1) DMA_CHN_TA
#define JI_DMA_CHN_TA(_n1) (_n1)
#define REG_DMA_CHN_TC(_n1) jz_reg(DMA_CHN_TC(_n1))
#define JA_DMA_CHN_TC(_n1) (0xb3420000 + (_n1) * 0x20 + 0x8)
#define JT_DMA_CHN_TC(_n1) JIO_32_RW
#define JN_DMA_CHN_TC(_n1) DMA_CHN_TC
#define JI_DMA_CHN_TC(_n1) (_n1)
#define BP_DMA_CHN_TC_DOA 24
#define BM_DMA_CHN_TC_DOA 0xff000000
#define BF_DMA_CHN_TC_DOA(v) (((v) & 0xff) << 24)
#define BFM_DMA_CHN_TC_DOA(v) BM_DMA_CHN_TC_DOA
#define BF_DMA_CHN_TC_DOA_V(e) BF_DMA_CHN_TC_DOA(BV_DMA_CHN_TC_DOA__##e)
#define BFM_DMA_CHN_TC_DOA_V(v) BM_DMA_CHN_TC_DOA
#define BP_DMA_CHN_TC_CNT 0
#define BM_DMA_CHN_TC_CNT 0xffffff
#define BF_DMA_CHN_TC_CNT(v) (((v) & 0xffffff) << 0)
#define BFM_DMA_CHN_TC_CNT(v) BM_DMA_CHN_TC_CNT
#define BF_DMA_CHN_TC_CNT_V(e) BF_DMA_CHN_TC_CNT(BV_DMA_CHN_TC_CNT__##e)
#define BFM_DMA_CHN_TC_CNT_V(v) BM_DMA_CHN_TC_CNT
#define REG_DMA_CHN_RT(_n1) jz_reg(DMA_CHN_RT(_n1))
#define JA_DMA_CHN_RT(_n1) (0xb3420000 + (_n1) * 0x20 + 0xc)
#define JT_DMA_CHN_RT(_n1) JIO_32_RW
#define JN_DMA_CHN_RT(_n1) DMA_CHN_RT
#define JI_DMA_CHN_RT(_n1) (_n1)
#define BP_DMA_CHN_RT_TYPE 0
#define BM_DMA_CHN_RT_TYPE 0x3f
#define BV_DMA_CHN_RT_TYPE__DMIC_RX 0x5
#define BV_DMA_CHN_RT_TYPE__I2S_TX 0x6
#define BV_DMA_CHN_RT_TYPE__I2S_RX 0x7
#define BV_DMA_CHN_RT_TYPE__AUTO 0x8
#define BV_DMA_CHN_RT_TYPE__UART2_TX 0x10
#define BV_DMA_CHN_RT_TYPE__UART2_RX 0x11
#define BV_DMA_CHN_RT_TYPE__UART1_TX 0x12
#define BV_DMA_CHN_RT_TYPE__UART1_RX 0x13
#define BV_DMA_CHN_RT_TYPE__UART0_TX 0x14
#define BV_DMA_CHN_RT_TYPE__UART0_RX 0x15
#define BV_DMA_CHN_RT_TYPE__SSI_TX 0x16
#define BV_DMA_CHN_RT_TYPE__SSI_RX 0x17
#define BV_DMA_CHN_RT_TYPE__MSC0_TX 0x1a
#define BV_DMA_CHN_RT_TYPE__MSC0_RX 0x1b
#define BV_DMA_CHN_RT_TYPE__MSC1_TX 0x1c
#define BV_DMA_CHN_RT_TYPE__MSC1_RX 0x1d
#define BV_DMA_CHN_RT_TYPE__PCM_TX 0x20
#define BV_DMA_CHN_RT_TYPE__PCM_RX 0x21
#define BV_DMA_CHN_RT_TYPE__I2C0_TX 0x24
#define BV_DMA_CHN_RT_TYPE__I2C0_RX 0x25
#define BV_DMA_CHN_RT_TYPE__I2C1_TX 0x26
#define BV_DMA_CHN_RT_TYPE__I2C1_RX 0x27
#define BV_DMA_CHN_RT_TYPE__I2C2_TX 0x28
#define BV_DMA_CHN_RT_TYPE__I2C2_RX 0x29
#define BF_DMA_CHN_RT_TYPE(v) (((v) & 0x3f) << 0)
#define BFM_DMA_CHN_RT_TYPE(v) BM_DMA_CHN_RT_TYPE
#define BF_DMA_CHN_RT_TYPE_V(e) BF_DMA_CHN_RT_TYPE(BV_DMA_CHN_RT_TYPE__##e)
#define BFM_DMA_CHN_RT_TYPE_V(v) BM_DMA_CHN_RT_TYPE
#define REG_DMA_CHN_CS(_n1) jz_reg(DMA_CHN_CS(_n1))
#define JA_DMA_CHN_CS(_n1) (0xb3420000 + (_n1) * 0x20 + 0x10)
#define JT_DMA_CHN_CS(_n1) JIO_32_RW
#define JN_DMA_CHN_CS(_n1) DMA_CHN_CS
#define JI_DMA_CHN_CS(_n1) (_n1)
#define BP_DMA_CHN_CS_CDOA 8
#define BM_DMA_CHN_CS_CDOA 0xff00
#define BF_DMA_CHN_CS_CDOA(v) (((v) & 0xff) << 8)
#define BFM_DMA_CHN_CS_CDOA(v) BM_DMA_CHN_CS_CDOA
#define BF_DMA_CHN_CS_CDOA_V(e) BF_DMA_CHN_CS_CDOA(BV_DMA_CHN_CS_CDOA__##e)
#define BFM_DMA_CHN_CS_CDOA_V(v) BM_DMA_CHN_CS_CDOA
#define BP_DMA_CHN_CS_NDES 31
#define BM_DMA_CHN_CS_NDES 0x80000000
#define BF_DMA_CHN_CS_NDES(v) (((v) & 0x1) << 31)
#define BFM_DMA_CHN_CS_NDES(v) BM_DMA_CHN_CS_NDES
#define BF_DMA_CHN_CS_NDES_V(e) BF_DMA_CHN_CS_NDES(BV_DMA_CHN_CS_NDES__##e)
#define BFM_DMA_CHN_CS_NDES_V(v) BM_DMA_CHN_CS_NDES
#define BP_DMA_CHN_CS_DES8 30
#define BM_DMA_CHN_CS_DES8 0x40000000
#define BF_DMA_CHN_CS_DES8(v) (((v) & 0x1) << 30)
#define BFM_DMA_CHN_CS_DES8(v) BM_DMA_CHN_CS_DES8
#define BF_DMA_CHN_CS_DES8_V(e) BF_DMA_CHN_CS_DES8(BV_DMA_CHN_CS_DES8__##e)
#define BFM_DMA_CHN_CS_DES8_V(v) BM_DMA_CHN_CS_DES8
#define BP_DMA_CHN_CS_AR 4
#define BM_DMA_CHN_CS_AR 0x10
#define BF_DMA_CHN_CS_AR(v) (((v) & 0x1) << 4)
#define BFM_DMA_CHN_CS_AR(v) BM_DMA_CHN_CS_AR
#define BF_DMA_CHN_CS_AR_V(e) BF_DMA_CHN_CS_AR(BV_DMA_CHN_CS_AR__##e)
#define BFM_DMA_CHN_CS_AR_V(v) BM_DMA_CHN_CS_AR
#define BP_DMA_CHN_CS_TT 3
#define BM_DMA_CHN_CS_TT 0x8
#define BF_DMA_CHN_CS_TT(v) (((v) & 0x1) << 3)
#define BFM_DMA_CHN_CS_TT(v) BM_DMA_CHN_CS_TT
#define BF_DMA_CHN_CS_TT_V(e) BF_DMA_CHN_CS_TT(BV_DMA_CHN_CS_TT__##e)
#define BFM_DMA_CHN_CS_TT_V(v) BM_DMA_CHN_CS_TT
#define BP_DMA_CHN_CS_HLT 2
#define BM_DMA_CHN_CS_HLT 0x4
#define BF_DMA_CHN_CS_HLT(v) (((v) & 0x1) << 2)
#define BFM_DMA_CHN_CS_HLT(v) BM_DMA_CHN_CS_HLT
#define BF_DMA_CHN_CS_HLT_V(e) BF_DMA_CHN_CS_HLT(BV_DMA_CHN_CS_HLT__##e)
#define BFM_DMA_CHN_CS_HLT_V(v) BM_DMA_CHN_CS_HLT
#define BP_DMA_CHN_CS_CTE 0
#define BM_DMA_CHN_CS_CTE 0x1
#define BF_DMA_CHN_CS_CTE(v) (((v) & 0x1) << 0)
#define BFM_DMA_CHN_CS_CTE(v) BM_DMA_CHN_CS_CTE
#define BF_DMA_CHN_CS_CTE_V(e) BF_DMA_CHN_CS_CTE(BV_DMA_CHN_CS_CTE__##e)
#define BFM_DMA_CHN_CS_CTE_V(v) BM_DMA_CHN_CS_CTE
#define REG_DMA_CHN_CM(_n1) jz_reg(DMA_CHN_CM(_n1))
#define JA_DMA_CHN_CM(_n1) (0xb3420000 + (_n1) * 0x20 + 0x14)
#define JT_DMA_CHN_CM(_n1) JIO_32_RW
#define JN_DMA_CHN_CM(_n1) DMA_CHN_CM
#define JI_DMA_CHN_CM(_n1) (_n1)
#define BP_DMA_CHN_CM_RDIL 16
#define BM_DMA_CHN_CM_RDIL 0xf0000
#define BF_DMA_CHN_CM_RDIL(v) (((v) & 0xf) << 16)
#define BFM_DMA_CHN_CM_RDIL(v) BM_DMA_CHN_CM_RDIL
#define BF_DMA_CHN_CM_RDIL_V(e) BF_DMA_CHN_CM_RDIL(BV_DMA_CHN_CM_RDIL__##e)
#define BFM_DMA_CHN_CM_RDIL_V(v) BM_DMA_CHN_CM_RDIL
#define BP_DMA_CHN_CM_SP 14
#define BM_DMA_CHN_CM_SP 0xc000
#define BV_DMA_CHN_CM_SP__32BIT 0x0
#define BV_DMA_CHN_CM_SP__8BIT 0x1
#define BV_DMA_CHN_CM_SP__16BIT 0x2
#define BF_DMA_CHN_CM_SP(v) (((v) & 0x3) << 14)
#define BFM_DMA_CHN_CM_SP(v) BM_DMA_CHN_CM_SP
#define BF_DMA_CHN_CM_SP_V(e) BF_DMA_CHN_CM_SP(BV_DMA_CHN_CM_SP__##e)
#define BFM_DMA_CHN_CM_SP_V(v) BM_DMA_CHN_CM_SP
#define BP_DMA_CHN_CM_DP 12
#define BM_DMA_CHN_CM_DP 0x3000
#define BV_DMA_CHN_CM_DP__32BIT 0x0
#define BV_DMA_CHN_CM_DP__8BIT 0x1
#define BV_DMA_CHN_CM_DP__16BIT 0x2
#define BF_DMA_CHN_CM_DP(v) (((v) & 0x3) << 12)
#define BFM_DMA_CHN_CM_DP(v) BM_DMA_CHN_CM_DP
#define BF_DMA_CHN_CM_DP_V(e) BF_DMA_CHN_CM_DP(BV_DMA_CHN_CM_DP__##e)
#define BFM_DMA_CHN_CM_DP_V(v) BM_DMA_CHN_CM_DP
#define BP_DMA_CHN_CM_TSZ 8
#define BM_DMA_CHN_CM_TSZ 0x700
#define BV_DMA_CHN_CM_TSZ__32BIT 0x0
#define BV_DMA_CHN_CM_TSZ__8BIT 0x1
#define BV_DMA_CHN_CM_TSZ__16BIT 0x2
#define BV_DMA_CHN_CM_TSZ__16BYTE 0x3
#define BV_DMA_CHN_CM_TSZ__32BYTE 0x4
#define BV_DMA_CHN_CM_TSZ__64BYTE 0x5
#define BV_DMA_CHN_CM_TSZ__128BYTE 0x6
#define BV_DMA_CHN_CM_TSZ__AUTO 0x7
#define BF_DMA_CHN_CM_TSZ(v) (((v) & 0x7) << 8)
#define BFM_DMA_CHN_CM_TSZ(v) BM_DMA_CHN_CM_TSZ
#define BF_DMA_CHN_CM_TSZ_V(e) BF_DMA_CHN_CM_TSZ(BV_DMA_CHN_CM_TSZ__##e)
#define BFM_DMA_CHN_CM_TSZ_V(v) BM_DMA_CHN_CM_TSZ
#define BP_DMA_CHN_CM_SAI 23
#define BM_DMA_CHN_CM_SAI 0x800000
#define BF_DMA_CHN_CM_SAI(v) (((v) & 0x1) << 23)
#define BFM_DMA_CHN_CM_SAI(v) BM_DMA_CHN_CM_SAI
#define BF_DMA_CHN_CM_SAI_V(e) BF_DMA_CHN_CM_SAI(BV_DMA_CHN_CM_SAI__##e)
#define BFM_DMA_CHN_CM_SAI_V(v) BM_DMA_CHN_CM_SAI
#define BP_DMA_CHN_CM_DAI 22
#define BM_DMA_CHN_CM_DAI 0x400000
#define BF_DMA_CHN_CM_DAI(v) (((v) & 0x1) << 22)
#define BFM_DMA_CHN_CM_DAI(v) BM_DMA_CHN_CM_DAI
#define BF_DMA_CHN_CM_DAI_V(e) BF_DMA_CHN_CM_DAI(BV_DMA_CHN_CM_DAI__##e)
#define BFM_DMA_CHN_CM_DAI_V(v) BM_DMA_CHN_CM_DAI
#define BP_DMA_CHN_CM_STDE 2
#define BM_DMA_CHN_CM_STDE 0x4
#define BF_DMA_CHN_CM_STDE(v) (((v) & 0x1) << 2)
#define BFM_DMA_CHN_CM_STDE(v) BM_DMA_CHN_CM_STDE
#define BF_DMA_CHN_CM_STDE_V(e) BF_DMA_CHN_CM_STDE(BV_DMA_CHN_CM_STDE__##e)
#define BFM_DMA_CHN_CM_STDE_V(v) BM_DMA_CHN_CM_STDE
#define BP_DMA_CHN_CM_TIE 1
#define BM_DMA_CHN_CM_TIE 0x2
#define BF_DMA_CHN_CM_TIE(v) (((v) & 0x1) << 1)
#define BFM_DMA_CHN_CM_TIE(v) BM_DMA_CHN_CM_TIE
#define BF_DMA_CHN_CM_TIE_V(e) BF_DMA_CHN_CM_TIE(BV_DMA_CHN_CM_TIE__##e)
#define BFM_DMA_CHN_CM_TIE_V(v) BM_DMA_CHN_CM_TIE
#define BP_DMA_CHN_CM_LINK 0
#define BM_DMA_CHN_CM_LINK 0x1
#define BF_DMA_CHN_CM_LINK(v) (((v) & 0x1) << 0)
#define BFM_DMA_CHN_CM_LINK(v) BM_DMA_CHN_CM_LINK
#define BF_DMA_CHN_CM_LINK_V(e) BF_DMA_CHN_CM_LINK(BV_DMA_CHN_CM_LINK__##e)
#define BFM_DMA_CHN_CM_LINK_V(v) BM_DMA_CHN_CM_LINK
#define REG_DMA_CHN_DA(_n1) jz_reg(DMA_CHN_DA(_n1))
#define JA_DMA_CHN_DA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x18)
#define JT_DMA_CHN_DA(_n1) JIO_32_RW
#define JN_DMA_CHN_DA(_n1) DMA_CHN_DA
#define JI_DMA_CHN_DA(_n1) (_n1)
#define BP_DMA_CHN_DA_DBA 12
#define BM_DMA_CHN_DA_DBA 0xfffff000
#define BF_DMA_CHN_DA_DBA(v) (((v) & 0xfffff) << 12)
#define BFM_DMA_CHN_DA_DBA(v) BM_DMA_CHN_DA_DBA
#define BF_DMA_CHN_DA_DBA_V(e) BF_DMA_CHN_DA_DBA(BV_DMA_CHN_DA_DBA__##e)
#define BFM_DMA_CHN_DA_DBA_V(v) BM_DMA_CHN_DA_DBA
#define BP_DMA_CHN_DA_DOA 4
#define BM_DMA_CHN_DA_DOA 0xff0
#define BF_DMA_CHN_DA_DOA(v) (((v) & 0xff) << 4)
#define BFM_DMA_CHN_DA_DOA(v) BM_DMA_CHN_DA_DOA
#define BF_DMA_CHN_DA_DOA_V(e) BF_DMA_CHN_DA_DOA(BV_DMA_CHN_DA_DOA__##e)
#define BFM_DMA_CHN_DA_DOA_V(v) BM_DMA_CHN_DA_DOA
#define REG_DMA_CHN_SD(_n1) jz_reg(DMA_CHN_SD(_n1))
#define JA_DMA_CHN_SD(_n1) (0xb3420000 + (_n1) * 0x20 + 0x1c)
#define JT_DMA_CHN_SD(_n1) JIO_32_RW
#define JN_DMA_CHN_SD(_n1) DMA_CHN_SD
#define JI_DMA_CHN_SD(_n1) (_n1)
#define BP_DMA_CHN_SD_TSD 16
#define BM_DMA_CHN_SD_TSD 0xffff0000
#define BF_DMA_CHN_SD_TSD(v) (((v) & 0xffff) << 16)
#define BFM_DMA_CHN_SD_TSD(v) BM_DMA_CHN_SD_TSD
#define BF_DMA_CHN_SD_TSD_V(e) BF_DMA_CHN_SD_TSD(BV_DMA_CHN_SD_TSD__##e)
#define BFM_DMA_CHN_SD_TSD_V(v) BM_DMA_CHN_SD_TSD
#define BP_DMA_CHN_SD_SSD 0
#define BM_DMA_CHN_SD_SSD 0xffff
#define BF_DMA_CHN_SD_SSD(v) (((v) & 0xffff) << 0)
#define BFM_DMA_CHN_SD_SSD(v) BM_DMA_CHN_SD_SSD
#define BF_DMA_CHN_SD_SSD_V(e) BF_DMA_CHN_SD_SSD(BV_DMA_CHN_SD_SSD__##e)
#define BFM_DMA_CHN_SD_SSD_V(v) BM_DMA_CHN_SD_SSD
#endif /* __HEADERGEN_DMA_CHN_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_GPIO_H__
#define __HEADERGEN_GPIO_H__
#include "macro.h"
#define REG_GPIO_C_GLITCH_CFG0 jz_reg(GPIO_C_GLITCH_CFG0)
#define JA_GPIO_C_GLITCH_CFG0 (0xb0010000 + 0x200 + 0x800)
#define JT_GPIO_C_GLITCH_CFG0 JIO_32_RW
#define JN_GPIO_C_GLITCH_CFG0 GPIO_C_GLITCH_CFG0
#define JI_GPIO_C_GLITCH_CFG0
#define REG_GPIO_C_GLITCH_CFG0_SET jz_reg(GPIO_C_GLITCH_CFG0_SET)
#define JA_GPIO_C_GLITCH_CFG0_SET (JA_GPIO_C_GLITCH_CFG0 + 0x4)
#define JT_GPIO_C_GLITCH_CFG0_SET JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG0_SET GPIO_C_GLITCH_CFG0
#define JI_GPIO_C_GLITCH_CFG0_SET
#define REG_GPIO_C_GLITCH_CFG0_CLR jz_reg(GPIO_C_GLITCH_CFG0_CLR)
#define JA_GPIO_C_GLITCH_CFG0_CLR (JA_GPIO_C_GLITCH_CFG0 + 0x8)
#define JT_GPIO_C_GLITCH_CFG0_CLR JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG0_CLR GPIO_C_GLITCH_CFG0
#define JI_GPIO_C_GLITCH_CFG0_CLR
#define REG_GPIO_C_GLITCH_CFG1 jz_reg(GPIO_C_GLITCH_CFG1)
#define JA_GPIO_C_GLITCH_CFG1 (0xb0010000 + 0x200 + 0x810)
#define JT_GPIO_C_GLITCH_CFG1 JIO_32_RW
#define JN_GPIO_C_GLITCH_CFG1 GPIO_C_GLITCH_CFG1
#define JI_GPIO_C_GLITCH_CFG1
#define REG_GPIO_C_GLITCH_CFG1_SET jz_reg(GPIO_C_GLITCH_CFG1_SET)
#define JA_GPIO_C_GLITCH_CFG1_SET (JA_GPIO_C_GLITCH_CFG1 + 0x4)
#define JT_GPIO_C_GLITCH_CFG1_SET JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG1_SET GPIO_C_GLITCH_CFG1
#define JI_GPIO_C_GLITCH_CFG1_SET
#define REG_GPIO_C_GLITCH_CFG1_CLR jz_reg(GPIO_C_GLITCH_CFG1_CLR)
#define JA_GPIO_C_GLITCH_CFG1_CLR (JA_GPIO_C_GLITCH_CFG1 + 0x8)
#define JT_GPIO_C_GLITCH_CFG1_CLR JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG1_CLR GPIO_C_GLITCH_CFG1
#define JI_GPIO_C_GLITCH_CFG1_CLR
#define REG_GPIO_C_GLITCH_CFG2 jz_reg(GPIO_C_GLITCH_CFG2)
#define JA_GPIO_C_GLITCH_CFG2 (0xb0010000 + 0x200 + 0x820)
#define JT_GPIO_C_GLITCH_CFG2 JIO_32_RW
#define JN_GPIO_C_GLITCH_CFG2 GPIO_C_GLITCH_CFG2
#define JI_GPIO_C_GLITCH_CFG2
#define REG_GPIO_C_GLITCH_CFG2_SET jz_reg(GPIO_C_GLITCH_CFG2_SET)
#define JA_GPIO_C_GLITCH_CFG2_SET (JA_GPIO_C_GLITCH_CFG2 + 0x4)
#define JT_GPIO_C_GLITCH_CFG2_SET JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG2_SET GPIO_C_GLITCH_CFG2
#define JI_GPIO_C_GLITCH_CFG2_SET
#define REG_GPIO_C_GLITCH_CFG2_CLR jz_reg(GPIO_C_GLITCH_CFG2_CLR)
#define JA_GPIO_C_GLITCH_CFG2_CLR (JA_GPIO_C_GLITCH_CFG2 + 0x8)
#define JT_GPIO_C_GLITCH_CFG2_CLR JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG2_CLR GPIO_C_GLITCH_CFG2
#define JI_GPIO_C_GLITCH_CFG2_CLR
#define REG_GPIO_C_GLITCH_CFG3 jz_reg(GPIO_C_GLITCH_CFG3)
#define JA_GPIO_C_GLITCH_CFG3 (0xb0010000 + 0x200 + 0x830)
#define JT_GPIO_C_GLITCH_CFG3 JIO_32_RW
#define JN_GPIO_C_GLITCH_CFG3 GPIO_C_GLITCH_CFG3
#define JI_GPIO_C_GLITCH_CFG3
#define REG_GPIO_C_GLITCH_CFG3_SET jz_reg(GPIO_C_GLITCH_CFG3_SET)
#define JA_GPIO_C_GLITCH_CFG3_SET (JA_GPIO_C_GLITCH_CFG3 + 0x4)
#define JT_GPIO_C_GLITCH_CFG3_SET JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG3_SET GPIO_C_GLITCH_CFG3
#define JI_GPIO_C_GLITCH_CFG3_SET
#define REG_GPIO_C_GLITCH_CFG3_CLR jz_reg(GPIO_C_GLITCH_CFG3_CLR)
#define JA_GPIO_C_GLITCH_CFG3_CLR (JA_GPIO_C_GLITCH_CFG3 + 0x8)
#define JT_GPIO_C_GLITCH_CFG3_CLR JIO_32_WO
#define JN_GPIO_C_GLITCH_CFG3_CLR GPIO_C_GLITCH_CFG3
#define JI_GPIO_C_GLITCH_CFG3_CLR
#define REG_GPIO_PIN(_n1) jz_reg(GPIO_PIN(_n1))
#define JA_GPIO_PIN(_n1) (0xb0010000 + 0x0 + (_n1) * 0x100)
#define JT_GPIO_PIN(_n1) JIO_32_RW
#define JN_GPIO_PIN(_n1) GPIO_PIN
#define JI_GPIO_PIN(_n1) (_n1)
#define REG_GPIO_INT(_n1) jz_reg(GPIO_INT(_n1))
#define JA_GPIO_INT(_n1) (0xb0010000 + 0x10 + (_n1) * 0x100)
#define JT_GPIO_INT(_n1) JIO_32_RW
#define JN_GPIO_INT(_n1) GPIO_INT
#define JI_GPIO_INT(_n1) (_n1)
#define REG_GPIO_INT_SET(_n1) jz_reg(GPIO_INT_SET(_n1))
#define JA_GPIO_INT_SET(_n1) (JA_GPIO_INT(_n1) + 0x4)
#define JT_GPIO_INT_SET(_n1) JIO_32_WO
#define JN_GPIO_INT_SET(_n1) GPIO_INT
#define JI_GPIO_INT_SET(_n1) (_n1)
#define REG_GPIO_INT_CLR(_n1) jz_reg(GPIO_INT_CLR(_n1))
#define JA_GPIO_INT_CLR(_n1) (JA_GPIO_INT(_n1) + 0x8)
#define JT_GPIO_INT_CLR(_n1) JIO_32_WO
#define JN_GPIO_INT_CLR(_n1) GPIO_INT
#define JI_GPIO_INT_CLR(_n1) (_n1)
#define REG_GPIO_MSK(_n1) jz_reg(GPIO_MSK(_n1))
#define JA_GPIO_MSK(_n1) (0xb0010000 + 0x20 + (_n1) * 0x100)
#define JT_GPIO_MSK(_n1) JIO_32_RW
#define JN_GPIO_MSK(_n1) GPIO_MSK
#define JI_GPIO_MSK(_n1) (_n1)
#define REG_GPIO_MSK_SET(_n1) jz_reg(GPIO_MSK_SET(_n1))
#define JA_GPIO_MSK_SET(_n1) (JA_GPIO_MSK(_n1) + 0x4)
#define JT_GPIO_MSK_SET(_n1) JIO_32_WO
#define JN_GPIO_MSK_SET(_n1) GPIO_MSK
#define JI_GPIO_MSK_SET(_n1) (_n1)
#define REG_GPIO_MSK_CLR(_n1) jz_reg(GPIO_MSK_CLR(_n1))
#define JA_GPIO_MSK_CLR(_n1) (JA_GPIO_MSK(_n1) + 0x8)
#define JT_GPIO_MSK_CLR(_n1) JIO_32_WO
#define JN_GPIO_MSK_CLR(_n1) GPIO_MSK
#define JI_GPIO_MSK_CLR(_n1) (_n1)
#define REG_GPIO_PAT1(_n1) jz_reg(GPIO_PAT1(_n1))
#define JA_GPIO_PAT1(_n1) (0xb0010000 + 0x30 + (_n1) * 0x100)
#define JT_GPIO_PAT1(_n1) JIO_32_RW
#define JN_GPIO_PAT1(_n1) GPIO_PAT1
#define JI_GPIO_PAT1(_n1) (_n1)
#define REG_GPIO_PAT1_SET(_n1) jz_reg(GPIO_PAT1_SET(_n1))
#define JA_GPIO_PAT1_SET(_n1) (JA_GPIO_PAT1(_n1) + 0x4)
#define JT_GPIO_PAT1_SET(_n1) JIO_32_WO
#define JN_GPIO_PAT1_SET(_n1) GPIO_PAT1
#define JI_GPIO_PAT1_SET(_n1) (_n1)
#define REG_GPIO_PAT1_CLR(_n1) jz_reg(GPIO_PAT1_CLR(_n1))
#define JA_GPIO_PAT1_CLR(_n1) (JA_GPIO_PAT1(_n1) + 0x8)
#define JT_GPIO_PAT1_CLR(_n1) JIO_32_WO
#define JN_GPIO_PAT1_CLR(_n1) GPIO_PAT1
#define JI_GPIO_PAT1_CLR(_n1) (_n1)
#define REG_GPIO_PAT0(_n1) jz_reg(GPIO_PAT0(_n1))
#define JA_GPIO_PAT0(_n1) (0xb0010000 + 0x40 + (_n1) * 0x100)
#define JT_GPIO_PAT0(_n1) JIO_32_RW
#define JN_GPIO_PAT0(_n1) GPIO_PAT0
#define JI_GPIO_PAT0(_n1) (_n1)
#define REG_GPIO_PAT0_SET(_n1) jz_reg(GPIO_PAT0_SET(_n1))
#define JA_GPIO_PAT0_SET(_n1) (JA_GPIO_PAT0(_n1) + 0x4)
#define JT_GPIO_PAT0_SET(_n1) JIO_32_WO
#define JN_GPIO_PAT0_SET(_n1) GPIO_PAT0
#define JI_GPIO_PAT0_SET(_n1) (_n1)
#define REG_GPIO_PAT0_CLR(_n1) jz_reg(GPIO_PAT0_CLR(_n1))
#define JA_GPIO_PAT0_CLR(_n1) (JA_GPIO_PAT0(_n1) + 0x8)
#define JT_GPIO_PAT0_CLR(_n1) JIO_32_WO
#define JN_GPIO_PAT0_CLR(_n1) GPIO_PAT0
#define JI_GPIO_PAT0_CLR(_n1) (_n1)
#define REG_GPIO_FLAG(_n1) jz_reg(GPIO_FLAG(_n1))
#define JA_GPIO_FLAG(_n1) (0xb0010000 + 0x50 + (_n1) * 0x100)
#define JT_GPIO_FLAG(_n1) JIO_32_RW
#define JN_GPIO_FLAG(_n1) GPIO_FLAG
#define JI_GPIO_FLAG(_n1) (_n1)
#define REG_GPIO_FLAG_CLR(_n1) jz_reg(GPIO_FLAG_CLR(_n1))
#define JA_GPIO_FLAG_CLR(_n1) (JA_GPIO_FLAG(_n1) + 0x8)
#define JT_GPIO_FLAG_CLR(_n1) JIO_32_WO
#define JN_GPIO_FLAG_CLR(_n1) GPIO_FLAG
#define JI_GPIO_FLAG_CLR(_n1) (_n1)
#define REG_GPIO_PULL(_n1) jz_reg(GPIO_PULL(_n1))
#define JA_GPIO_PULL(_n1) (0xb0010000 + 0x70 + (_n1) * 0x100)
#define JT_GPIO_PULL(_n1) JIO_32_RW
#define JN_GPIO_PULL(_n1) GPIO_PULL
#define JI_GPIO_PULL(_n1) (_n1)
#define REG_GPIO_PULL_SET(_n1) jz_reg(GPIO_PULL_SET(_n1))
#define JA_GPIO_PULL_SET(_n1) (JA_GPIO_PULL(_n1) + 0x4)
#define JT_GPIO_PULL_SET(_n1) JIO_32_WO
#define JN_GPIO_PULL_SET(_n1) GPIO_PULL
#define JI_GPIO_PULL_SET(_n1) (_n1)
#define REG_GPIO_PULL_CLR(_n1) jz_reg(GPIO_PULL_CLR(_n1))
#define JA_GPIO_PULL_CLR(_n1) (JA_GPIO_PULL(_n1) + 0x8)
#define JT_GPIO_PULL_CLR(_n1) JIO_32_WO
#define JN_GPIO_PULL_CLR(_n1) GPIO_PULL
#define JI_GPIO_PULL_CLR(_n1) (_n1)
#define REG_GPIO_Z_GID2LD jz_reg(GPIO_Z_GID2LD)
#define JA_GPIO_Z_GID2LD (0xb0010000 + 0x7f0)
#define JT_GPIO_Z_GID2LD JIO_32_RW
#define JN_GPIO_Z_GID2LD GPIO_Z_GID2LD
#define JI_GPIO_Z_GID2LD
#endif /* __HEADERGEN_GPIO_H__*/

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firmware/target/mips/ingenic_x1000/x1000/i2c.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_I2C_H__
#define __HEADERGEN_I2C_H__
#include "macro.h"
#define REG_I2C_CON(_n1) jz_reg(I2C_CON(_n1))
#define JA_I2C_CON(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x0)
#define JT_I2C_CON(_n1) JIO_32_RW
#define JN_I2C_CON(_n1) I2C_CON
#define JI_I2C_CON(_n1) (_n1)
#define BP_I2C_CON_SPEED 1
#define BM_I2C_CON_SPEED 0x6
#define BV_I2C_CON_SPEED__100K 0x1
#define BV_I2C_CON_SPEED__400K 0x2
#define BF_I2C_CON_SPEED(v) (((v) & 0x3) << 1)
#define BFM_I2C_CON_SPEED(v) BM_I2C_CON_SPEED
#define BF_I2C_CON_SPEED_V(e) BF_I2C_CON_SPEED(BV_I2C_CON_SPEED__##e)
#define BFM_I2C_CON_SPEED_V(v) BM_I2C_CON_SPEED
#define BP_I2C_CON_SLVDIS 6
#define BM_I2C_CON_SLVDIS 0x40
#define BF_I2C_CON_SLVDIS(v) (((v) & 0x1) << 6)
#define BFM_I2C_CON_SLVDIS(v) BM_I2C_CON_SLVDIS
#define BF_I2C_CON_SLVDIS_V(e) BF_I2C_CON_SLVDIS(BV_I2C_CON_SLVDIS__##e)
#define BFM_I2C_CON_SLVDIS_V(v) BM_I2C_CON_SLVDIS
#define BP_I2C_CON_RESTART 5
#define BM_I2C_CON_RESTART 0x20
#define BF_I2C_CON_RESTART(v) (((v) & 0x1) << 5)
#define BFM_I2C_CON_RESTART(v) BM_I2C_CON_RESTART
#define BF_I2C_CON_RESTART_V(e) BF_I2C_CON_RESTART(BV_I2C_CON_RESTART__##e)
#define BFM_I2C_CON_RESTART_V(v) BM_I2C_CON_RESTART
#define BP_I2C_CON_MATP 4
#define BM_I2C_CON_MATP 0x10
#define BF_I2C_CON_MATP(v) (((v) & 0x1) << 4)
#define BFM_I2C_CON_MATP(v) BM_I2C_CON_MATP
#define BF_I2C_CON_MATP_V(e) BF_I2C_CON_MATP(BV_I2C_CON_MATP__##e)
#define BFM_I2C_CON_MATP_V(v) BM_I2C_CON_MATP
#define BP_I2C_CON_SATP 3
#define BM_I2C_CON_SATP 0x8
#define BF_I2C_CON_SATP(v) (((v) & 0x1) << 3)
#define BFM_I2C_CON_SATP(v) BM_I2C_CON_SATP
#define BF_I2C_CON_SATP_V(e) BF_I2C_CON_SATP(BV_I2C_CON_SATP__##e)
#define BFM_I2C_CON_SATP_V(v) BM_I2C_CON_SATP
#define BP_I2C_CON_MD 0
#define BM_I2C_CON_MD 0x1
#define BF_I2C_CON_MD(v) (((v) & 0x1) << 0)
#define BFM_I2C_CON_MD(v) BM_I2C_CON_MD
#define BF_I2C_CON_MD_V(e) BF_I2C_CON_MD(BV_I2C_CON_MD__##e)
#define BFM_I2C_CON_MD_V(v) BM_I2C_CON_MD
#define REG_I2C_DC(_n1) jz_reg(I2C_DC(_n1))
#define JA_I2C_DC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x10)
#define JT_I2C_DC(_n1) JIO_32_RW
#define JN_I2C_DC(_n1) I2C_DC
#define JI_I2C_DC(_n1) (_n1)
#define BP_I2C_DC_DAT 0
#define BM_I2C_DC_DAT 0xff
#define BF_I2C_DC_DAT(v) (((v) & 0xff) << 0)
#define BFM_I2C_DC_DAT(v) BM_I2C_DC_DAT
#define BF_I2C_DC_DAT_V(e) BF_I2C_DC_DAT(BV_I2C_DC_DAT__##e)
#define BFM_I2C_DC_DAT_V(v) BM_I2C_DC_DAT
#define BP_I2C_DC_RESTART 10
#define BM_I2C_DC_RESTART 0x400
#define BF_I2C_DC_RESTART(v) (((v) & 0x1) << 10)
#define BFM_I2C_DC_RESTART(v) BM_I2C_DC_RESTART
#define BF_I2C_DC_RESTART_V(e) BF_I2C_DC_RESTART(BV_I2C_DC_RESTART__##e)
#define BFM_I2C_DC_RESTART_V(v) BM_I2C_DC_RESTART
#define BP_I2C_DC_STOP 9
#define BM_I2C_DC_STOP 0x200
#define BF_I2C_DC_STOP(v) (((v) & 0x1) << 9)
#define BFM_I2C_DC_STOP(v) BM_I2C_DC_STOP
#define BF_I2C_DC_STOP_V(e) BF_I2C_DC_STOP(BV_I2C_DC_STOP__##e)
#define BFM_I2C_DC_STOP_V(v) BM_I2C_DC_STOP
#define BP_I2C_DC_CMD 8
#define BM_I2C_DC_CMD 0x100
#define BF_I2C_DC_CMD(v) (((v) & 0x1) << 8)
#define BFM_I2C_DC_CMD(v) BM_I2C_DC_CMD
#define BF_I2C_DC_CMD_V(e) BF_I2C_DC_CMD(BV_I2C_DC_CMD__##e)
#define BFM_I2C_DC_CMD_V(v) BM_I2C_DC_CMD
#define REG_I2C_INTST(_n1) jz_reg(I2C_INTST(_n1))
#define JA_I2C_INTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x2c)
#define JT_I2C_INTST(_n1) JIO_32_RW
#define JN_I2C_INTST(_n1) I2C_INTST
#define JI_I2C_INTST(_n1) (_n1)
#define BP_I2C_INTST_GC 11
#define BM_I2C_INTST_GC 0x800
#define BF_I2C_INTST_GC(v) (((v) & 0x1) << 11)
#define BFM_I2C_INTST_GC(v) BM_I2C_INTST_GC
#define BF_I2C_INTST_GC_V(e) BF_I2C_INTST_GC(BV_I2C_INTST_GC__##e)
#define BFM_I2C_INTST_GC_V(v) BM_I2C_INTST_GC
#define BP_I2C_INTST_STT 10
#define BM_I2C_INTST_STT 0x400
#define BF_I2C_INTST_STT(v) (((v) & 0x1) << 10)
#define BFM_I2C_INTST_STT(v) BM_I2C_INTST_STT
#define BF_I2C_INTST_STT_V(e) BF_I2C_INTST_STT(BV_I2C_INTST_STT__##e)
#define BFM_I2C_INTST_STT_V(v) BM_I2C_INTST_STT
#define BP_I2C_INTST_STP 9
#define BM_I2C_INTST_STP 0x200
#define BF_I2C_INTST_STP(v) (((v) & 0x1) << 9)
#define BFM_I2C_INTST_STP(v) BM_I2C_INTST_STP
#define BF_I2C_INTST_STP_V(e) BF_I2C_INTST_STP(BV_I2C_INTST_STP__##e)
#define BFM_I2C_INTST_STP_V(v) BM_I2C_INTST_STP
#define BP_I2C_INTST_ACT 8
#define BM_I2C_INTST_ACT 0x100
#define BF_I2C_INTST_ACT(v) (((v) & 0x1) << 8)
#define BFM_I2C_INTST_ACT(v) BM_I2C_INTST_ACT
#define BF_I2C_INTST_ACT_V(e) BF_I2C_INTST_ACT(BV_I2C_INTST_ACT__##e)
#define BFM_I2C_INTST_ACT_V(v) BM_I2C_INTST_ACT
#define BP_I2C_INTST_RXDN 7
#define BM_I2C_INTST_RXDN 0x80
#define BF_I2C_INTST_RXDN(v) (((v) & 0x1) << 7)
#define BFM_I2C_INTST_RXDN(v) BM_I2C_INTST_RXDN
#define BF_I2C_INTST_RXDN_V(e) BF_I2C_INTST_RXDN(BV_I2C_INTST_RXDN__##e)
#define BFM_I2C_INTST_RXDN_V(v) BM_I2C_INTST_RXDN
#define BP_I2C_INTST_TXABT 6
#define BM_I2C_INTST_TXABT 0x40
#define BF_I2C_INTST_TXABT(v) (((v) & 0x1) << 6)
#define BFM_I2C_INTST_TXABT(v) BM_I2C_INTST_TXABT
#define BF_I2C_INTST_TXABT_V(e) BF_I2C_INTST_TXABT(BV_I2C_INTST_TXABT__##e)
#define BFM_I2C_INTST_TXABT_V(v) BM_I2C_INTST_TXABT
#define BP_I2C_INTST_RDREQ 5
#define BM_I2C_INTST_RDREQ 0x20
#define BF_I2C_INTST_RDREQ(v) (((v) & 0x1) << 5)
#define BFM_I2C_INTST_RDREQ(v) BM_I2C_INTST_RDREQ
#define BF_I2C_INTST_RDREQ_V(e) BF_I2C_INTST_RDREQ(BV_I2C_INTST_RDREQ__##e)
#define BFM_I2C_INTST_RDREQ_V(v) BM_I2C_INTST_RDREQ
#define BP_I2C_INTST_TXEMP 4
#define BM_I2C_INTST_TXEMP 0x10
#define BF_I2C_INTST_TXEMP(v) (((v) & 0x1) << 4)
#define BFM_I2C_INTST_TXEMP(v) BM_I2C_INTST_TXEMP
#define BF_I2C_INTST_TXEMP_V(e) BF_I2C_INTST_TXEMP(BV_I2C_INTST_TXEMP__##e)
#define BFM_I2C_INTST_TXEMP_V(v) BM_I2C_INTST_TXEMP
#define BP_I2C_INTST_TXOF 3
#define BM_I2C_INTST_TXOF 0x8
#define BF_I2C_INTST_TXOF(v) (((v) & 0x1) << 3)
#define BFM_I2C_INTST_TXOF(v) BM_I2C_INTST_TXOF
#define BF_I2C_INTST_TXOF_V(e) BF_I2C_INTST_TXOF(BV_I2C_INTST_TXOF__##e)
#define BFM_I2C_INTST_TXOF_V(v) BM_I2C_INTST_TXOF
#define BP_I2C_INTST_RXFL 2
#define BM_I2C_INTST_RXFL 0x4
#define BF_I2C_INTST_RXFL(v) (((v) & 0x1) << 2)
#define BFM_I2C_INTST_RXFL(v) BM_I2C_INTST_RXFL
#define BF_I2C_INTST_RXFL_V(e) BF_I2C_INTST_RXFL(BV_I2C_INTST_RXFL__##e)
#define BFM_I2C_INTST_RXFL_V(v) BM_I2C_INTST_RXFL
#define BP_I2C_INTST_RXOF 1
#define BM_I2C_INTST_RXOF 0x2
#define BF_I2C_INTST_RXOF(v) (((v) & 0x1) << 1)
#define BFM_I2C_INTST_RXOF(v) BM_I2C_INTST_RXOF
#define BF_I2C_INTST_RXOF_V(e) BF_I2C_INTST_RXOF(BV_I2C_INTST_RXOF__##e)
#define BFM_I2C_INTST_RXOF_V(v) BM_I2C_INTST_RXOF
#define BP_I2C_INTST_RXUF 0
#define BM_I2C_INTST_RXUF 0x1
#define BF_I2C_INTST_RXUF(v) (((v) & 0x1) << 0)
#define BFM_I2C_INTST_RXUF(v) BM_I2C_INTST_RXUF
#define BF_I2C_INTST_RXUF_V(e) BF_I2C_INTST_RXUF(BV_I2C_INTST_RXUF__##e)
#define BFM_I2C_INTST_RXUF_V(v) BM_I2C_INTST_RXUF
#define REG_I2C_INTMSK(_n1) jz_reg(I2C_INTMSK(_n1))
#define JA_I2C_INTMSK(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x30)
#define JT_I2C_INTMSK(_n1) JIO_32_RW
#define JN_I2C_INTMSK(_n1) I2C_INTMSK
#define JI_I2C_INTMSK(_n1) (_n1)
#define BP_I2C_INTMSK_GC 11
#define BM_I2C_INTMSK_GC 0x800
#define BF_I2C_INTMSK_GC(v) (((v) & 0x1) << 11)
#define BFM_I2C_INTMSK_GC(v) BM_I2C_INTMSK_GC
#define BF_I2C_INTMSK_GC_V(e) BF_I2C_INTMSK_GC(BV_I2C_INTMSK_GC__##e)
#define BFM_I2C_INTMSK_GC_V(v) BM_I2C_INTMSK_GC
#define BP_I2C_INTMSK_STT 10
#define BM_I2C_INTMSK_STT 0x400
#define BF_I2C_INTMSK_STT(v) (((v) & 0x1) << 10)
#define BFM_I2C_INTMSK_STT(v) BM_I2C_INTMSK_STT
#define BF_I2C_INTMSK_STT_V(e) BF_I2C_INTMSK_STT(BV_I2C_INTMSK_STT__##e)
#define BFM_I2C_INTMSK_STT_V(v) BM_I2C_INTMSK_STT
#define BP_I2C_INTMSK_STP 9
#define BM_I2C_INTMSK_STP 0x200
#define BF_I2C_INTMSK_STP(v) (((v) & 0x1) << 9)
#define BFM_I2C_INTMSK_STP(v) BM_I2C_INTMSK_STP
#define BF_I2C_INTMSK_STP_V(e) BF_I2C_INTMSK_STP(BV_I2C_INTMSK_STP__##e)
#define BFM_I2C_INTMSK_STP_V(v) BM_I2C_INTMSK_STP
#define BP_I2C_INTMSK_ACT 8
#define BM_I2C_INTMSK_ACT 0x100
#define BF_I2C_INTMSK_ACT(v) (((v) & 0x1) << 8)
#define BFM_I2C_INTMSK_ACT(v) BM_I2C_INTMSK_ACT
#define BF_I2C_INTMSK_ACT_V(e) BF_I2C_INTMSK_ACT(BV_I2C_INTMSK_ACT__##e)
#define BFM_I2C_INTMSK_ACT_V(v) BM_I2C_INTMSK_ACT
#define BP_I2C_INTMSK_RXDN 7
#define BM_I2C_INTMSK_RXDN 0x80
#define BF_I2C_INTMSK_RXDN(v) (((v) & 0x1) << 7)
#define BFM_I2C_INTMSK_RXDN(v) BM_I2C_INTMSK_RXDN
#define BF_I2C_INTMSK_RXDN_V(e) BF_I2C_INTMSK_RXDN(BV_I2C_INTMSK_RXDN__##e)
#define BFM_I2C_INTMSK_RXDN_V(v) BM_I2C_INTMSK_RXDN
#define BP_I2C_INTMSK_TXABT 6
#define BM_I2C_INTMSK_TXABT 0x40
#define BF_I2C_INTMSK_TXABT(v) (((v) & 0x1) << 6)
#define BFM_I2C_INTMSK_TXABT(v) BM_I2C_INTMSK_TXABT
#define BF_I2C_INTMSK_TXABT_V(e) BF_I2C_INTMSK_TXABT(BV_I2C_INTMSK_TXABT__##e)
#define BFM_I2C_INTMSK_TXABT_V(v) BM_I2C_INTMSK_TXABT
#define BP_I2C_INTMSK_RDREQ 5
#define BM_I2C_INTMSK_RDREQ 0x20
#define BF_I2C_INTMSK_RDREQ(v) (((v) & 0x1) << 5)
#define BFM_I2C_INTMSK_RDREQ(v) BM_I2C_INTMSK_RDREQ
#define BF_I2C_INTMSK_RDREQ_V(e) BF_I2C_INTMSK_RDREQ(BV_I2C_INTMSK_RDREQ__##e)
#define BFM_I2C_INTMSK_RDREQ_V(v) BM_I2C_INTMSK_RDREQ
#define BP_I2C_INTMSK_TXEMP 4
#define BM_I2C_INTMSK_TXEMP 0x10
#define BF_I2C_INTMSK_TXEMP(v) (((v) & 0x1) << 4)
#define BFM_I2C_INTMSK_TXEMP(v) BM_I2C_INTMSK_TXEMP
#define BF_I2C_INTMSK_TXEMP_V(e) BF_I2C_INTMSK_TXEMP(BV_I2C_INTMSK_TXEMP__##e)
#define BFM_I2C_INTMSK_TXEMP_V(v) BM_I2C_INTMSK_TXEMP
#define BP_I2C_INTMSK_TXOF 3
#define BM_I2C_INTMSK_TXOF 0x8
#define BF_I2C_INTMSK_TXOF(v) (((v) & 0x1) << 3)
#define BFM_I2C_INTMSK_TXOF(v) BM_I2C_INTMSK_TXOF
#define BF_I2C_INTMSK_TXOF_V(e) BF_I2C_INTMSK_TXOF(BV_I2C_INTMSK_TXOF__##e)
#define BFM_I2C_INTMSK_TXOF_V(v) BM_I2C_INTMSK_TXOF
#define BP_I2C_INTMSK_RXFL 2
#define BM_I2C_INTMSK_RXFL 0x4
#define BF_I2C_INTMSK_RXFL(v) (((v) & 0x1) << 2)
#define BFM_I2C_INTMSK_RXFL(v) BM_I2C_INTMSK_RXFL
#define BF_I2C_INTMSK_RXFL_V(e) BF_I2C_INTMSK_RXFL(BV_I2C_INTMSK_RXFL__##e)
#define BFM_I2C_INTMSK_RXFL_V(v) BM_I2C_INTMSK_RXFL
#define BP_I2C_INTMSK_RXOF 1
#define BM_I2C_INTMSK_RXOF 0x2
#define BF_I2C_INTMSK_RXOF(v) (((v) & 0x1) << 1)
#define BFM_I2C_INTMSK_RXOF(v) BM_I2C_INTMSK_RXOF
#define BF_I2C_INTMSK_RXOF_V(e) BF_I2C_INTMSK_RXOF(BV_I2C_INTMSK_RXOF__##e)
#define BFM_I2C_INTMSK_RXOF_V(v) BM_I2C_INTMSK_RXOF
#define BP_I2C_INTMSK_RXUF 0
#define BM_I2C_INTMSK_RXUF 0x1
#define BF_I2C_INTMSK_RXUF(v) (((v) & 0x1) << 0)
#define BFM_I2C_INTMSK_RXUF(v) BM_I2C_INTMSK_RXUF
#define BF_I2C_INTMSK_RXUF_V(e) BF_I2C_INTMSK_RXUF(BV_I2C_INTMSK_RXUF__##e)
#define BFM_I2C_INTMSK_RXUF_V(v) BM_I2C_INTMSK_RXUF
#define REG_I2C_RINTST(_n1) jz_reg(I2C_RINTST(_n1))
#define JA_I2C_RINTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x34)
#define JT_I2C_RINTST(_n1) JIO_32_RW
#define JN_I2C_RINTST(_n1) I2C_RINTST
#define JI_I2C_RINTST(_n1) (_n1)
#define BP_I2C_RINTST_GC 11
#define BM_I2C_RINTST_GC 0x800
#define BF_I2C_RINTST_GC(v) (((v) & 0x1) << 11)
#define BFM_I2C_RINTST_GC(v) BM_I2C_RINTST_GC
#define BF_I2C_RINTST_GC_V(e) BF_I2C_RINTST_GC(BV_I2C_RINTST_GC__##e)
#define BFM_I2C_RINTST_GC_V(v) BM_I2C_RINTST_GC
#define BP_I2C_RINTST_STT 10
#define BM_I2C_RINTST_STT 0x400
#define BF_I2C_RINTST_STT(v) (((v) & 0x1) << 10)
#define BFM_I2C_RINTST_STT(v) BM_I2C_RINTST_STT
#define BF_I2C_RINTST_STT_V(e) BF_I2C_RINTST_STT(BV_I2C_RINTST_STT__##e)
#define BFM_I2C_RINTST_STT_V(v) BM_I2C_RINTST_STT
#define BP_I2C_RINTST_STP 9
#define BM_I2C_RINTST_STP 0x200
#define BF_I2C_RINTST_STP(v) (((v) & 0x1) << 9)
#define BFM_I2C_RINTST_STP(v) BM_I2C_RINTST_STP
#define BF_I2C_RINTST_STP_V(e) BF_I2C_RINTST_STP(BV_I2C_RINTST_STP__##e)
#define BFM_I2C_RINTST_STP_V(v) BM_I2C_RINTST_STP
#define BP_I2C_RINTST_ACT 8
#define BM_I2C_RINTST_ACT 0x100
#define BF_I2C_RINTST_ACT(v) (((v) & 0x1) << 8)
#define BFM_I2C_RINTST_ACT(v) BM_I2C_RINTST_ACT
#define BF_I2C_RINTST_ACT_V(e) BF_I2C_RINTST_ACT(BV_I2C_RINTST_ACT__##e)
#define BFM_I2C_RINTST_ACT_V(v) BM_I2C_RINTST_ACT
#define BP_I2C_RINTST_RXDN 7
#define BM_I2C_RINTST_RXDN 0x80
#define BF_I2C_RINTST_RXDN(v) (((v) & 0x1) << 7)
#define BFM_I2C_RINTST_RXDN(v) BM_I2C_RINTST_RXDN
#define BF_I2C_RINTST_RXDN_V(e) BF_I2C_RINTST_RXDN(BV_I2C_RINTST_RXDN__##e)
#define BFM_I2C_RINTST_RXDN_V(v) BM_I2C_RINTST_RXDN
#define BP_I2C_RINTST_TXABT 6
#define BM_I2C_RINTST_TXABT 0x40
#define BF_I2C_RINTST_TXABT(v) (((v) & 0x1) << 6)
#define BFM_I2C_RINTST_TXABT(v) BM_I2C_RINTST_TXABT
#define BF_I2C_RINTST_TXABT_V(e) BF_I2C_RINTST_TXABT(BV_I2C_RINTST_TXABT__##e)
#define BFM_I2C_RINTST_TXABT_V(v) BM_I2C_RINTST_TXABT
#define BP_I2C_RINTST_RDREQ 5
#define BM_I2C_RINTST_RDREQ 0x20
#define BF_I2C_RINTST_RDREQ(v) (((v) & 0x1) << 5)
#define BFM_I2C_RINTST_RDREQ(v) BM_I2C_RINTST_RDREQ
#define BF_I2C_RINTST_RDREQ_V(e) BF_I2C_RINTST_RDREQ(BV_I2C_RINTST_RDREQ__##e)
#define BFM_I2C_RINTST_RDREQ_V(v) BM_I2C_RINTST_RDREQ
#define BP_I2C_RINTST_TXEMP 4
#define BM_I2C_RINTST_TXEMP 0x10
#define BF_I2C_RINTST_TXEMP(v) (((v) & 0x1) << 4)
#define BFM_I2C_RINTST_TXEMP(v) BM_I2C_RINTST_TXEMP
#define BF_I2C_RINTST_TXEMP_V(e) BF_I2C_RINTST_TXEMP(BV_I2C_RINTST_TXEMP__##e)
#define BFM_I2C_RINTST_TXEMP_V(v) BM_I2C_RINTST_TXEMP
#define BP_I2C_RINTST_TXOF 3
#define BM_I2C_RINTST_TXOF 0x8
#define BF_I2C_RINTST_TXOF(v) (((v) & 0x1) << 3)
#define BFM_I2C_RINTST_TXOF(v) BM_I2C_RINTST_TXOF
#define BF_I2C_RINTST_TXOF_V(e) BF_I2C_RINTST_TXOF(BV_I2C_RINTST_TXOF__##e)
#define BFM_I2C_RINTST_TXOF_V(v) BM_I2C_RINTST_TXOF
#define BP_I2C_RINTST_RXFL 2
#define BM_I2C_RINTST_RXFL 0x4
#define BF_I2C_RINTST_RXFL(v) (((v) & 0x1) << 2)
#define BFM_I2C_RINTST_RXFL(v) BM_I2C_RINTST_RXFL
#define BF_I2C_RINTST_RXFL_V(e) BF_I2C_RINTST_RXFL(BV_I2C_RINTST_RXFL__##e)
#define BFM_I2C_RINTST_RXFL_V(v) BM_I2C_RINTST_RXFL
#define BP_I2C_RINTST_RXOF 1
#define BM_I2C_RINTST_RXOF 0x2
#define BF_I2C_RINTST_RXOF(v) (((v) & 0x1) << 1)
#define BFM_I2C_RINTST_RXOF(v) BM_I2C_RINTST_RXOF
#define BF_I2C_RINTST_RXOF_V(e) BF_I2C_RINTST_RXOF(BV_I2C_RINTST_RXOF__##e)
#define BFM_I2C_RINTST_RXOF_V(v) BM_I2C_RINTST_RXOF
#define BP_I2C_RINTST_RXUF 0
#define BM_I2C_RINTST_RXUF 0x1
#define BF_I2C_RINTST_RXUF(v) (((v) & 0x1) << 0)
#define BFM_I2C_RINTST_RXUF(v) BM_I2C_RINTST_RXUF
#define BF_I2C_RINTST_RXUF_V(e) BF_I2C_RINTST_RXUF(BV_I2C_RINTST_RXUF__##e)
#define BFM_I2C_RINTST_RXUF_V(v) BM_I2C_RINTST_RXUF
#define REG_I2C_ENABLE(_n1) jz_reg(I2C_ENABLE(_n1))
#define JA_I2C_ENABLE(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x6c)
#define JT_I2C_ENABLE(_n1) JIO_32_RW
#define JN_I2C_ENABLE(_n1) I2C_ENABLE
#define JI_I2C_ENABLE(_n1) (_n1)
#define BP_I2C_ENABLE_ABORT 1
#define BM_I2C_ENABLE_ABORT 0x2
#define BF_I2C_ENABLE_ABORT(v) (((v) & 0x1) << 1)
#define BFM_I2C_ENABLE_ABORT(v) BM_I2C_ENABLE_ABORT
#define BF_I2C_ENABLE_ABORT_V(e) BF_I2C_ENABLE_ABORT(BV_I2C_ENABLE_ABORT__##e)
#define BFM_I2C_ENABLE_ABORT_V(v) BM_I2C_ENABLE_ABORT
#define BP_I2C_ENABLE_ACTIVE 0
#define BM_I2C_ENABLE_ACTIVE 0x1
#define BF_I2C_ENABLE_ACTIVE(v) (((v) & 0x1) << 0)
#define BFM_I2C_ENABLE_ACTIVE(v) BM_I2C_ENABLE_ACTIVE
#define BF_I2C_ENABLE_ACTIVE_V(e) BF_I2C_ENABLE_ACTIVE(BV_I2C_ENABLE_ACTIVE__##e)
#define BFM_I2C_ENABLE_ACTIVE_V(v) BM_I2C_ENABLE_ACTIVE
#define REG_I2C_STATUS(_n1) jz_reg(I2C_STATUS(_n1))
#define JA_I2C_STATUS(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x70)
#define JT_I2C_STATUS(_n1) JIO_32_RW
#define JN_I2C_STATUS(_n1) I2C_STATUS
#define JI_I2C_STATUS(_n1) (_n1)
#define BP_I2C_STATUS_SLVACT 6
#define BM_I2C_STATUS_SLVACT 0x40
#define BF_I2C_STATUS_SLVACT(v) (((v) & 0x1) << 6)
#define BFM_I2C_STATUS_SLVACT(v) BM_I2C_STATUS_SLVACT
#define BF_I2C_STATUS_SLVACT_V(e) BF_I2C_STATUS_SLVACT(BV_I2C_STATUS_SLVACT__##e)
#define BFM_I2C_STATUS_SLVACT_V(v) BM_I2C_STATUS_SLVACT
#define BP_I2C_STATUS_MSTACT 5
#define BM_I2C_STATUS_MSTACT 0x20
#define BF_I2C_STATUS_MSTACT(v) (((v) & 0x1) << 5)
#define BFM_I2C_STATUS_MSTACT(v) BM_I2C_STATUS_MSTACT
#define BF_I2C_STATUS_MSTACT_V(e) BF_I2C_STATUS_MSTACT(BV_I2C_STATUS_MSTACT__##e)
#define BFM_I2C_STATUS_MSTACT_V(v) BM_I2C_STATUS_MSTACT
#define BP_I2C_STATUS_RFF 4
#define BM_I2C_STATUS_RFF 0x10
#define BF_I2C_STATUS_RFF(v) (((v) & 0x1) << 4)
#define BFM_I2C_STATUS_RFF(v) BM_I2C_STATUS_RFF
#define BF_I2C_STATUS_RFF_V(e) BF_I2C_STATUS_RFF(BV_I2C_STATUS_RFF__##e)
#define BFM_I2C_STATUS_RFF_V(v) BM_I2C_STATUS_RFF
#define BP_I2C_STATUS_RFNE 3
#define BM_I2C_STATUS_RFNE 0x8
#define BF_I2C_STATUS_RFNE(v) (((v) & 0x1) << 3)
#define BFM_I2C_STATUS_RFNE(v) BM_I2C_STATUS_RFNE
#define BF_I2C_STATUS_RFNE_V(e) BF_I2C_STATUS_RFNE(BV_I2C_STATUS_RFNE__##e)
#define BFM_I2C_STATUS_RFNE_V(v) BM_I2C_STATUS_RFNE
#define BP_I2C_STATUS_TFE 2
#define BM_I2C_STATUS_TFE 0x4
#define BF_I2C_STATUS_TFE(v) (((v) & 0x1) << 2)
#define BFM_I2C_STATUS_TFE(v) BM_I2C_STATUS_TFE
#define BF_I2C_STATUS_TFE_V(e) BF_I2C_STATUS_TFE(BV_I2C_STATUS_TFE__##e)
#define BFM_I2C_STATUS_TFE_V(v) BM_I2C_STATUS_TFE
#define BP_I2C_STATUS_TFNF 1
#define BM_I2C_STATUS_TFNF 0x2
#define BF_I2C_STATUS_TFNF(v) (((v) & 0x1) << 1)
#define BFM_I2C_STATUS_TFNF(v) BM_I2C_STATUS_TFNF
#define BF_I2C_STATUS_TFNF_V(e) BF_I2C_STATUS_TFNF(BV_I2C_STATUS_TFNF__##e)
#define BFM_I2C_STATUS_TFNF_V(v) BM_I2C_STATUS_TFNF
#define BP_I2C_STATUS_ACT 0
#define BM_I2C_STATUS_ACT 0x1
#define BF_I2C_STATUS_ACT(v) (((v) & 0x1) << 0)
#define BFM_I2C_STATUS_ACT(v) BM_I2C_STATUS_ACT
#define BF_I2C_STATUS_ACT_V(e) BF_I2C_STATUS_ACT(BV_I2C_STATUS_ACT__##e)
#define BFM_I2C_STATUS_ACT_V(v) BM_I2C_STATUS_ACT
#define REG_I2C_ENBST(_n1) jz_reg(I2C_ENBST(_n1))
#define JA_I2C_ENBST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x9c)
#define JT_I2C_ENBST(_n1) JIO_32_RW
#define JN_I2C_ENBST(_n1) I2C_ENBST
#define JI_I2C_ENBST(_n1) (_n1)
#define BP_I2C_ENBST_SLVRDLST 2
#define BM_I2C_ENBST_SLVRDLST 0x4
#define BF_I2C_ENBST_SLVRDLST(v) (((v) & 0x1) << 2)
#define BFM_I2C_ENBST_SLVRDLST(v) BM_I2C_ENBST_SLVRDLST
#define BF_I2C_ENBST_SLVRDLST_V(e) BF_I2C_ENBST_SLVRDLST(BV_I2C_ENBST_SLVRDLST__##e)
#define BFM_I2C_ENBST_SLVRDLST_V(v) BM_I2C_ENBST_SLVRDLST
#define BP_I2C_ENBST_SLVDISB 1
#define BM_I2C_ENBST_SLVDISB 0x2
#define BF_I2C_ENBST_SLVDISB(v) (((v) & 0x1) << 1)
#define BFM_I2C_ENBST_SLVDISB(v) BM_I2C_ENBST_SLVDISB
#define BF_I2C_ENBST_SLVDISB_V(e) BF_I2C_ENBST_SLVDISB(BV_I2C_ENBST_SLVDISB__##e)
#define BFM_I2C_ENBST_SLVDISB_V(v) BM_I2C_ENBST_SLVDISB
#define BP_I2C_ENBST_ACTIVE 0
#define BM_I2C_ENBST_ACTIVE 0x1
#define BF_I2C_ENBST_ACTIVE(v) (((v) & 0x1) << 0)
#define BFM_I2C_ENBST_ACTIVE(v) BM_I2C_ENBST_ACTIVE
#define BF_I2C_ENBST_ACTIVE_V(e) BF_I2C_ENBST_ACTIVE(BV_I2C_ENBST_ACTIVE__##e)
#define BFM_I2C_ENBST_ACTIVE_V(v) BM_I2C_ENBST_ACTIVE
#define REG_I2C_TAR(_n1) jz_reg(I2C_TAR(_n1))
#define JA_I2C_TAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4)
#define JT_I2C_TAR(_n1) JIO_32_RW
#define JN_I2C_TAR(_n1) I2C_TAR
#define JI_I2C_TAR(_n1) (_n1)
#define BP_I2C_TAR_ADDR 0
#define BM_I2C_TAR_ADDR 0x3ff
#define BF_I2C_TAR_ADDR(v) (((v) & 0x3ff) << 0)
#define BFM_I2C_TAR_ADDR(v) BM_I2C_TAR_ADDR
#define BF_I2C_TAR_ADDR_V(e) BF_I2C_TAR_ADDR(BV_I2C_TAR_ADDR__##e)
#define BFM_I2C_TAR_ADDR_V(v) BM_I2C_TAR_ADDR
#define BP_I2C_TAR_10BITS 12
#define BM_I2C_TAR_10BITS 0x1000
#define BF_I2C_TAR_10BITS(v) (((v) & 0x1) << 12)
#define BFM_I2C_TAR_10BITS(v) BM_I2C_TAR_10BITS
#define BF_I2C_TAR_10BITS_V(e) BF_I2C_TAR_10BITS(BV_I2C_TAR_10BITS__##e)
#define BFM_I2C_TAR_10BITS_V(v) BM_I2C_TAR_10BITS
#define BP_I2C_TAR_SPECIAL 11
#define BM_I2C_TAR_SPECIAL 0x800
#define BF_I2C_TAR_SPECIAL(v) (((v) & 0x1) << 11)
#define BFM_I2C_TAR_SPECIAL(v) BM_I2C_TAR_SPECIAL
#define BF_I2C_TAR_SPECIAL_V(e) BF_I2C_TAR_SPECIAL(BV_I2C_TAR_SPECIAL__##e)
#define BFM_I2C_TAR_SPECIAL_V(v) BM_I2C_TAR_SPECIAL
#define BP_I2C_TAR_GC_OR_START 10
#define BM_I2C_TAR_GC_OR_START 0x400
#define BF_I2C_TAR_GC_OR_START(v) (((v) & 0x1) << 10)
#define BFM_I2C_TAR_GC_OR_START(v) BM_I2C_TAR_GC_OR_START
#define BF_I2C_TAR_GC_OR_START_V(e) BF_I2C_TAR_GC_OR_START(BV_I2C_TAR_GC_OR_START__##e)
#define BFM_I2C_TAR_GC_OR_START_V(v) BM_I2C_TAR_GC_OR_START
#define REG_I2C_SAR(_n1) jz_reg(I2C_SAR(_n1))
#define JA_I2C_SAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8)
#define JT_I2C_SAR(_n1) JIO_32_RW
#define JN_I2C_SAR(_n1) I2C_SAR
#define JI_I2C_SAR(_n1) (_n1)
#define REG_I2C_SHCNT(_n1) jz_reg(I2C_SHCNT(_n1))
#define JA_I2C_SHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x14)
#define JT_I2C_SHCNT(_n1) JIO_32_RW
#define JN_I2C_SHCNT(_n1) I2C_SHCNT
#define JI_I2C_SHCNT(_n1) (_n1)
#define REG_I2C_SLCNT(_n1) jz_reg(I2C_SLCNT(_n1))
#define JA_I2C_SLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x18)
#define JT_I2C_SLCNT(_n1) JIO_32_RW
#define JN_I2C_SLCNT(_n1) I2C_SLCNT
#define JI_I2C_SLCNT(_n1) (_n1)
#define REG_I2C_FHCNT(_n1) jz_reg(I2C_FHCNT(_n1))
#define JA_I2C_FHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x1c)
#define JT_I2C_FHCNT(_n1) JIO_32_RW
#define JN_I2C_FHCNT(_n1) I2C_FHCNT
#define JI_I2C_FHCNT(_n1) (_n1)
#define REG_I2C_FLCNT(_n1) jz_reg(I2C_FLCNT(_n1))
#define JA_I2C_FLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x20)
#define JT_I2C_FLCNT(_n1) JIO_32_RW
#define JN_I2C_FLCNT(_n1) I2C_FLCNT
#define JI_I2C_FLCNT(_n1) (_n1)
#define REG_I2C_RXTL(_n1) jz_reg(I2C_RXTL(_n1))
#define JA_I2C_RXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x38)
#define JT_I2C_RXTL(_n1) JIO_32_RW
#define JN_I2C_RXTL(_n1) I2C_RXTL
#define JI_I2C_RXTL(_n1) (_n1)
#define REG_I2C_TXTL(_n1) jz_reg(I2C_TXTL(_n1))
#define JA_I2C_TXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x3c)
#define JT_I2C_TXTL(_n1) JIO_32_RW
#define JN_I2C_TXTL(_n1) I2C_TXTL
#define JI_I2C_TXTL(_n1) (_n1)
#define REG_I2C_TXFLR(_n1) jz_reg(I2C_TXFLR(_n1))
#define JA_I2C_TXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x74)
#define JT_I2C_TXFLR(_n1) JIO_32_RW
#define JN_I2C_TXFLR(_n1) I2C_TXFLR
#define JI_I2C_TXFLR(_n1) (_n1)
#define REG_I2C_RXFLR(_n1) jz_reg(I2C_RXFLR(_n1))
#define JA_I2C_RXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x78)
#define JT_I2C_RXFLR(_n1) JIO_32_RW
#define JN_I2C_RXFLR(_n1) I2C_RXFLR
#define JI_I2C_RXFLR(_n1) (_n1)
#define REG_I2C_SDAHD(_n1) jz_reg(I2C_SDAHD(_n1))
#define JA_I2C_SDAHD(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x7c)
#define JT_I2C_SDAHD(_n1) JIO_32_RW
#define JN_I2C_SDAHD(_n1) I2C_SDAHD
#define JI_I2C_SDAHD(_n1) (_n1)
#define REG_I2C_ABTSRC(_n1) jz_reg(I2C_ABTSRC(_n1))
#define JA_I2C_ABTSRC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x80)
#define JT_I2C_ABTSRC(_n1) JIO_32_RW
#define JN_I2C_ABTSRC(_n1) I2C_ABTSRC
#define JI_I2C_ABTSRC(_n1) (_n1)
#define REG_I2C_DMACR(_n1) jz_reg(I2C_DMACR(_n1))
#define JA_I2C_DMACR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x88)
#define JT_I2C_DMACR(_n1) JIO_32_RW
#define JN_I2C_DMACR(_n1) I2C_DMACR
#define JI_I2C_DMACR(_n1) (_n1)
#define REG_I2C_DMATDLR(_n1) jz_reg(I2C_DMATDLR(_n1))
#define JA_I2C_DMATDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8c)
#define JT_I2C_DMATDLR(_n1) JIO_32_RW
#define JN_I2C_DMATDLR(_n1) I2C_DMATDLR
#define JI_I2C_DMATDLR(_n1) (_n1)
#define REG_I2C_DMARDLR(_n1) jz_reg(I2C_DMARDLR(_n1))
#define JA_I2C_DMARDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x90)
#define JT_I2C_DMARDLR(_n1) JIO_32_RW
#define JN_I2C_DMARDLR(_n1) I2C_DMARDLR
#define JI_I2C_DMARDLR(_n1) (_n1)
#define REG_I2C_SDASU(_n1) jz_reg(I2C_SDASU(_n1))
#define JA_I2C_SDASU(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x94)
#define JT_I2C_SDASU(_n1) JIO_32_RW
#define JN_I2C_SDASU(_n1) I2C_SDASU
#define JI_I2C_SDASU(_n1) (_n1)
#define REG_I2C_ACKGC(_n1) jz_reg(I2C_ACKGC(_n1))
#define JA_I2C_ACKGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x98)
#define JT_I2C_ACKGC(_n1) JIO_32_RW
#define JN_I2C_ACKGC(_n1) I2C_ACKGC
#define JI_I2C_ACKGC(_n1) (_n1)
#define REG_I2C_FLT(_n1) jz_reg(I2C_FLT(_n1))
#define JA_I2C_FLT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0xa0)
#define JT_I2C_FLT(_n1) JIO_32_RW
#define JN_I2C_FLT(_n1) I2C_FLT
#define JI_I2C_FLT(_n1) (_n1)
#define REG_I2C_CINT(_n1) jz_reg(I2C_CINT(_n1))
#define JA_I2C_CINT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x40)
#define JT_I2C_CINT(_n1) JIO_32_RW
#define JN_I2C_CINT(_n1) I2C_CINT
#define JI_I2C_CINT(_n1) (_n1)
#define REG_I2C_CRXUF(_n1) jz_reg(I2C_CRXUF(_n1))
#define JA_I2C_CRXUF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x44)
#define JT_I2C_CRXUF(_n1) JIO_32_RW
#define JN_I2C_CRXUF(_n1) I2C_CRXUF
#define JI_I2C_CRXUF(_n1) (_n1)
#define REG_I2C_CRXOF(_n1) jz_reg(I2C_CRXOF(_n1))
#define JA_I2C_CRXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x48)
#define JT_I2C_CRXOF(_n1) JIO_32_RW
#define JN_I2C_CRXOF(_n1) I2C_CRXOF
#define JI_I2C_CRXOF(_n1) (_n1)
#define REG_I2C_CTXOF(_n1) jz_reg(I2C_CTXOF(_n1))
#define JA_I2C_CTXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4c)
#define JT_I2C_CTXOF(_n1) JIO_32_RW
#define JN_I2C_CTXOF(_n1) I2C_CTXOF
#define JI_I2C_CTXOF(_n1) (_n1)
#define REG_I2C_CRXREQ(_n1) jz_reg(I2C_CRXREQ(_n1))
#define JA_I2C_CRXREQ(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x50)
#define JT_I2C_CRXREQ(_n1) JIO_32_RW
#define JN_I2C_CRXREQ(_n1) I2C_CRXREQ
#define JI_I2C_CRXREQ(_n1) (_n1)
#define REG_I2C_CTXABT(_n1) jz_reg(I2C_CTXABT(_n1))
#define JA_I2C_CTXABT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x54)
#define JT_I2C_CTXABT(_n1) JIO_32_RW
#define JN_I2C_CTXABT(_n1) I2C_CTXABT
#define JI_I2C_CTXABT(_n1) (_n1)
#define REG_I2C_CRXDN(_n1) jz_reg(I2C_CRXDN(_n1))
#define JA_I2C_CRXDN(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x58)
#define JT_I2C_CRXDN(_n1) JIO_32_RW
#define JN_I2C_CRXDN(_n1) I2C_CRXDN
#define JI_I2C_CRXDN(_n1) (_n1)
#define REG_I2C_CACT(_n1) jz_reg(I2C_CACT(_n1))
#define JA_I2C_CACT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x5c)
#define JT_I2C_CACT(_n1) JIO_32_RW
#define JN_I2C_CACT(_n1) I2C_CACT
#define JI_I2C_CACT(_n1) (_n1)
#define REG_I2C_CSTP(_n1) jz_reg(I2C_CSTP(_n1))
#define JA_I2C_CSTP(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x60)
#define JT_I2C_CSTP(_n1) JIO_32_RW
#define JN_I2C_CSTP(_n1) I2C_CSTP
#define JI_I2C_CSTP(_n1) (_n1)
#define REG_I2C_CSTT(_n1) jz_reg(I2C_CSTT(_n1))
#define JA_I2C_CSTT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x64)
#define JT_I2C_CSTT(_n1) JIO_32_RW
#define JN_I2C_CSTT(_n1) I2C_CSTT
#define JI_I2C_CSTT(_n1) (_n1)
#define REG_I2C_CGC(_n1) jz_reg(I2C_CGC(_n1))
#define JA_I2C_CGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x68)
#define JT_I2C_CGC(_n1) JIO_32_RW
#define JN_I2C_CGC(_n1) I2C_CGC
#define JI_I2C_CGC(_n1) (_n1)
#endif /* __HEADERGEN_I2C_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_INTC_H__
#define __HEADERGEN_INTC_H__
#include "macro.h"
#define REG_INTC_SRC(_n1) jz_reg(INTC_SRC(_n1))
#define JA_INTC_SRC(_n1) (0xb0001000 + 0x0 + (_n1) * 0x20)
#define JT_INTC_SRC(_n1) JIO_32_RW
#define JN_INTC_SRC(_n1) INTC_SRC
#define JI_INTC_SRC(_n1) (_n1)
#define REG_INTC_MSK(_n1) jz_reg(INTC_MSK(_n1))
#define JA_INTC_MSK(_n1) (0xb0001000 + 0x4 + (_n1) * 0x20)
#define JT_INTC_MSK(_n1) JIO_32_RW
#define JN_INTC_MSK(_n1) INTC_MSK
#define JI_INTC_MSK(_n1) (_n1)
#define REG_INTC_MSK_SET(_n1) jz_reg(INTC_MSK_SET(_n1))
#define JA_INTC_MSK_SET(_n1) (JA_INTC_MSK(_n1) + 0x4)
#define JT_INTC_MSK_SET(_n1) JIO_32_WO
#define JN_INTC_MSK_SET(_n1) INTC_MSK
#define JI_INTC_MSK_SET(_n1) (_n1)
#define REG_INTC_MSK_CLR(_n1) jz_reg(INTC_MSK_CLR(_n1))
#define JA_INTC_MSK_CLR(_n1) (JA_INTC_MSK(_n1) + 0x8)
#define JT_INTC_MSK_CLR(_n1) JIO_32_WO
#define JN_INTC_MSK_CLR(_n1) INTC_MSK
#define JI_INTC_MSK_CLR(_n1) (_n1)
#define REG_INTC_PND(_n1) jz_reg(INTC_PND(_n1))
#define JA_INTC_PND(_n1) (0xb0001000 + 0x10 + (_n1) * 0x20)
#define JT_INTC_PND(_n1) JIO_32_RW
#define JN_INTC_PND(_n1) INTC_PND
#define JI_INTC_PND(_n1) (_n1)
#endif /* __HEADERGEN_INTC_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_LCD_H__
#define __HEADERGEN_LCD_H__
#include "macro.h"
#define REG_LCD_CFG jz_reg(LCD_CFG)
#define JA_LCD_CFG (0xb3050000 + 0x0)
#define JT_LCD_CFG JIO_32_RW
#define JN_LCD_CFG LCD_CFG
#define JI_LCD_CFG
#define BP_LCD_CFG_INVDAT 17
#define BM_LCD_CFG_INVDAT 0x20000
#define BF_LCD_CFG_INVDAT(v) (((v) & 0x1) << 17)
#define BFM_LCD_CFG_INVDAT(v) BM_LCD_CFG_INVDAT
#define BF_LCD_CFG_INVDAT_V(e) BF_LCD_CFG_INVDAT(BV_LCD_CFG_INVDAT__##e)
#define BFM_LCD_CFG_INVDAT_V(v) BM_LCD_CFG_INVDAT
#define REG_LCD_CTRL jz_reg(LCD_CTRL)
#define JA_LCD_CTRL (0xb3050000 + 0x30)
#define JT_LCD_CTRL JIO_32_RW
#define JN_LCD_CTRL LCD_CTRL
#define JI_LCD_CTRL
#define BP_LCD_CTRL_BURST 28
#define BM_LCD_CTRL_BURST 0x70000000
#define BV_LCD_CTRL_BURST__4WORD 0x0
#define BV_LCD_CTRL_BURST__8WORD 0x1
#define BV_LCD_CTRL_BURST__16WORD 0x2
#define BV_LCD_CTRL_BURST__32WORD 0x3
#define BV_LCD_CTRL_BURST__64WORD 0x4
#define BF_LCD_CTRL_BURST(v) (((v) & 0x7) << 28)
#define BFM_LCD_CTRL_BURST(v) BM_LCD_CTRL_BURST
#define BF_LCD_CTRL_BURST_V(e) BF_LCD_CTRL_BURST(BV_LCD_CTRL_BURST__##e)
#define BFM_LCD_CTRL_BURST_V(v) BM_LCD_CTRL_BURST
#define BP_LCD_CTRL_BPP 0
#define BM_LCD_CTRL_BPP 0x7
#define BV_LCD_CTRL_BPP__15BIT_OR_16BIT 0x4
#define BV_LCD_CTRL_BPP__18BIT_OR_24BIT 0x5
#define BV_LCD_CTRL_BPP__24BIT_COMPRESSED 0x6
#define BV_LCD_CTRL_BPP__30BIT 0x7
#define BF_LCD_CTRL_BPP(v) (((v) & 0x7) << 0)
#define BFM_LCD_CTRL_BPP(v) BM_LCD_CTRL_BPP
#define BF_LCD_CTRL_BPP_V(e) BF_LCD_CTRL_BPP(BV_LCD_CTRL_BPP__##e)
#define BFM_LCD_CTRL_BPP_V(v) BM_LCD_CTRL_BPP
#define BP_LCD_CTRL_EOFM 13
#define BM_LCD_CTRL_EOFM 0x2000
#define BF_LCD_CTRL_EOFM(v) (((v) & 0x1) << 13)
#define BFM_LCD_CTRL_EOFM(v) BM_LCD_CTRL_EOFM
#define BF_LCD_CTRL_EOFM_V(e) BF_LCD_CTRL_EOFM(BV_LCD_CTRL_EOFM__##e)
#define BFM_LCD_CTRL_EOFM_V(v) BM_LCD_CTRL_EOFM
#define BP_LCD_CTRL_SOFM 12
#define BM_LCD_CTRL_SOFM 0x1000
#define BF_LCD_CTRL_SOFM(v) (((v) & 0x1) << 12)
#define BFM_LCD_CTRL_SOFM(v) BM_LCD_CTRL_SOFM
#define BF_LCD_CTRL_SOFM_V(e) BF_LCD_CTRL_SOFM(BV_LCD_CTRL_SOFM__##e)
#define BFM_LCD_CTRL_SOFM_V(v) BM_LCD_CTRL_SOFM
#define BP_LCD_CTRL_IFUM 10
#define BM_LCD_CTRL_IFUM 0x400
#define BF_LCD_CTRL_IFUM(v) (((v) & 0x1) << 10)
#define BFM_LCD_CTRL_IFUM(v) BM_LCD_CTRL_IFUM
#define BF_LCD_CTRL_IFUM_V(e) BF_LCD_CTRL_IFUM(BV_LCD_CTRL_IFUM__##e)
#define BFM_LCD_CTRL_IFUM_V(v) BM_LCD_CTRL_IFUM
#define BP_LCD_CTRL_QDM 7
#define BM_LCD_CTRL_QDM 0x80
#define BF_LCD_CTRL_QDM(v) (((v) & 0x1) << 7)
#define BFM_LCD_CTRL_QDM(v) BM_LCD_CTRL_QDM
#define BF_LCD_CTRL_QDM_V(e) BF_LCD_CTRL_QDM(BV_LCD_CTRL_QDM__##e)
#define BFM_LCD_CTRL_QDM_V(v) BM_LCD_CTRL_QDM
#define BP_LCD_CTRL_BEDN 6
#define BM_LCD_CTRL_BEDN 0x40
#define BF_LCD_CTRL_BEDN(v) (((v) & 0x1) << 6)
#define BFM_LCD_CTRL_BEDN(v) BM_LCD_CTRL_BEDN
#define BF_LCD_CTRL_BEDN_V(e) BF_LCD_CTRL_BEDN(BV_LCD_CTRL_BEDN__##e)
#define BFM_LCD_CTRL_BEDN_V(v) BM_LCD_CTRL_BEDN
#define BP_LCD_CTRL_PEDN 5
#define BM_LCD_CTRL_PEDN 0x20
#define BF_LCD_CTRL_PEDN(v) (((v) & 0x1) << 5)
#define BFM_LCD_CTRL_PEDN(v) BM_LCD_CTRL_PEDN
#define BF_LCD_CTRL_PEDN_V(e) BF_LCD_CTRL_PEDN(BV_LCD_CTRL_PEDN__##e)
#define BFM_LCD_CTRL_PEDN_V(v) BM_LCD_CTRL_PEDN
#define BP_LCD_CTRL_ENABLE 3
#define BM_LCD_CTRL_ENABLE 0x8
#define BF_LCD_CTRL_ENABLE(v) (((v) & 0x1) << 3)
#define BFM_LCD_CTRL_ENABLE(v) BM_LCD_CTRL_ENABLE
#define BF_LCD_CTRL_ENABLE_V(e) BF_LCD_CTRL_ENABLE(BV_LCD_CTRL_ENABLE__##e)
#define BFM_LCD_CTRL_ENABLE_V(v) BM_LCD_CTRL_ENABLE
#define REG_LCD_STATE jz_reg(LCD_STATE)
#define JA_LCD_STATE (0xb3050000 + 0x34)
#define JT_LCD_STATE JIO_32_RW
#define JN_LCD_STATE LCD_STATE
#define JI_LCD_STATE
#define BP_LCD_STATE_QD 7
#define BM_LCD_STATE_QD 0x80
#define BF_LCD_STATE_QD(v) (((v) & 0x1) << 7)
#define BFM_LCD_STATE_QD(v) BM_LCD_STATE_QD
#define BF_LCD_STATE_QD_V(e) BF_LCD_STATE_QD(BV_LCD_STATE_QD__##e)
#define BFM_LCD_STATE_QD_V(v) BM_LCD_STATE_QD
#define BP_LCD_STATE_EOF 5
#define BM_LCD_STATE_EOF 0x20
#define BF_LCD_STATE_EOF(v) (((v) & 0x1) << 5)
#define BFM_LCD_STATE_EOF(v) BM_LCD_STATE_EOF
#define BF_LCD_STATE_EOF_V(e) BF_LCD_STATE_EOF(BV_LCD_STATE_EOF__##e)
#define BFM_LCD_STATE_EOF_V(v) BM_LCD_STATE_EOF
#define BP_LCD_STATE_SOF 4
#define BM_LCD_STATE_SOF 0x10
#define BF_LCD_STATE_SOF(v) (((v) & 0x1) << 4)
#define BFM_LCD_STATE_SOF(v) BM_LCD_STATE_SOF
#define BF_LCD_STATE_SOF_V(e) BF_LCD_STATE_SOF(BV_LCD_STATE_SOF__##e)
#define BFM_LCD_STATE_SOF_V(v) BM_LCD_STATE_SOF
#define BP_LCD_STATE_IFU 2
#define BM_LCD_STATE_IFU 0x4
#define BF_LCD_STATE_IFU(v) (((v) & 0x1) << 2)
#define BFM_LCD_STATE_IFU(v) BM_LCD_STATE_IFU
#define BF_LCD_STATE_IFU_V(e) BF_LCD_STATE_IFU(BV_LCD_STATE_IFU__##e)
#define BFM_LCD_STATE_IFU_V(v) BM_LCD_STATE_IFU
#define REG_LCD_OSDCTRL jz_reg(LCD_OSDCTRL)
#define JA_LCD_OSDCTRL (0xb3050000 + 0x104)
#define JT_LCD_OSDCTRL JIO_32_RW
#define JN_LCD_OSDCTRL LCD_OSDCTRL
#define JI_LCD_OSDCTRL
#define REG_LCD_BGC jz_reg(LCD_BGC)
#define JA_LCD_BGC (0xb3050000 + 0x10c)
#define JT_LCD_BGC JIO_32_RW
#define JN_LCD_BGC LCD_BGC
#define JI_LCD_BGC
#define REG_LCD_DAH jz_reg(LCD_DAH)
#define JA_LCD_DAH (0xb3050000 + 0x10)
#define JT_LCD_DAH JIO_32_RW
#define JN_LCD_DAH LCD_DAH
#define JI_LCD_DAH
#define REG_LCD_DAV jz_reg(LCD_DAV)
#define JA_LCD_DAV (0xb3050000 + 0x14)
#define JT_LCD_DAV JIO_32_RW
#define JN_LCD_DAV LCD_DAV
#define JI_LCD_DAV
#define REG_LCD_VAT jz_reg(LCD_VAT)
#define JA_LCD_VAT (0xb3050000 + 0xc)
#define JT_LCD_VAT JIO_32_RW
#define JN_LCD_VAT LCD_VAT
#define JI_LCD_VAT
#define REG_LCD_VSYNC jz_reg(LCD_VSYNC)
#define JA_LCD_VSYNC (0xb3050000 + 0x4)
#define JT_LCD_VSYNC JIO_32_RW
#define JN_LCD_VSYNC LCD_VSYNC
#define JI_LCD_VSYNC
#define REG_LCD_HSYNC jz_reg(LCD_HSYNC)
#define JA_LCD_HSYNC (0xb3050000 + 0x8)
#define JT_LCD_HSYNC JIO_32_RW
#define JN_LCD_HSYNC LCD_HSYNC
#define JI_LCD_HSYNC
#define REG_LCD_IID jz_reg(LCD_IID)
#define JA_LCD_IID (0xb3050000 + 0x38)
#define JT_LCD_IID JIO_32_RW
#define JN_LCD_IID LCD_IID
#define JI_LCD_IID
#define REG_LCD_DA jz_reg(LCD_DA)
#define JA_LCD_DA (0xb3050000 + 0x40)
#define JT_LCD_DA JIO_32_RW
#define JN_LCD_DA LCD_DA
#define JI_LCD_DA
#define REG_LCD_MCFG jz_reg(LCD_MCFG)
#define JA_LCD_MCFG (0xb3050000 + 0xa0)
#define JT_LCD_MCFG JIO_32_RW
#define JN_LCD_MCFG LCD_MCFG
#define JI_LCD_MCFG
#define BP_LCD_MCFG_CWIDTH 8
#define BM_LCD_MCFG_CWIDTH 0x300
#define BV_LCD_MCFG_CWIDTH__16BIT_OR_9BIT 0x0
#define BV_LCD_MCFG_CWIDTH__8BIT 0x1
#define BV_LCD_MCFG_CWIDTH__18BIT 0x2
#define BV_LCD_MCFG_CWIDTH__24BIT 0x3
#define BF_LCD_MCFG_CWIDTH(v) (((v) & 0x3) << 8)
#define BFM_LCD_MCFG_CWIDTH(v) BM_LCD_MCFG_CWIDTH
#define BF_LCD_MCFG_CWIDTH_V(e) BF_LCD_MCFG_CWIDTH(BV_LCD_MCFG_CWIDTH__##e)
#define BFM_LCD_MCFG_CWIDTH_V(v) BM_LCD_MCFG_CWIDTH
#define REG_LCD_MCFG_NEW jz_reg(LCD_MCFG_NEW)
#define JA_LCD_MCFG_NEW (0xb3050000 + 0xb8)
#define JT_LCD_MCFG_NEW JIO_32_RW
#define JN_LCD_MCFG_NEW LCD_MCFG_NEW
#define JI_LCD_MCFG_NEW
#define BP_LCD_MCFG_NEW_DWIDTH 13
#define BM_LCD_MCFG_NEW_DWIDTH 0xe000
#define BV_LCD_MCFG_NEW_DWIDTH__8BIT 0x0
#define BV_LCD_MCFG_NEW_DWIDTH__9BIT 0x1
#define BV_LCD_MCFG_NEW_DWIDTH__16BIT 0x2
#define BV_LCD_MCFG_NEW_DWIDTH__18BIT 0x3
#define BV_LCD_MCFG_NEW_DWIDTH__24BIT 0x4
#define BF_LCD_MCFG_NEW_DWIDTH(v) (((v) & 0x7) << 13)
#define BFM_LCD_MCFG_NEW_DWIDTH(v) BM_LCD_MCFG_NEW_DWIDTH
#define BF_LCD_MCFG_NEW_DWIDTH_V(e) BF_LCD_MCFG_NEW_DWIDTH(BV_LCD_MCFG_NEW_DWIDTH__##e)
#define BFM_LCD_MCFG_NEW_DWIDTH_V(v) BM_LCD_MCFG_NEW_DWIDTH
#define BP_LCD_MCFG_NEW_DTIMES 8
#define BM_LCD_MCFG_NEW_DTIMES 0x300
#define BV_LCD_MCFG_NEW_DTIMES__1TIME 0x0
#define BV_LCD_MCFG_NEW_DTIMES__2TIME 0x1
#define BV_LCD_MCFG_NEW_DTIMES__3TIME 0x2
#define BF_LCD_MCFG_NEW_DTIMES(v) (((v) & 0x3) << 8)
#define BFM_LCD_MCFG_NEW_DTIMES(v) BM_LCD_MCFG_NEW_DTIMES
#define BF_LCD_MCFG_NEW_DTIMES_V(e) BF_LCD_MCFG_NEW_DTIMES(BV_LCD_MCFG_NEW_DTIMES__##e)
#define BFM_LCD_MCFG_NEW_DTIMES_V(v) BM_LCD_MCFG_NEW_DTIMES
#define BP_LCD_MCFG_NEW_6800_MODE 11
#define BM_LCD_MCFG_NEW_6800_MODE 0x800
#define BF_LCD_MCFG_NEW_6800_MODE(v) (((v) & 0x1) << 11)
#define BFM_LCD_MCFG_NEW_6800_MODE(v) BM_LCD_MCFG_NEW_6800_MODE
#define BF_LCD_MCFG_NEW_6800_MODE_V(e) BF_LCD_MCFG_NEW_6800_MODE(BV_LCD_MCFG_NEW_6800_MODE__##e)
#define BFM_LCD_MCFG_NEW_6800_MODE_V(v) BM_LCD_MCFG_NEW_6800_MODE
#define BP_LCD_MCFG_NEW_CMD_9BIT 10
#define BM_LCD_MCFG_NEW_CMD_9BIT 0x400
#define BF_LCD_MCFG_NEW_CMD_9BIT(v) (((v) & 0x1) << 10)
#define BFM_LCD_MCFG_NEW_CMD_9BIT(v) BM_LCD_MCFG_NEW_CMD_9BIT
#define BF_LCD_MCFG_NEW_CMD_9BIT_V(e) BF_LCD_MCFG_NEW_CMD_9BIT(BV_LCD_MCFG_NEW_CMD_9BIT__##e)
#define BFM_LCD_MCFG_NEW_CMD_9BIT_V(v) BM_LCD_MCFG_NEW_CMD_9BIT
#define BP_LCD_MCFG_NEW_CSPLY 5
#define BM_LCD_MCFG_NEW_CSPLY 0x20
#define BF_LCD_MCFG_NEW_CSPLY(v) (((v) & 0x1) << 5)
#define BFM_LCD_MCFG_NEW_CSPLY(v) BM_LCD_MCFG_NEW_CSPLY
#define BF_LCD_MCFG_NEW_CSPLY_V(e) BF_LCD_MCFG_NEW_CSPLY(BV_LCD_MCFG_NEW_CSPLY__##e)
#define BFM_LCD_MCFG_NEW_CSPLY_V(v) BM_LCD_MCFG_NEW_CSPLY
#define BP_LCD_MCFG_NEW_RSPLY 4
#define BM_LCD_MCFG_NEW_RSPLY 0x10
#define BF_LCD_MCFG_NEW_RSPLY(v) (((v) & 0x1) << 4)
#define BFM_LCD_MCFG_NEW_RSPLY(v) BM_LCD_MCFG_NEW_RSPLY
#define BF_LCD_MCFG_NEW_RSPLY_V(e) BF_LCD_MCFG_NEW_RSPLY(BV_LCD_MCFG_NEW_RSPLY__##e)
#define BFM_LCD_MCFG_NEW_RSPLY_V(v) BM_LCD_MCFG_NEW_RSPLY
#define BP_LCD_MCFG_NEW_CLKPLY 3
#define BM_LCD_MCFG_NEW_CLKPLY 0x8
#define BF_LCD_MCFG_NEW_CLKPLY(v) (((v) & 0x1) << 3)
#define BFM_LCD_MCFG_NEW_CLKPLY(v) BM_LCD_MCFG_NEW_CLKPLY
#define BF_LCD_MCFG_NEW_CLKPLY_V(e) BF_LCD_MCFG_NEW_CLKPLY(BV_LCD_MCFG_NEW_CLKPLY__##e)
#define BFM_LCD_MCFG_NEW_CLKPLY_V(v) BM_LCD_MCFG_NEW_CLKPLY
#define BP_LCD_MCFG_NEW_DTYPE 2
#define BM_LCD_MCFG_NEW_DTYPE 0x4
#define BV_LCD_MCFG_NEW_DTYPE__SERIAL 0x1
#define BV_LCD_MCFG_NEW_DTYPE__PARALLEL 0x0
#define BF_LCD_MCFG_NEW_DTYPE(v) (((v) & 0x1) << 2)
#define BFM_LCD_MCFG_NEW_DTYPE(v) BM_LCD_MCFG_NEW_DTYPE
#define BF_LCD_MCFG_NEW_DTYPE_V(e) BF_LCD_MCFG_NEW_DTYPE(BV_LCD_MCFG_NEW_DTYPE__##e)
#define BFM_LCD_MCFG_NEW_DTYPE_V(v) BM_LCD_MCFG_NEW_DTYPE
#define BP_LCD_MCFG_NEW_CTYPE 1
#define BM_LCD_MCFG_NEW_CTYPE 0x2
#define BV_LCD_MCFG_NEW_CTYPE__SERIAL 0x1
#define BV_LCD_MCFG_NEW_CTYPE__PARALLEL 0x0
#define BF_LCD_MCFG_NEW_CTYPE(v) (((v) & 0x1) << 1)
#define BFM_LCD_MCFG_NEW_CTYPE(v) BM_LCD_MCFG_NEW_CTYPE
#define BF_LCD_MCFG_NEW_CTYPE_V(e) BF_LCD_MCFG_NEW_CTYPE(BV_LCD_MCFG_NEW_CTYPE__##e)
#define BFM_LCD_MCFG_NEW_CTYPE_V(v) BM_LCD_MCFG_NEW_CTYPE
#define BP_LCD_MCFG_NEW_FMT_CONV 0
#define BM_LCD_MCFG_NEW_FMT_CONV 0x1
#define BF_LCD_MCFG_NEW_FMT_CONV(v) (((v) & 0x1) << 0)
#define BFM_LCD_MCFG_NEW_FMT_CONV(v) BM_LCD_MCFG_NEW_FMT_CONV
#define BF_LCD_MCFG_NEW_FMT_CONV_V(e) BF_LCD_MCFG_NEW_FMT_CONV(BV_LCD_MCFG_NEW_FMT_CONV__##e)
#define BFM_LCD_MCFG_NEW_FMT_CONV_V(v) BM_LCD_MCFG_NEW_FMT_CONV
#define REG_LCD_MCTRL jz_reg(LCD_MCTRL)
#define JA_LCD_MCTRL (0xb3050000 + 0xa4)
#define JT_LCD_MCTRL JIO_32_RW
#define JN_LCD_MCTRL LCD_MCTRL
#define JI_LCD_MCTRL
#define BP_LCD_MCTRL_NARROW_TE 10
#define BM_LCD_MCTRL_NARROW_TE 0x400
#define BF_LCD_MCTRL_NARROW_TE(v) (((v) & 0x1) << 10)
#define BFM_LCD_MCTRL_NARROW_TE(v) BM_LCD_MCTRL_NARROW_TE
#define BF_LCD_MCTRL_NARROW_TE_V(e) BF_LCD_MCTRL_NARROW_TE(BV_LCD_MCTRL_NARROW_TE__##e)
#define BFM_LCD_MCTRL_NARROW_TE_V(v) BM_LCD_MCTRL_NARROW_TE
#define BP_LCD_MCTRL_TE_INV 9
#define BM_LCD_MCTRL_TE_INV 0x200
#define BF_LCD_MCTRL_TE_INV(v) (((v) & 0x1) << 9)
#define BFM_LCD_MCTRL_TE_INV(v) BM_LCD_MCTRL_TE_INV
#define BF_LCD_MCTRL_TE_INV_V(e) BF_LCD_MCTRL_TE_INV(BV_LCD_MCTRL_TE_INV__##e)
#define BFM_LCD_MCTRL_TE_INV_V(v) BM_LCD_MCTRL_TE_INV
#define BP_LCD_MCTRL_NOT_USE_TE 8
#define BM_LCD_MCTRL_NOT_USE_TE 0x100
#define BF_LCD_MCTRL_NOT_USE_TE(v) (((v) & 0x1) << 8)
#define BFM_LCD_MCTRL_NOT_USE_TE(v) BM_LCD_MCTRL_NOT_USE_TE
#define BF_LCD_MCTRL_NOT_USE_TE_V(e) BF_LCD_MCTRL_NOT_USE_TE(BV_LCD_MCTRL_NOT_USE_TE__##e)
#define BFM_LCD_MCTRL_NOT_USE_TE_V(v) BM_LCD_MCTRL_NOT_USE_TE
#define BP_LCD_MCTRL_DCSI_SEL 7
#define BM_LCD_MCTRL_DCSI_SEL 0x80
#define BF_LCD_MCTRL_DCSI_SEL(v) (((v) & 0x1) << 7)
#define BFM_LCD_MCTRL_DCSI_SEL(v) BM_LCD_MCTRL_DCSI_SEL
#define BF_LCD_MCTRL_DCSI_SEL_V(e) BF_LCD_MCTRL_DCSI_SEL(BV_LCD_MCTRL_DCSI_SEL__##e)
#define BFM_LCD_MCTRL_DCSI_SEL_V(v) BM_LCD_MCTRL_DCSI_SEL
#define BP_LCD_MCTRL_MIPI_SLCD 6
#define BM_LCD_MCTRL_MIPI_SLCD 0x40
#define BF_LCD_MCTRL_MIPI_SLCD(v) (((v) & 0x1) << 6)
#define BFM_LCD_MCTRL_MIPI_SLCD(v) BM_LCD_MCTRL_MIPI_SLCD
#define BF_LCD_MCTRL_MIPI_SLCD_V(e) BF_LCD_MCTRL_MIPI_SLCD(BV_LCD_MCTRL_MIPI_SLCD__##e)
#define BFM_LCD_MCTRL_MIPI_SLCD_V(v) BM_LCD_MCTRL_MIPI_SLCD
#define BP_LCD_MCTRL_FAST_MODE 4
#define BM_LCD_MCTRL_FAST_MODE 0x10
#define BF_LCD_MCTRL_FAST_MODE(v) (((v) & 0x1) << 4)
#define BFM_LCD_MCTRL_FAST_MODE(v) BM_LCD_MCTRL_FAST_MODE
#define BF_LCD_MCTRL_FAST_MODE_V(e) BF_LCD_MCTRL_FAST_MODE(BV_LCD_MCTRL_FAST_MODE__##e)
#define BFM_LCD_MCTRL_FAST_MODE_V(v) BM_LCD_MCTRL_FAST_MODE
#define BP_LCD_MCTRL_GATE_MASK 3
#define BM_LCD_MCTRL_GATE_MASK 0x8
#define BF_LCD_MCTRL_GATE_MASK(v) (((v) & 0x1) << 3)
#define BFM_LCD_MCTRL_GATE_MASK(v) BM_LCD_MCTRL_GATE_MASK
#define BF_LCD_MCTRL_GATE_MASK_V(e) BF_LCD_MCTRL_GATE_MASK(BV_LCD_MCTRL_GATE_MASK__##e)
#define BFM_LCD_MCTRL_GATE_MASK_V(v) BM_LCD_MCTRL_GATE_MASK
#define BP_LCD_MCTRL_DMA_MODE 2
#define BM_LCD_MCTRL_DMA_MODE 0x4
#define BF_LCD_MCTRL_DMA_MODE(v) (((v) & 0x1) << 2)
#define BFM_LCD_MCTRL_DMA_MODE(v) BM_LCD_MCTRL_DMA_MODE
#define BF_LCD_MCTRL_DMA_MODE_V(e) BF_LCD_MCTRL_DMA_MODE(BV_LCD_MCTRL_DMA_MODE__##e)
#define BFM_LCD_MCTRL_DMA_MODE_V(v) BM_LCD_MCTRL_DMA_MODE
#define BP_LCD_MCTRL_DMA_START 1
#define BM_LCD_MCTRL_DMA_START 0x2
#define BF_LCD_MCTRL_DMA_START(v) (((v) & 0x1) << 1)
#define BFM_LCD_MCTRL_DMA_START(v) BM_LCD_MCTRL_DMA_START
#define BF_LCD_MCTRL_DMA_START_V(e) BF_LCD_MCTRL_DMA_START(BV_LCD_MCTRL_DMA_START__##e)
#define BFM_LCD_MCTRL_DMA_START_V(v) BM_LCD_MCTRL_DMA_START
#define BP_LCD_MCTRL_DMA_TX_EN 0
#define BM_LCD_MCTRL_DMA_TX_EN 0x1
#define BF_LCD_MCTRL_DMA_TX_EN(v) (((v) & 0x1) << 0)
#define BFM_LCD_MCTRL_DMA_TX_EN(v) BM_LCD_MCTRL_DMA_TX_EN
#define BF_LCD_MCTRL_DMA_TX_EN_V(e) BF_LCD_MCTRL_DMA_TX_EN(BV_LCD_MCTRL_DMA_TX_EN__##e)
#define BFM_LCD_MCTRL_DMA_TX_EN_V(v) BM_LCD_MCTRL_DMA_TX_EN
#define REG_LCD_MSTATE jz_reg(LCD_MSTATE)
#define JA_LCD_MSTATE (0xb3050000 + 0xa8)
#define JT_LCD_MSTATE JIO_32_RW
#define JN_LCD_MSTATE LCD_MSTATE
#define JI_LCD_MSTATE
#define BP_LCD_MSTATE_LCD_ID 16
#define BM_LCD_MSTATE_LCD_ID 0xffff0000
#define BF_LCD_MSTATE_LCD_ID(v) (((v) & 0xffff) << 16)
#define BFM_LCD_MSTATE_LCD_ID(v) BM_LCD_MSTATE_LCD_ID
#define BF_LCD_MSTATE_LCD_ID_V(e) BF_LCD_MSTATE_LCD_ID(BV_LCD_MSTATE_LCD_ID__##e)
#define BFM_LCD_MSTATE_LCD_ID_V(v) BM_LCD_MSTATE_LCD_ID
#define BP_LCD_MSTATE_BUSY 0
#define BM_LCD_MSTATE_BUSY 0x1
#define BF_LCD_MSTATE_BUSY(v) (((v) & 0x1) << 0)
#define BFM_LCD_MSTATE_BUSY(v) BM_LCD_MSTATE_BUSY
#define BF_LCD_MSTATE_BUSY_V(e) BF_LCD_MSTATE_BUSY(BV_LCD_MSTATE_BUSY__##e)
#define BFM_LCD_MSTATE_BUSY_V(v) BM_LCD_MSTATE_BUSY
#define REG_LCD_MDATA jz_reg(LCD_MDATA)
#define JA_LCD_MDATA (0xb3050000 + 0xac)
#define JT_LCD_MDATA JIO_32_RW
#define JN_LCD_MDATA LCD_MDATA
#define JI_LCD_MDATA
#define BP_LCD_MDATA_TYPE 30
#define BM_LCD_MDATA_TYPE 0xc0000000
#define BV_LCD_MDATA_TYPE__CMD 0x1
#define BV_LCD_MDATA_TYPE__DAT 0x0
#define BF_LCD_MDATA_TYPE(v) (((v) & 0x3) << 30)
#define BFM_LCD_MDATA_TYPE(v) BM_LCD_MDATA_TYPE
#define BF_LCD_MDATA_TYPE_V(e) BF_LCD_MDATA_TYPE(BV_LCD_MDATA_TYPE__##e)
#define BFM_LCD_MDATA_TYPE_V(v) BM_LCD_MDATA_TYPE
#define BP_LCD_MDATA_DATA 0
#define BM_LCD_MDATA_DATA 0xffffff
#define BF_LCD_MDATA_DATA(v) (((v) & 0xffffff) << 0)
#define BFM_LCD_MDATA_DATA(v) BM_LCD_MDATA_DATA
#define BF_LCD_MDATA_DATA_V(e) BF_LCD_MDATA_DATA(BV_LCD_MDATA_DATA__##e)
#define BFM_LCD_MDATA_DATA_V(v) BM_LCD_MDATA_DATA
#define REG_LCD_WTIME jz_reg(LCD_WTIME)
#define JA_LCD_WTIME (0xb3050000 + 0xb0)
#define JT_LCD_WTIME JIO_32_RW
#define JN_LCD_WTIME LCD_WTIME
#define JI_LCD_WTIME
#define BP_LCD_WTIME_DHTIME 24
#define BM_LCD_WTIME_DHTIME 0xff000000
#define BF_LCD_WTIME_DHTIME(v) (((v) & 0xff) << 24)
#define BFM_LCD_WTIME_DHTIME(v) BM_LCD_WTIME_DHTIME
#define BF_LCD_WTIME_DHTIME_V(e) BF_LCD_WTIME_DHTIME(BV_LCD_WTIME_DHTIME__##e)
#define BFM_LCD_WTIME_DHTIME_V(v) BM_LCD_WTIME_DHTIME
#define BP_LCD_WTIME_DLTIME 16
#define BM_LCD_WTIME_DLTIME 0xff0000
#define BF_LCD_WTIME_DLTIME(v) (((v) & 0xff) << 16)
#define BFM_LCD_WTIME_DLTIME(v) BM_LCD_WTIME_DLTIME
#define BF_LCD_WTIME_DLTIME_V(e) BF_LCD_WTIME_DLTIME(BV_LCD_WTIME_DLTIME__##e)
#define BFM_LCD_WTIME_DLTIME_V(v) BM_LCD_WTIME_DLTIME
#define BP_LCD_WTIME_CHTIME 8
#define BM_LCD_WTIME_CHTIME 0xff00
#define BF_LCD_WTIME_CHTIME(v) (((v) & 0xff) << 8)
#define BFM_LCD_WTIME_CHTIME(v) BM_LCD_WTIME_CHTIME
#define BF_LCD_WTIME_CHTIME_V(e) BF_LCD_WTIME_CHTIME(BV_LCD_WTIME_CHTIME__##e)
#define BFM_LCD_WTIME_CHTIME_V(v) BM_LCD_WTIME_CHTIME
#define BP_LCD_WTIME_CLTIME 0
#define BM_LCD_WTIME_CLTIME 0xff
#define BF_LCD_WTIME_CLTIME(v) (((v) & 0xff) << 0)
#define BFM_LCD_WTIME_CLTIME(v) BM_LCD_WTIME_CLTIME
#define BF_LCD_WTIME_CLTIME_V(e) BF_LCD_WTIME_CLTIME(BV_LCD_WTIME_CLTIME__##e)
#define BFM_LCD_WTIME_CLTIME_V(v) BM_LCD_WTIME_CLTIME
#define REG_LCD_TASH jz_reg(LCD_TASH)
#define JA_LCD_TASH (0xb3050000 + 0xb4)
#define JT_LCD_TASH JIO_32_RW
#define JN_LCD_TASH LCD_TASH
#define JI_LCD_TASH
#define BP_LCD_TASH_TAH 8
#define BM_LCD_TASH_TAH 0xff00
#define BF_LCD_TASH_TAH(v) (((v) & 0xff) << 8)
#define BFM_LCD_TASH_TAH(v) BM_LCD_TASH_TAH
#define BF_LCD_TASH_TAH_V(e) BF_LCD_TASH_TAH(BV_LCD_TASH_TAH__##e)
#define BFM_LCD_TASH_TAH_V(v) BM_LCD_TASH_TAH
#define BP_LCD_TASH_TAS 0
#define BM_LCD_TASH_TAS 0xff
#define BF_LCD_TASH_TAS(v) (((v) & 0xff) << 0)
#define BFM_LCD_TASH_TAS(v) BM_LCD_TASH_TAS
#define BF_LCD_TASH_TAS_V(e) BF_LCD_TASH_TAS(BV_LCD_TASH_TAS__##e)
#define BFM_LCD_TASH_TAS_V(v) BM_LCD_TASH_TAS
#define REG_LCD_SMWT jz_reg(LCD_SMWT)
#define JA_LCD_SMWT (0xb3050000 + 0xbc)
#define JT_LCD_SMWT JIO_32_RW
#define JN_LCD_SMWT LCD_SMWT
#define JI_LCD_SMWT
#endif /* __HEADERGEN_LCD_H__*/

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firmware/target/mips/ingenic_x1000/x1000/macro.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_MACRO_H__
#define __HEADERGEN_MACRO_H__
#include <stdint.h>
#define __VAR_OR1(prefix, suffix) \
(prefix##suffix)
#define __VAR_OR2(pre, s1, s2) \
(__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2))
#define __VAR_OR3(pre, s1, s2, s3) \
(__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3))
#define __VAR_OR4(pre, s1, s2, s3, s4) \
(__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4))
#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \
(__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5))
#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6))
#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7))
#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8))
#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9))
#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10))
#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11))
#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12))
#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13))
#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, N, ...) N
#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__)
#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__)
#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__)
#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__)
#define JIO_8_RO(op, name, ...) JIO_8_RO_##op(name, __VA_ARGS__)
#define JIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(JA_##name))
#define JIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define JIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define JIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(JA_##name))
#define JIO_16_RO(op, name, ...) JIO_16_RO_##op(name, __VA_ARGS__)
#define JIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(JA_##name))
#define JIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define JIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define JIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(JA_##name))
#define JIO_32_RO(op, name, ...) JIO_32_RO_##op(name, __VA_ARGS__)
#define JIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(JA_##name))
#define JIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define JIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define JIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(JA_##name))
#define JIO_8_RW(op, name, ...) JIO_8_RW_##op(name, __VA_ARGS__)
#define JIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(JA_##name))
#define JIO_8_RW_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val)
#define JIO_8_RW_RMW(name, vand, vor) JIO_8_RW_WR(name, (JIO_8_RW_RD(name) & (vand)) | (vor))
#define JIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(JA_##name))
#define JIO_16_RW(op, name, ...) JIO_16_RW_##op(name, __VA_ARGS__)
#define JIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(JA_##name))
#define JIO_16_RW_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val)
#define JIO_16_RW_RMW(name, vand, vor) JIO_16_RW_WR(name, (JIO_16_RW_RD(name) & (vand)) | (vor))
#define JIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(JA_##name))
#define JIO_32_RW(op, name, ...) JIO_32_RW_##op(name, __VA_ARGS__)
#define JIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(JA_##name))
#define JIO_32_RW_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val)
#define JIO_32_RW_RMW(name, vand, vor) JIO_32_RW_WR(name, (JIO_32_RW_RD(name) & (vand)) | (vor))
#define JIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(JA_##name))
#define JIO_8_WO(op, name, ...) JIO_8_WO_##op(name, __VA_ARGS__)
#define JIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define JIO_8_WO_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val)
#define JIO_8_WO_RMW(name, vand, vor) JIO_8_WO_WR(name, vor)
#define JIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(JA_##name))
#define JIO_16_WO(op, name, ...) JIO_16_WO_##op(name, __VA_ARGS__)
#define JIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define JIO_16_WO_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val)
#define JIO_16_WO_RMW(name, vand, vor) JIO_16_WO_WR(name, vor)
#define JIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(JA_##name))
#define JIO_32_WO(op, name, ...) JIO_32_WO_##op(name, __VA_ARGS__)
#define JIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define JIO_32_WO_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val)
#define JIO_32_WO_RMW(name, vand, vor) JIO_32_WO_WR(name, vor)
#define JIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(JA_##name))
/** __jz_variant
*
* usage: __jz_variant(register, variant_prefix, variant_postfix)
*
* effect: expands to register variant given as argument
* note: internal usage
* note: register must be fully qualified if indexed
*
* example: __jz_variant(ICOLL_CTRL, , _SET)
* example: __jz_variant(ICOLL_ENABLE(3), , _CLR)
*/
#define __jz_variant(name, varp, vars) __jz_variant_(JN_##name, JI_##name, varp, vars)
#define __jz_variant_(...) __jz_variant__(__VA_ARGS__)
#define __jz_variant__(name, index, varp, vars) varp##name##vars index
/** jz_orf
*
* usage: jz_orf(register, f1(v1), f2(v2), ...)
*
* effect: expands to the register value where each field fi has value vi.
* Informally: reg_f1(v1) | reg_f2(v2) | ...
* note: enumerated values for fields can be obtained by using the syntax:
* f1_V(name)
*
* example: jz_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
*/
#define jz_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__)
/** __jz_orfm
*
* usage: __jz_orfm(register, f1(v1), f2(v2), ...)
*
* effect: expands to the register value where each field fi has maximum value (vi is ignored).
* note: internal usage
*
* example: __jz_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
*/
#define __jz_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__)
/** jz_orm
*
* usage: jz_orm(register, f1, f2, ...)
*
* effect: expands to the register value where each field fi is set to its maximum value.
* Informally: reg_f1_mask | reg_f2_mask | ...
*
* example: jz_orm(ICOLL_CTRL, SFTRST, CLKGATE)
*/
#define jz_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__)
/** jz_read
*
* usage: jz_read(register)
*
* effect: read a register and return its value
* note: register must be fully qualified if indexed
*
* example: jz_read(ICOLL_STATUS)
* jz_read(ICOLL_ENABLE(42))
*/
#define jz_read(name) JT_##name(RD, name)
/** jz_vreadf
*
* usage: jz_vreadf(value, register, field)
*
* effect: given a register value, return the value of a particular field
* note: this macro does NOT read any register
*
* example: jz_vreadf(0xc0000000, ICOLL_CTRL, SFTRST)
* jz_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO)
*/
#define jz_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field)
/** jz_readf
*
* usage: jz_readf(register, field)
*
* effect: read a register and return the value of a particular field
* note: register must be fully qualified if indexed
*
* example: jz_readf(ICOLL_CTRL, SFTRST)
* jz_readf(ICOLL_ENABLE(3), CPU0_PRIO)
*/
#define jz_readf(name, field) jz_readf_(jz_read(name), JN_##name, field)
#define jz_readf_(...) jz_vreadf(__VA_ARGS__)
/** jz_write
*
* usage: jz_write(register, value)
*
* effect: write a register
* note: register must be fully qualified if indexed
*
* example: jz_write(ICOLL_CTRL, 0x42)
* jz_write(ICOLL_ENABLE_SET(3), 0x37)
*/
#define jz_write(name, val) JT_##name(WR, name, val)
/** jz_writef
*
* usage: jz_writef(register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi
* note: register must be fully qualified if indexed
* note: this macro may perform a read-modify-write
*
* example: jz_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* jz_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define jz_writef(name, ...) jz_writef_(name, JN_##name, __VA_ARGS__)
#define jz_writef_(name, name2, ...) JT_##name(RMW, name, ~__jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__))
/** jz_overwritef
*
* usage: jz_overwritef(register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi and other fields have value zero
* thus this macro is equivalent to:
* jz_write(register, jz_orf(register, f1(v1), ...))
* note: register must be fully qualified if indexed
* note: this macro will overwrite the register (it is NOT a read-modify-write)
*
* example: jz_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* jz_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define jz_overwritef(name, ...) jz_overwritef_(name, JN_##name, __VA_ARGS__)
#define jz_overwritef_(name, name2, ...) JT_##name(WR, name, jz_orf(name2, __VA_ARGS__))
/** jz_vwritef
*
* usage: jz_vwritef(var, register, f1(v1), f2(v2), ...)
*
* effect: change the variable value so that field fi has value vi
* note: this macro will perform a read-modify-write
*
* example: jz_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* jz_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define jz_vwritef(var, name, ...) (var) = jz_orf(name, __VA_ARGS__) | (~__jz_orfm(name, __VA_ARGS__) & (var))
/** jz_setf
*
* usage: jz_setf(register, f1, f2, ...)
*
* effect: change the register value so that field fi has maximum value
* IMPORTANT: this macro performs a write to the set variant of the register
* note: register must be fully qualified if indexed
*
* example: jz_setf(ICOLL_CTRL, SFTRST, CLKGATE)
* jz_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define jz_setf(name, ...) jz_setf_(__jz_variant(name, , _SET), JN_##name, __VA_ARGS__)
#define jz_setf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__))
/** jz_clrf
*
* usage: jz_clrf(register, f1, f2, ...)
*
* effect: change the register value so that field fi has value zero
* IMPORTANT: this macro performs a write to the clr variant of the register
* note: register must be fully qualified if indexed
*
* example: jz_clrf(ICOLL_CTRL, SFTRST, CLKGATE)
* jz_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define jz_clrf(name, ...) jz_clrf_(__jz_variant(name, , _CLR), JN_##name, __VA_ARGS__)
#define jz_clrf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__))
/** jz_set
*
* usage: jz_set(register, set_value)
*
* effect: set some bits using set variant
* note: register must be fully qualified if indexed
*
* example: jz_set(ICOLL_CTRL, 0x42)
* jz_set(ICOLL_ENABLE(3), 0x37)
*/
#define jz_set(name, sval) jz_set_(__jz_variant(name, , _SET), sval)
#define jz_set_(sname, sval) jz_write(sname, sval)
/** jz_clr
*
* usage: jz_clr(register, clr_value)
*
* effect: clear some bits using clr variant
* note: register must be fully qualified if indexed
*
* example: jz_clr(ICOLL_CTRL, 0x42)
* jz_clr(ICOLL_ENABLE(3), 0x37)
*/
#define jz_clr(name, cval) jz_clr_(__jz_variant(name, , _CLR), cval)
#define jz_clr_(cname, cval) jz_write(cname, cval)
/** jz_cs
*
* usage: jz_cs(register, clear_value, set_value)
*
* effect: clear some bits using clr variant and then set some using set variant
* note: register must be fully qualified if indexed
*
* example: jz_cs(ICOLL_CTRL, 0xff, 0x42)
* jz_cs(ICOLL_ENABLE(3), 0xff, 0x37)
*/
#define jz_cs(name, cval, sval) jz_cs_(__jz_variant(name, , _CLR), __jz_variant(name, , _SET), cval, sval)
#define jz_cs_(cname, sname, cval, sval) do { jz_write(cname, cval); jz_write(sname, sval); } while(0)
/** jz_csf
*
* usage: jz_csf(register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi using clr and set variants
* note: register must be fully qualified if indexed
* note: this macro will NOT perform a read-modify-write and is thus safer
* IMPORTANT: this macro will set some fields to 0 temporarily, make sure this is acceptable
*
* example: jz_csf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* jz_csf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define jz_csf(name, ...) jz_csf_(name, JN_##name, __VA_ARGS__)
#define jz_csf_(name, name2, ...) jz_cs(name, __jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__))
/** jz_reg
*
* usage: jz_reg(register)
*
* effect: return a variable-like expression that can be read/written
* note: register must be fully qualified if indexed
* note: read-only registers will yield a constant expression
*
* example: unsigned x = jz_reg(ICOLL_STATUS)
* unsigned x = jz_reg(ICOLL_ENABLE(42))
* jz_reg(ICOLL_ENABLE(42)) = 64
*/
#define jz_reg(name) JT_##name(VAR, name)
#endif /* __HEADERGEN_MACRO_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_MSC_H__
#define __HEADERGEN_MSC_H__
#include "macro.h"
#define REG_MSC_CTRL(_n1) jz_reg(MSC_CTRL(_n1))
#define JA_MSC_CTRL(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x0)
#define JT_MSC_CTRL(_n1) JIO_32_RW
#define JN_MSC_CTRL(_n1) MSC_CTRL
#define JI_MSC_CTRL(_n1) (_n1)
#define BP_MSC_CTRL_CLOCK 0
#define BM_MSC_CTRL_CLOCK 0x3
#define BV_MSC_CTRL_CLOCK__DO_NOTHING 0x0
#define BV_MSC_CTRL_CLOCK__STOP 0x1
#define BV_MSC_CTRL_CLOCK__START 0x2
#define BF_MSC_CTRL_CLOCK(v) (((v) & 0x3) << 0)
#define BFM_MSC_CTRL_CLOCK(v) BM_MSC_CTRL_CLOCK
#define BF_MSC_CTRL_CLOCK_V(e) BF_MSC_CTRL_CLOCK(BV_MSC_CTRL_CLOCK__##e)
#define BFM_MSC_CTRL_CLOCK_V(v) BM_MSC_CTRL_CLOCK
#define BP_MSC_CTRL_SEND_CCSD 15
#define BM_MSC_CTRL_SEND_CCSD 0x8000
#define BF_MSC_CTRL_SEND_CCSD(v) (((v) & 0x1) << 15)
#define BFM_MSC_CTRL_SEND_CCSD(v) BM_MSC_CTRL_SEND_CCSD
#define BF_MSC_CTRL_SEND_CCSD_V(e) BF_MSC_CTRL_SEND_CCSD(BV_MSC_CTRL_SEND_CCSD__##e)
#define BFM_MSC_CTRL_SEND_CCSD_V(v) BM_MSC_CTRL_SEND_CCSD
#define BP_MSC_CTRL_SEND_AS_CCSD 14
#define BM_MSC_CTRL_SEND_AS_CCSD 0x4000
#define BF_MSC_CTRL_SEND_AS_CCSD(v) (((v) & 0x1) << 14)
#define BFM_MSC_CTRL_SEND_AS_CCSD(v) BM_MSC_CTRL_SEND_AS_CCSD
#define BF_MSC_CTRL_SEND_AS_CCSD_V(e) BF_MSC_CTRL_SEND_AS_CCSD(BV_MSC_CTRL_SEND_AS_CCSD__##e)
#define BFM_MSC_CTRL_SEND_AS_CCSD_V(v) BM_MSC_CTRL_SEND_AS_CCSD
#define BP_MSC_CTRL_EXIT_MULTIPLE 7
#define BM_MSC_CTRL_EXIT_MULTIPLE 0x80
#define BF_MSC_CTRL_EXIT_MULTIPLE(v) (((v) & 0x1) << 7)
#define BFM_MSC_CTRL_EXIT_MULTIPLE(v) BM_MSC_CTRL_EXIT_MULTIPLE
#define BF_MSC_CTRL_EXIT_MULTIPLE_V(e) BF_MSC_CTRL_EXIT_MULTIPLE(BV_MSC_CTRL_EXIT_MULTIPLE__##e)
#define BFM_MSC_CTRL_EXIT_MULTIPLE_V(v) BM_MSC_CTRL_EXIT_MULTIPLE
#define BP_MSC_CTRL_EXIT_TRANSFER 6
#define BM_MSC_CTRL_EXIT_TRANSFER 0x40
#define BF_MSC_CTRL_EXIT_TRANSFER(v) (((v) & 0x1) << 6)
#define BFM_MSC_CTRL_EXIT_TRANSFER(v) BM_MSC_CTRL_EXIT_TRANSFER
#define BF_MSC_CTRL_EXIT_TRANSFER_V(e) BF_MSC_CTRL_EXIT_TRANSFER(BV_MSC_CTRL_EXIT_TRANSFER__##e)
#define BFM_MSC_CTRL_EXIT_TRANSFER_V(v) BM_MSC_CTRL_EXIT_TRANSFER
#define BP_MSC_CTRL_START_READ_WAIT 5
#define BM_MSC_CTRL_START_READ_WAIT 0x20
#define BF_MSC_CTRL_START_READ_WAIT(v) (((v) & 0x1) << 5)
#define BFM_MSC_CTRL_START_READ_WAIT(v) BM_MSC_CTRL_START_READ_WAIT
#define BF_MSC_CTRL_START_READ_WAIT_V(e) BF_MSC_CTRL_START_READ_WAIT(BV_MSC_CTRL_START_READ_WAIT__##e)
#define BFM_MSC_CTRL_START_READ_WAIT_V(v) BM_MSC_CTRL_START_READ_WAIT
#define BP_MSC_CTRL_STOP_READ_WAIT 4
#define BM_MSC_CTRL_STOP_READ_WAIT 0x10
#define BF_MSC_CTRL_STOP_READ_WAIT(v) (((v) & 0x1) << 4)
#define BFM_MSC_CTRL_STOP_READ_WAIT(v) BM_MSC_CTRL_STOP_READ_WAIT
#define BF_MSC_CTRL_STOP_READ_WAIT_V(e) BF_MSC_CTRL_STOP_READ_WAIT(BV_MSC_CTRL_STOP_READ_WAIT__##e)
#define BFM_MSC_CTRL_STOP_READ_WAIT_V(v) BM_MSC_CTRL_STOP_READ_WAIT
#define BP_MSC_CTRL_RESET 3
#define BM_MSC_CTRL_RESET 0x8
#define BF_MSC_CTRL_RESET(v) (((v) & 0x1) << 3)
#define BFM_MSC_CTRL_RESET(v) BM_MSC_CTRL_RESET
#define BF_MSC_CTRL_RESET_V(e) BF_MSC_CTRL_RESET(BV_MSC_CTRL_RESET__##e)
#define BFM_MSC_CTRL_RESET_V(v) BM_MSC_CTRL_RESET
#define BP_MSC_CTRL_START_OP 2
#define BM_MSC_CTRL_START_OP 0x4
#define BF_MSC_CTRL_START_OP(v) (((v) & 0x1) << 2)
#define BFM_MSC_CTRL_START_OP(v) BM_MSC_CTRL_START_OP
#define BF_MSC_CTRL_START_OP_V(e) BF_MSC_CTRL_START_OP(BV_MSC_CTRL_START_OP__##e)
#define BFM_MSC_CTRL_START_OP_V(v) BM_MSC_CTRL_START_OP
#define REG_MSC_STAT(_n1) jz_reg(MSC_STAT(_n1))
#define JA_MSC_STAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4)
#define JT_MSC_STAT(_n1) JIO_32_RW
#define JN_MSC_STAT(_n1) MSC_STAT
#define JI_MSC_STAT(_n1) (_n1)
#define BP_MSC_STAT_PINS 24
#define BM_MSC_STAT_PINS 0x1f000000
#define BF_MSC_STAT_PINS(v) (((v) & 0x1f) << 24)
#define BFM_MSC_STAT_PINS(v) BM_MSC_STAT_PINS
#define BF_MSC_STAT_PINS_V(e) BF_MSC_STAT_PINS(BV_MSC_STAT_PINS__##e)
#define BFM_MSC_STAT_PINS_V(v) BM_MSC_STAT_PINS
#define BP_MSC_STAT_CRC_WRITE_ERROR 2
#define BM_MSC_STAT_CRC_WRITE_ERROR 0xc
#define BV_MSC_STAT_CRC_WRITE_ERROR__NONE 0x0
#define BV_MSC_STAT_CRC_WRITE_ERROR__BADDATA 0x1
#define BV_MSC_STAT_CRC_WRITE_ERROR__NOCRC 0x2
#define BF_MSC_STAT_CRC_WRITE_ERROR(v) (((v) & 0x3) << 2)
#define BFM_MSC_STAT_CRC_WRITE_ERROR(v) BM_MSC_STAT_CRC_WRITE_ERROR
#define BF_MSC_STAT_CRC_WRITE_ERROR_V(e) BF_MSC_STAT_CRC_WRITE_ERROR(BV_MSC_STAT_CRC_WRITE_ERROR__##e)
#define BFM_MSC_STAT_CRC_WRITE_ERROR_V(v) BM_MSC_STAT_CRC_WRITE_ERROR
#define BP_MSC_STAT_AUTO_CMD12_DONE 31
#define BM_MSC_STAT_AUTO_CMD12_DONE 0x80000000
#define BF_MSC_STAT_AUTO_CMD12_DONE(v) (((v) & 0x1) << 31)
#define BFM_MSC_STAT_AUTO_CMD12_DONE(v) BM_MSC_STAT_AUTO_CMD12_DONE
#define BF_MSC_STAT_AUTO_CMD12_DONE_V(e) BF_MSC_STAT_AUTO_CMD12_DONE(BV_MSC_STAT_AUTO_CMD12_DONE__##e)
#define BFM_MSC_STAT_AUTO_CMD12_DONE_V(v) BM_MSC_STAT_AUTO_CMD12_DONE
#define BP_MSC_STAT_BCE 20
#define BM_MSC_STAT_BCE 0x100000
#define BF_MSC_STAT_BCE(v) (((v) & 0x1) << 20)
#define BFM_MSC_STAT_BCE(v) BM_MSC_STAT_BCE
#define BF_MSC_STAT_BCE_V(e) BF_MSC_STAT_BCE(BV_MSC_STAT_BCE__##e)
#define BFM_MSC_STAT_BCE_V(v) BM_MSC_STAT_BCE
#define BP_MSC_STAT_BDE 19
#define BM_MSC_STAT_BDE 0x80000
#define BF_MSC_STAT_BDE(v) (((v) & 0x1) << 19)
#define BFM_MSC_STAT_BDE(v) BM_MSC_STAT_BDE
#define BF_MSC_STAT_BDE_V(e) BF_MSC_STAT_BDE(BV_MSC_STAT_BDE__##e)
#define BFM_MSC_STAT_BDE_V(v) BM_MSC_STAT_BDE
#define BP_MSC_STAT_BAE 18
#define BM_MSC_STAT_BAE 0x40000
#define BF_MSC_STAT_BAE(v) (((v) & 0x1) << 18)
#define BFM_MSC_STAT_BAE(v) BM_MSC_STAT_BAE
#define BF_MSC_STAT_BAE_V(e) BF_MSC_STAT_BAE(BV_MSC_STAT_BAE__##e)
#define BFM_MSC_STAT_BAE_V(v) BM_MSC_STAT_BAE
#define BP_MSC_STAT_BAR 17
#define BM_MSC_STAT_BAR 0x20000
#define BF_MSC_STAT_BAR(v) (((v) & 0x1) << 17)
#define BFM_MSC_STAT_BAR(v) BM_MSC_STAT_BAR
#define BF_MSC_STAT_BAR_V(e) BF_MSC_STAT_BAR(BV_MSC_STAT_BAR__##e)
#define BFM_MSC_STAT_BAR_V(v) BM_MSC_STAT_BAR
#define BP_MSC_STAT_DMAEND 16
#define BM_MSC_STAT_DMAEND 0x10000
#define BF_MSC_STAT_DMAEND(v) (((v) & 0x1) << 16)
#define BFM_MSC_STAT_DMAEND(v) BM_MSC_STAT_DMAEND
#define BF_MSC_STAT_DMAEND_V(e) BF_MSC_STAT_DMAEND(BV_MSC_STAT_DMAEND__##e)
#define BFM_MSC_STAT_DMAEND_V(v) BM_MSC_STAT_DMAEND
#define BP_MSC_STAT_IS_RESETTING 15
#define BM_MSC_STAT_IS_RESETTING 0x8000
#define BF_MSC_STAT_IS_RESETTING(v) (((v) & 0x1) << 15)
#define BFM_MSC_STAT_IS_RESETTING(v) BM_MSC_STAT_IS_RESETTING
#define BF_MSC_STAT_IS_RESETTING_V(e) BF_MSC_STAT_IS_RESETTING(BV_MSC_STAT_IS_RESETTING__##e)
#define BFM_MSC_STAT_IS_RESETTING_V(v) BM_MSC_STAT_IS_RESETTING
#define BP_MSC_STAT_SDIO_INT_ACTIVE 14
#define BM_MSC_STAT_SDIO_INT_ACTIVE 0x4000
#define BF_MSC_STAT_SDIO_INT_ACTIVE(v) (((v) & 0x1) << 14)
#define BFM_MSC_STAT_SDIO_INT_ACTIVE(v) BM_MSC_STAT_SDIO_INT_ACTIVE
#define BF_MSC_STAT_SDIO_INT_ACTIVE_V(e) BF_MSC_STAT_SDIO_INT_ACTIVE(BV_MSC_STAT_SDIO_INT_ACTIVE__##e)
#define BFM_MSC_STAT_SDIO_INT_ACTIVE_V(v) BM_MSC_STAT_SDIO_INT_ACTIVE
#define BP_MSC_STAT_PROG_DONE 13
#define BM_MSC_STAT_PROG_DONE 0x2000
#define BF_MSC_STAT_PROG_DONE(v) (((v) & 0x1) << 13)
#define BFM_MSC_STAT_PROG_DONE(v) BM_MSC_STAT_PROG_DONE
#define BF_MSC_STAT_PROG_DONE_V(e) BF_MSC_STAT_PROG_DONE(BV_MSC_STAT_PROG_DONE__##e)
#define BFM_MSC_STAT_PROG_DONE_V(v) BM_MSC_STAT_PROG_DONE
#define BP_MSC_STAT_DATA_TRAN_DONE 12
#define BM_MSC_STAT_DATA_TRAN_DONE 0x1000
#define BF_MSC_STAT_DATA_TRAN_DONE(v) (((v) & 0x1) << 12)
#define BFM_MSC_STAT_DATA_TRAN_DONE(v) BM_MSC_STAT_DATA_TRAN_DONE
#define BF_MSC_STAT_DATA_TRAN_DONE_V(e) BF_MSC_STAT_DATA_TRAN_DONE(BV_MSC_STAT_DATA_TRAN_DONE__##e)
#define BFM_MSC_STAT_DATA_TRAN_DONE_V(v) BM_MSC_STAT_DATA_TRAN_DONE
#define BP_MSC_STAT_END_CMD_RES 11
#define BM_MSC_STAT_END_CMD_RES 0x800
#define BF_MSC_STAT_END_CMD_RES(v) (((v) & 0x1) << 11)
#define BFM_MSC_STAT_END_CMD_RES(v) BM_MSC_STAT_END_CMD_RES
#define BF_MSC_STAT_END_CMD_RES_V(e) BF_MSC_STAT_END_CMD_RES(BV_MSC_STAT_END_CMD_RES__##e)
#define BFM_MSC_STAT_END_CMD_RES_V(v) BM_MSC_STAT_END_CMD_RES
#define BP_MSC_STAT_DATA_FIFO_AFULL 10
#define BM_MSC_STAT_DATA_FIFO_AFULL 0x400
#define BF_MSC_STAT_DATA_FIFO_AFULL(v) (((v) & 0x1) << 10)
#define BFM_MSC_STAT_DATA_FIFO_AFULL(v) BM_MSC_STAT_DATA_FIFO_AFULL
#define BF_MSC_STAT_DATA_FIFO_AFULL_V(e) BF_MSC_STAT_DATA_FIFO_AFULL(BV_MSC_STAT_DATA_FIFO_AFULL__##e)
#define BFM_MSC_STAT_DATA_FIFO_AFULL_V(v) BM_MSC_STAT_DATA_FIFO_AFULL
#define BP_MSC_STAT_IS_READ_WAIT 9
#define BM_MSC_STAT_IS_READ_WAIT 0x200
#define BF_MSC_STAT_IS_READ_WAIT(v) (((v) & 0x1) << 9)
#define BFM_MSC_STAT_IS_READ_WAIT(v) BM_MSC_STAT_IS_READ_WAIT
#define BF_MSC_STAT_IS_READ_WAIT_V(e) BF_MSC_STAT_IS_READ_WAIT(BV_MSC_STAT_IS_READ_WAIT__##e)
#define BFM_MSC_STAT_IS_READ_WAIT_V(v) BM_MSC_STAT_IS_READ_WAIT
#define BP_MSC_STAT_CLOCK_EN 8
#define BM_MSC_STAT_CLOCK_EN 0x100
#define BF_MSC_STAT_CLOCK_EN(v) (((v) & 0x1) << 8)
#define BFM_MSC_STAT_CLOCK_EN(v) BM_MSC_STAT_CLOCK_EN
#define BF_MSC_STAT_CLOCK_EN_V(e) BF_MSC_STAT_CLOCK_EN(BV_MSC_STAT_CLOCK_EN__##e)
#define BFM_MSC_STAT_CLOCK_EN_V(v) BM_MSC_STAT_CLOCK_EN
#define BP_MSC_STAT_DATA_FIFO_FULL 7
#define BM_MSC_STAT_DATA_FIFO_FULL 0x80
#define BF_MSC_STAT_DATA_FIFO_FULL(v) (((v) & 0x1) << 7)
#define BFM_MSC_STAT_DATA_FIFO_FULL(v) BM_MSC_STAT_DATA_FIFO_FULL
#define BF_MSC_STAT_DATA_FIFO_FULL_V(e) BF_MSC_STAT_DATA_FIFO_FULL(BV_MSC_STAT_DATA_FIFO_FULL__##e)
#define BFM_MSC_STAT_DATA_FIFO_FULL_V(v) BM_MSC_STAT_DATA_FIFO_FULL
#define BP_MSC_STAT_DATA_FIFO_EMPTY 6
#define BM_MSC_STAT_DATA_FIFO_EMPTY 0x40
#define BF_MSC_STAT_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 6)
#define BFM_MSC_STAT_DATA_FIFO_EMPTY(v) BM_MSC_STAT_DATA_FIFO_EMPTY
#define BF_MSC_STAT_DATA_FIFO_EMPTY_V(e) BF_MSC_STAT_DATA_FIFO_EMPTY(BV_MSC_STAT_DATA_FIFO_EMPTY__##e)
#define BFM_MSC_STAT_DATA_FIFO_EMPTY_V(v) BM_MSC_STAT_DATA_FIFO_EMPTY
#define BP_MSC_STAT_CRC_RES_ERROR 5
#define BM_MSC_STAT_CRC_RES_ERROR 0x20
#define BF_MSC_STAT_CRC_RES_ERROR(v) (((v) & 0x1) << 5)
#define BFM_MSC_STAT_CRC_RES_ERROR(v) BM_MSC_STAT_CRC_RES_ERROR
#define BF_MSC_STAT_CRC_RES_ERROR_V(e) BF_MSC_STAT_CRC_RES_ERROR(BV_MSC_STAT_CRC_RES_ERROR__##e)
#define BFM_MSC_STAT_CRC_RES_ERROR_V(v) BM_MSC_STAT_CRC_RES_ERROR
#define BP_MSC_STAT_CRC_READ_ERROR 4
#define BM_MSC_STAT_CRC_READ_ERROR 0x10
#define BF_MSC_STAT_CRC_READ_ERROR(v) (((v) & 0x1) << 4)
#define BFM_MSC_STAT_CRC_READ_ERROR(v) BM_MSC_STAT_CRC_READ_ERROR
#define BF_MSC_STAT_CRC_READ_ERROR_V(e) BF_MSC_STAT_CRC_READ_ERROR(BV_MSC_STAT_CRC_READ_ERROR__##e)
#define BFM_MSC_STAT_CRC_READ_ERROR_V(v) BM_MSC_STAT_CRC_READ_ERROR
#define BP_MSC_STAT_TIME_OUT_RES 1
#define BM_MSC_STAT_TIME_OUT_RES 0x2
#define BF_MSC_STAT_TIME_OUT_RES(v) (((v) & 0x1) << 1)
#define BFM_MSC_STAT_TIME_OUT_RES(v) BM_MSC_STAT_TIME_OUT_RES
#define BF_MSC_STAT_TIME_OUT_RES_V(e) BF_MSC_STAT_TIME_OUT_RES(BV_MSC_STAT_TIME_OUT_RES__##e)
#define BFM_MSC_STAT_TIME_OUT_RES_V(v) BM_MSC_STAT_TIME_OUT_RES
#define BP_MSC_STAT_TIME_OUT_READ 0
#define BM_MSC_STAT_TIME_OUT_READ 0x1
#define BF_MSC_STAT_TIME_OUT_READ(v) (((v) & 0x1) << 0)
#define BFM_MSC_STAT_TIME_OUT_READ(v) BM_MSC_STAT_TIME_OUT_READ
#define BF_MSC_STAT_TIME_OUT_READ_V(e) BF_MSC_STAT_TIME_OUT_READ(BV_MSC_STAT_TIME_OUT_READ__##e)
#define BFM_MSC_STAT_TIME_OUT_READ_V(v) BM_MSC_STAT_TIME_OUT_READ
#define REG_MSC_CMDAT(_n1) jz_reg(MSC_CMDAT(_n1))
#define JA_MSC_CMDAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0xc)
#define JT_MSC_CMDAT(_n1) JIO_32_RW
#define JN_MSC_CMDAT(_n1) MSC_CMDAT
#define JI_MSC_CMDAT(_n1) (_n1)
#define BP_MSC_CMDAT_RTRG 14
#define BM_MSC_CMDAT_RTRG 0xc000
#define BV_MSC_CMDAT_RTRG__GE16 0x0
#define BV_MSC_CMDAT_RTRG__GE32 0x1
#define BV_MSC_CMDAT_RTRG__GE64 0x2
#define BV_MSC_CMDAT_RTRG__GE96 0x3
#define BF_MSC_CMDAT_RTRG(v) (((v) & 0x3) << 14)
#define BFM_MSC_CMDAT_RTRG(v) BM_MSC_CMDAT_RTRG
#define BF_MSC_CMDAT_RTRG_V(e) BF_MSC_CMDAT_RTRG(BV_MSC_CMDAT_RTRG__##e)
#define BFM_MSC_CMDAT_RTRG_V(v) BM_MSC_CMDAT_RTRG
#define BP_MSC_CMDAT_TTRG 12
#define BM_MSC_CMDAT_TTRG 0x3000
#define BV_MSC_CMDAT_TTRG__LE16 0x0
#define BV_MSC_CMDAT_TTRG__LE32 0x1
#define BV_MSC_CMDAT_TTRG__LE64 0x2
#define BV_MSC_CMDAT_TTRG__LE96 0x3
#define BF_MSC_CMDAT_TTRG(v) (((v) & 0x3) << 12)
#define BFM_MSC_CMDAT_TTRG(v) BM_MSC_CMDAT_TTRG
#define BF_MSC_CMDAT_TTRG_V(e) BF_MSC_CMDAT_TTRG(BV_MSC_CMDAT_TTRG__##e)
#define BFM_MSC_CMDAT_TTRG_V(v) BM_MSC_CMDAT_TTRG
#define BP_MSC_CMDAT_BUS_WIDTH 9
#define BM_MSC_CMDAT_BUS_WIDTH 0x600
#define BV_MSC_CMDAT_BUS_WIDTH__1BIT 0x0
#define BV_MSC_CMDAT_BUS_WIDTH__4BIT 0x2
#define BV_MSC_CMDAT_BUS_WIDTH__8BIT 0x3
#define BF_MSC_CMDAT_BUS_WIDTH(v) (((v) & 0x3) << 9)
#define BFM_MSC_CMDAT_BUS_WIDTH(v) BM_MSC_CMDAT_BUS_WIDTH
#define BF_MSC_CMDAT_BUS_WIDTH_V(e) BF_MSC_CMDAT_BUS_WIDTH(BV_MSC_CMDAT_BUS_WIDTH__##e)
#define BFM_MSC_CMDAT_BUS_WIDTH_V(v) BM_MSC_CMDAT_BUS_WIDTH
#define BP_MSC_CMDAT_RESP_FMT 0
#define BM_MSC_CMDAT_RESP_FMT 0x7
#define BF_MSC_CMDAT_RESP_FMT(v) (((v) & 0x7) << 0)
#define BFM_MSC_CMDAT_RESP_FMT(v) BM_MSC_CMDAT_RESP_FMT
#define BF_MSC_CMDAT_RESP_FMT_V(e) BF_MSC_CMDAT_RESP_FMT(BV_MSC_CMDAT_RESP_FMT__##e)
#define BFM_MSC_CMDAT_RESP_FMT_V(v) BM_MSC_CMDAT_RESP_FMT
#define BP_MSC_CMDAT_CCS_EXPECTED 31
#define BM_MSC_CMDAT_CCS_EXPECTED 0x80000000
#define BF_MSC_CMDAT_CCS_EXPECTED(v) (((v) & 0x1) << 31)
#define BFM_MSC_CMDAT_CCS_EXPECTED(v) BM_MSC_CMDAT_CCS_EXPECTED
#define BF_MSC_CMDAT_CCS_EXPECTED_V(e) BF_MSC_CMDAT_CCS_EXPECTED(BV_MSC_CMDAT_CCS_EXPECTED__##e)
#define BFM_MSC_CMDAT_CCS_EXPECTED_V(v) BM_MSC_CMDAT_CCS_EXPECTED
#define BP_MSC_CMDAT_READ_CEATA 30
#define BM_MSC_CMDAT_READ_CEATA 0x40000000
#define BF_MSC_CMDAT_READ_CEATA(v) (((v) & 0x1) << 30)
#define BFM_MSC_CMDAT_READ_CEATA(v) BM_MSC_CMDAT_READ_CEATA
#define BF_MSC_CMDAT_READ_CEATA_V(e) BF_MSC_CMDAT_READ_CEATA(BV_MSC_CMDAT_READ_CEATA__##e)
#define BFM_MSC_CMDAT_READ_CEATA_V(v) BM_MSC_CMDAT_READ_CEATA
#define BP_MSC_CMDAT_DIS_BOOT 27
#define BM_MSC_CMDAT_DIS_BOOT 0x8000000
#define BF_MSC_CMDAT_DIS_BOOT(v) (((v) & 0x1) << 27)
#define BFM_MSC_CMDAT_DIS_BOOT(v) BM_MSC_CMDAT_DIS_BOOT
#define BF_MSC_CMDAT_DIS_BOOT_V(e) BF_MSC_CMDAT_DIS_BOOT(BV_MSC_CMDAT_DIS_BOOT__##e)
#define BFM_MSC_CMDAT_DIS_BOOT_V(v) BM_MSC_CMDAT_DIS_BOOT
#define BP_MSC_CMDAT_EXP_BOOT_ACK 25
#define BM_MSC_CMDAT_EXP_BOOT_ACK 0x2000000
#define BF_MSC_CMDAT_EXP_BOOT_ACK(v) (((v) & 0x1) << 25)
#define BFM_MSC_CMDAT_EXP_BOOT_ACK(v) BM_MSC_CMDAT_EXP_BOOT_ACK
#define BF_MSC_CMDAT_EXP_BOOT_ACK_V(e) BF_MSC_CMDAT_EXP_BOOT_ACK(BV_MSC_CMDAT_EXP_BOOT_ACK__##e)
#define BFM_MSC_CMDAT_EXP_BOOT_ACK_V(v) BM_MSC_CMDAT_EXP_BOOT_ACK
#define BP_MSC_CMDAT_BOOT_MODE 24
#define BM_MSC_CMDAT_BOOT_MODE 0x1000000
#define BF_MSC_CMDAT_BOOT_MODE(v) (((v) & 0x1) << 24)
#define BFM_MSC_CMDAT_BOOT_MODE(v) BM_MSC_CMDAT_BOOT_MODE
#define BF_MSC_CMDAT_BOOT_MODE_V(e) BF_MSC_CMDAT_BOOT_MODE(BV_MSC_CMDAT_BOOT_MODE__##e)
#define BFM_MSC_CMDAT_BOOT_MODE_V(v) BM_MSC_CMDAT_BOOT_MODE
#define BP_MSC_CMDAT_SDIO_PRDT 17
#define BM_MSC_CMDAT_SDIO_PRDT 0x20000
#define BF_MSC_CMDAT_SDIO_PRDT(v) (((v) & 0x1) << 17)
#define BFM_MSC_CMDAT_SDIO_PRDT(v) BM_MSC_CMDAT_SDIO_PRDT
#define BF_MSC_CMDAT_SDIO_PRDT_V(e) BF_MSC_CMDAT_SDIO_PRDT(BV_MSC_CMDAT_SDIO_PRDT__##e)
#define BFM_MSC_CMDAT_SDIO_PRDT_V(v) BM_MSC_CMDAT_SDIO_PRDT
#define BP_MSC_CMDAT_AUTO_CMD12 16
#define BM_MSC_CMDAT_AUTO_CMD12 0x10000
#define BF_MSC_CMDAT_AUTO_CMD12(v) (((v) & 0x1) << 16)
#define BFM_MSC_CMDAT_AUTO_CMD12(v) BM_MSC_CMDAT_AUTO_CMD12
#define BF_MSC_CMDAT_AUTO_CMD12_V(e) BF_MSC_CMDAT_AUTO_CMD12(BV_MSC_CMDAT_AUTO_CMD12__##e)
#define BFM_MSC_CMDAT_AUTO_CMD12_V(v) BM_MSC_CMDAT_AUTO_CMD12
#define BP_MSC_CMDAT_IO_ABORT 11
#define BM_MSC_CMDAT_IO_ABORT 0x800
#define BF_MSC_CMDAT_IO_ABORT(v) (((v) & 0x1) << 11)
#define BFM_MSC_CMDAT_IO_ABORT(v) BM_MSC_CMDAT_IO_ABORT
#define BF_MSC_CMDAT_IO_ABORT_V(e) BF_MSC_CMDAT_IO_ABORT(BV_MSC_CMDAT_IO_ABORT__##e)
#define BFM_MSC_CMDAT_IO_ABORT_V(v) BM_MSC_CMDAT_IO_ABORT
#define BP_MSC_CMDAT_INIT 7
#define BM_MSC_CMDAT_INIT 0x80
#define BF_MSC_CMDAT_INIT(v) (((v) & 0x1) << 7)
#define BFM_MSC_CMDAT_INIT(v) BM_MSC_CMDAT_INIT
#define BF_MSC_CMDAT_INIT_V(e) BF_MSC_CMDAT_INIT(BV_MSC_CMDAT_INIT__##e)
#define BFM_MSC_CMDAT_INIT_V(v) BM_MSC_CMDAT_INIT
#define BP_MSC_CMDAT_BUSY 6
#define BM_MSC_CMDAT_BUSY 0x40
#define BF_MSC_CMDAT_BUSY(v) (((v) & 0x1) << 6)
#define BFM_MSC_CMDAT_BUSY(v) BM_MSC_CMDAT_BUSY
#define BF_MSC_CMDAT_BUSY_V(e) BF_MSC_CMDAT_BUSY(BV_MSC_CMDAT_BUSY__##e)
#define BFM_MSC_CMDAT_BUSY_V(v) BM_MSC_CMDAT_BUSY
#define BP_MSC_CMDAT_STREAM_BLOCK 5
#define BM_MSC_CMDAT_STREAM_BLOCK 0x20
#define BF_MSC_CMDAT_STREAM_BLOCK(v) (((v) & 0x1) << 5)
#define BFM_MSC_CMDAT_STREAM_BLOCK(v) BM_MSC_CMDAT_STREAM_BLOCK
#define BF_MSC_CMDAT_STREAM_BLOCK_V(e) BF_MSC_CMDAT_STREAM_BLOCK(BV_MSC_CMDAT_STREAM_BLOCK__##e)
#define BFM_MSC_CMDAT_STREAM_BLOCK_V(v) BM_MSC_CMDAT_STREAM_BLOCK
#define BP_MSC_CMDAT_WRITE_READ 4
#define BM_MSC_CMDAT_WRITE_READ 0x10
#define BF_MSC_CMDAT_WRITE_READ(v) (((v) & 0x1) << 4)
#define BFM_MSC_CMDAT_WRITE_READ(v) BM_MSC_CMDAT_WRITE_READ
#define BF_MSC_CMDAT_WRITE_READ_V(e) BF_MSC_CMDAT_WRITE_READ(BV_MSC_CMDAT_WRITE_READ__##e)
#define BFM_MSC_CMDAT_WRITE_READ_V(v) BM_MSC_CMDAT_WRITE_READ
#define BP_MSC_CMDAT_DATA_EN 3
#define BM_MSC_CMDAT_DATA_EN 0x8
#define BF_MSC_CMDAT_DATA_EN(v) (((v) & 0x1) << 3)
#define BFM_MSC_CMDAT_DATA_EN(v) BM_MSC_CMDAT_DATA_EN
#define BF_MSC_CMDAT_DATA_EN_V(e) BF_MSC_CMDAT_DATA_EN(BV_MSC_CMDAT_DATA_EN__##e)
#define BFM_MSC_CMDAT_DATA_EN_V(v) BM_MSC_CMDAT_DATA_EN
#define REG_MSC_IMASK(_n1) jz_reg(MSC_IMASK(_n1))
#define JA_MSC_IMASK(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x24)
#define JT_MSC_IMASK(_n1) JIO_32_RW
#define JN_MSC_IMASK(_n1) MSC_IMASK
#define JI_MSC_IMASK(_n1) (_n1)
#define BP_MSC_IMASK_PINS 24
#define BM_MSC_IMASK_PINS 0x1f000000
#define BF_MSC_IMASK_PINS(v) (((v) & 0x1f) << 24)
#define BFM_MSC_IMASK_PINS(v) BM_MSC_IMASK_PINS
#define BF_MSC_IMASK_PINS_V(e) BF_MSC_IMASK_PINS(BV_MSC_IMASK_PINS__##e)
#define BFM_MSC_IMASK_PINS_V(v) BM_MSC_IMASK_PINS
#define BP_MSC_IMASK_DMA_DATA_DONE 31
#define BM_MSC_IMASK_DMA_DATA_DONE 0x80000000
#define BF_MSC_IMASK_DMA_DATA_DONE(v) (((v) & 0x1) << 31)
#define BFM_MSC_IMASK_DMA_DATA_DONE(v) BM_MSC_IMASK_DMA_DATA_DONE
#define BF_MSC_IMASK_DMA_DATA_DONE_V(e) BF_MSC_IMASK_DMA_DATA_DONE(BV_MSC_IMASK_DMA_DATA_DONE__##e)
#define BFM_MSC_IMASK_DMA_DATA_DONE_V(v) BM_MSC_IMASK_DMA_DATA_DONE
#define BP_MSC_IMASK_WR_ALL_DONE 23
#define BM_MSC_IMASK_WR_ALL_DONE 0x800000
#define BF_MSC_IMASK_WR_ALL_DONE(v) (((v) & 0x1) << 23)
#define BFM_MSC_IMASK_WR_ALL_DONE(v) BM_MSC_IMASK_WR_ALL_DONE
#define BF_MSC_IMASK_WR_ALL_DONE_V(e) BF_MSC_IMASK_WR_ALL_DONE(BV_MSC_IMASK_WR_ALL_DONE__##e)
#define BFM_MSC_IMASK_WR_ALL_DONE_V(v) BM_MSC_IMASK_WR_ALL_DONE
#define BP_MSC_IMASK_BCE 20
#define BM_MSC_IMASK_BCE 0x100000
#define BF_MSC_IMASK_BCE(v) (((v) & 0x1) << 20)
#define BFM_MSC_IMASK_BCE(v) BM_MSC_IMASK_BCE
#define BF_MSC_IMASK_BCE_V(e) BF_MSC_IMASK_BCE(BV_MSC_IMASK_BCE__##e)
#define BFM_MSC_IMASK_BCE_V(v) BM_MSC_IMASK_BCE
#define BP_MSC_IMASK_BDE 19
#define BM_MSC_IMASK_BDE 0x80000
#define BF_MSC_IMASK_BDE(v) (((v) & 0x1) << 19)
#define BFM_MSC_IMASK_BDE(v) BM_MSC_IMASK_BDE
#define BF_MSC_IMASK_BDE_V(e) BF_MSC_IMASK_BDE(BV_MSC_IMASK_BDE__##e)
#define BFM_MSC_IMASK_BDE_V(v) BM_MSC_IMASK_BDE
#define BP_MSC_IMASK_BAE 18
#define BM_MSC_IMASK_BAE 0x40000
#define BF_MSC_IMASK_BAE(v) (((v) & 0x1) << 18)
#define BFM_MSC_IMASK_BAE(v) BM_MSC_IMASK_BAE
#define BF_MSC_IMASK_BAE_V(e) BF_MSC_IMASK_BAE(BV_MSC_IMASK_BAE__##e)
#define BFM_MSC_IMASK_BAE_V(v) BM_MSC_IMASK_BAE
#define BP_MSC_IMASK_BAR 17
#define BM_MSC_IMASK_BAR 0x20000
#define BF_MSC_IMASK_BAR(v) (((v) & 0x1) << 17)
#define BFM_MSC_IMASK_BAR(v) BM_MSC_IMASK_BAR
#define BF_MSC_IMASK_BAR_V(e) BF_MSC_IMASK_BAR(BV_MSC_IMASK_BAR__##e)
#define BFM_MSC_IMASK_BAR_V(v) BM_MSC_IMASK_BAR
#define BP_MSC_IMASK_DMAEND 16
#define BM_MSC_IMASK_DMAEND 0x10000
#define BF_MSC_IMASK_DMAEND(v) (((v) & 0x1) << 16)
#define BFM_MSC_IMASK_DMAEND(v) BM_MSC_IMASK_DMAEND
#define BF_MSC_IMASK_DMAEND_V(e) BF_MSC_IMASK_DMAEND(BV_MSC_IMASK_DMAEND__##e)
#define BFM_MSC_IMASK_DMAEND_V(v) BM_MSC_IMASK_DMAEND
#define BP_MSC_IMASK_AUTO_CMD12_DONE 15
#define BM_MSC_IMASK_AUTO_CMD12_DONE 0x8000
#define BF_MSC_IMASK_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15)
#define BFM_MSC_IMASK_AUTO_CMD12_DONE(v) BM_MSC_IMASK_AUTO_CMD12_DONE
#define BF_MSC_IMASK_AUTO_CMD12_DONE_V(e) BF_MSC_IMASK_AUTO_CMD12_DONE(BV_MSC_IMASK_AUTO_CMD12_DONE__##e)
#define BFM_MSC_IMASK_AUTO_CMD12_DONE_V(v) BM_MSC_IMASK_AUTO_CMD12_DONE
#define BP_MSC_IMASK_DATA_FIFO_FULL 14
#define BM_MSC_IMASK_DATA_FIFO_FULL 0x4000
#define BF_MSC_IMASK_DATA_FIFO_FULL(v) (((v) & 0x1) << 14)
#define BFM_MSC_IMASK_DATA_FIFO_FULL(v) BM_MSC_IMASK_DATA_FIFO_FULL
#define BF_MSC_IMASK_DATA_FIFO_FULL_V(e) BF_MSC_IMASK_DATA_FIFO_FULL(BV_MSC_IMASK_DATA_FIFO_FULL__##e)
#define BFM_MSC_IMASK_DATA_FIFO_FULL_V(v) BM_MSC_IMASK_DATA_FIFO_FULL
#define BP_MSC_IMASK_DATA_FIFO_EMPTY 13
#define BM_MSC_IMASK_DATA_FIFO_EMPTY 0x2000
#define BF_MSC_IMASK_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13)
#define BFM_MSC_IMASK_DATA_FIFO_EMPTY(v) BM_MSC_IMASK_DATA_FIFO_EMPTY
#define BF_MSC_IMASK_DATA_FIFO_EMPTY_V(e) BF_MSC_IMASK_DATA_FIFO_EMPTY(BV_MSC_IMASK_DATA_FIFO_EMPTY__##e)
#define BFM_MSC_IMASK_DATA_FIFO_EMPTY_V(v) BM_MSC_IMASK_DATA_FIFO_EMPTY
#define BP_MSC_IMASK_CRC_RES_ERROR 12
#define BM_MSC_IMASK_CRC_RES_ERROR 0x1000
#define BF_MSC_IMASK_CRC_RES_ERROR(v) (((v) & 0x1) << 12)
#define BFM_MSC_IMASK_CRC_RES_ERROR(v) BM_MSC_IMASK_CRC_RES_ERROR
#define BF_MSC_IMASK_CRC_RES_ERROR_V(e) BF_MSC_IMASK_CRC_RES_ERROR(BV_MSC_IMASK_CRC_RES_ERROR__##e)
#define BFM_MSC_IMASK_CRC_RES_ERROR_V(v) BM_MSC_IMASK_CRC_RES_ERROR
#define BP_MSC_IMASK_CRC_READ_ERROR 11
#define BM_MSC_IMASK_CRC_READ_ERROR 0x800
#define BF_MSC_IMASK_CRC_READ_ERROR(v) (((v) & 0x1) << 11)
#define BFM_MSC_IMASK_CRC_READ_ERROR(v) BM_MSC_IMASK_CRC_READ_ERROR
#define BF_MSC_IMASK_CRC_READ_ERROR_V(e) BF_MSC_IMASK_CRC_READ_ERROR(BV_MSC_IMASK_CRC_READ_ERROR__##e)
#define BFM_MSC_IMASK_CRC_READ_ERROR_V(v) BM_MSC_IMASK_CRC_READ_ERROR
#define BP_MSC_IMASK_CRC_WRITE_ERROR 10
#define BM_MSC_IMASK_CRC_WRITE_ERROR 0x400
#define BF_MSC_IMASK_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10)
#define BFM_MSC_IMASK_CRC_WRITE_ERROR(v) BM_MSC_IMASK_CRC_WRITE_ERROR
#define BF_MSC_IMASK_CRC_WRITE_ERROR_V(e) BF_MSC_IMASK_CRC_WRITE_ERROR(BV_MSC_IMASK_CRC_WRITE_ERROR__##e)
#define BFM_MSC_IMASK_CRC_WRITE_ERROR_V(v) BM_MSC_IMASK_CRC_WRITE_ERROR
#define BP_MSC_IMASK_TIME_OUT_RES 9
#define BM_MSC_IMASK_TIME_OUT_RES 0x200
#define BF_MSC_IMASK_TIME_OUT_RES(v) (((v) & 0x1) << 9)
#define BFM_MSC_IMASK_TIME_OUT_RES(v) BM_MSC_IMASK_TIME_OUT_RES
#define BF_MSC_IMASK_TIME_OUT_RES_V(e) BF_MSC_IMASK_TIME_OUT_RES(BV_MSC_IMASK_TIME_OUT_RES__##e)
#define BFM_MSC_IMASK_TIME_OUT_RES_V(v) BM_MSC_IMASK_TIME_OUT_RES
#define BP_MSC_IMASK_TIME_OUT_READ 8
#define BM_MSC_IMASK_TIME_OUT_READ 0x100
#define BF_MSC_IMASK_TIME_OUT_READ(v) (((v) & 0x1) << 8)
#define BFM_MSC_IMASK_TIME_OUT_READ(v) BM_MSC_IMASK_TIME_OUT_READ
#define BF_MSC_IMASK_TIME_OUT_READ_V(e) BF_MSC_IMASK_TIME_OUT_READ(BV_MSC_IMASK_TIME_OUT_READ__##e)
#define BFM_MSC_IMASK_TIME_OUT_READ_V(v) BM_MSC_IMASK_TIME_OUT_READ
#define BP_MSC_IMASK_SDIO 7
#define BM_MSC_IMASK_SDIO 0x80
#define BF_MSC_IMASK_SDIO(v) (((v) & 0x1) << 7)
#define BFM_MSC_IMASK_SDIO(v) BM_MSC_IMASK_SDIO
#define BF_MSC_IMASK_SDIO_V(e) BF_MSC_IMASK_SDIO(BV_MSC_IMASK_SDIO__##e)
#define BFM_MSC_IMASK_SDIO_V(v) BM_MSC_IMASK_SDIO
#define BP_MSC_IMASK_TXFIFO_WR_REQ 6
#define BM_MSC_IMASK_TXFIFO_WR_REQ 0x40
#define BF_MSC_IMASK_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6)
#define BFM_MSC_IMASK_TXFIFO_WR_REQ(v) BM_MSC_IMASK_TXFIFO_WR_REQ
#define BF_MSC_IMASK_TXFIFO_WR_REQ_V(e) BF_MSC_IMASK_TXFIFO_WR_REQ(BV_MSC_IMASK_TXFIFO_WR_REQ__##e)
#define BFM_MSC_IMASK_TXFIFO_WR_REQ_V(v) BM_MSC_IMASK_TXFIFO_WR_REQ
#define BP_MSC_IMASK_RXFIFO_RD_REQ 5
#define BM_MSC_IMASK_RXFIFO_RD_REQ 0x20
#define BF_MSC_IMASK_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5)
#define BFM_MSC_IMASK_RXFIFO_RD_REQ(v) BM_MSC_IMASK_RXFIFO_RD_REQ
#define BF_MSC_IMASK_RXFIFO_RD_REQ_V(e) BF_MSC_IMASK_RXFIFO_RD_REQ(BV_MSC_IMASK_RXFIFO_RD_REQ__##e)
#define BFM_MSC_IMASK_RXFIFO_RD_REQ_V(v) BM_MSC_IMASK_RXFIFO_RD_REQ
#define BP_MSC_IMASK_END_CMD_RES 2
#define BM_MSC_IMASK_END_CMD_RES 0x4
#define BF_MSC_IMASK_END_CMD_RES(v) (((v) & 0x1) << 2)
#define BFM_MSC_IMASK_END_CMD_RES(v) BM_MSC_IMASK_END_CMD_RES
#define BF_MSC_IMASK_END_CMD_RES_V(e) BF_MSC_IMASK_END_CMD_RES(BV_MSC_IMASK_END_CMD_RES__##e)
#define BFM_MSC_IMASK_END_CMD_RES_V(v) BM_MSC_IMASK_END_CMD_RES
#define BP_MSC_IMASK_PROG_DONE 1
#define BM_MSC_IMASK_PROG_DONE 0x2
#define BF_MSC_IMASK_PROG_DONE(v) (((v) & 0x1) << 1)
#define BFM_MSC_IMASK_PROG_DONE(v) BM_MSC_IMASK_PROG_DONE
#define BF_MSC_IMASK_PROG_DONE_V(e) BF_MSC_IMASK_PROG_DONE(BV_MSC_IMASK_PROG_DONE__##e)
#define BFM_MSC_IMASK_PROG_DONE_V(v) BM_MSC_IMASK_PROG_DONE
#define BP_MSC_IMASK_DATA_TRAN_DONE 0
#define BM_MSC_IMASK_DATA_TRAN_DONE 0x1
#define BF_MSC_IMASK_DATA_TRAN_DONE(v) (((v) & 0x1) << 0)
#define BFM_MSC_IMASK_DATA_TRAN_DONE(v) BM_MSC_IMASK_DATA_TRAN_DONE
#define BF_MSC_IMASK_DATA_TRAN_DONE_V(e) BF_MSC_IMASK_DATA_TRAN_DONE(BV_MSC_IMASK_DATA_TRAN_DONE__##e)
#define BFM_MSC_IMASK_DATA_TRAN_DONE_V(v) BM_MSC_IMASK_DATA_TRAN_DONE
#define REG_MSC_IFLAG(_n1) jz_reg(MSC_IFLAG(_n1))
#define JA_MSC_IFLAG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x28)
#define JT_MSC_IFLAG(_n1) JIO_32_RW
#define JN_MSC_IFLAG(_n1) MSC_IFLAG
#define JI_MSC_IFLAG(_n1) (_n1)
#define BP_MSC_IFLAG_PINS 24
#define BM_MSC_IFLAG_PINS 0x1f000000
#define BF_MSC_IFLAG_PINS(v) (((v) & 0x1f) << 24)
#define BFM_MSC_IFLAG_PINS(v) BM_MSC_IFLAG_PINS
#define BF_MSC_IFLAG_PINS_V(e) BF_MSC_IFLAG_PINS(BV_MSC_IFLAG_PINS__##e)
#define BFM_MSC_IFLAG_PINS_V(v) BM_MSC_IFLAG_PINS
#define BP_MSC_IFLAG_DMA_DATA_DONE 31
#define BM_MSC_IFLAG_DMA_DATA_DONE 0x80000000
#define BF_MSC_IFLAG_DMA_DATA_DONE(v) (((v) & 0x1) << 31)
#define BFM_MSC_IFLAG_DMA_DATA_DONE(v) BM_MSC_IFLAG_DMA_DATA_DONE
#define BF_MSC_IFLAG_DMA_DATA_DONE_V(e) BF_MSC_IFLAG_DMA_DATA_DONE(BV_MSC_IFLAG_DMA_DATA_DONE__##e)
#define BFM_MSC_IFLAG_DMA_DATA_DONE_V(v) BM_MSC_IFLAG_DMA_DATA_DONE
#define BP_MSC_IFLAG_WR_ALL_DONE 23
#define BM_MSC_IFLAG_WR_ALL_DONE 0x800000
#define BF_MSC_IFLAG_WR_ALL_DONE(v) (((v) & 0x1) << 23)
#define BFM_MSC_IFLAG_WR_ALL_DONE(v) BM_MSC_IFLAG_WR_ALL_DONE
#define BF_MSC_IFLAG_WR_ALL_DONE_V(e) BF_MSC_IFLAG_WR_ALL_DONE(BV_MSC_IFLAG_WR_ALL_DONE__##e)
#define BFM_MSC_IFLAG_WR_ALL_DONE_V(v) BM_MSC_IFLAG_WR_ALL_DONE
#define BP_MSC_IFLAG_BCE 20
#define BM_MSC_IFLAG_BCE 0x100000
#define BF_MSC_IFLAG_BCE(v) (((v) & 0x1) << 20)
#define BFM_MSC_IFLAG_BCE(v) BM_MSC_IFLAG_BCE
#define BF_MSC_IFLAG_BCE_V(e) BF_MSC_IFLAG_BCE(BV_MSC_IFLAG_BCE__##e)
#define BFM_MSC_IFLAG_BCE_V(v) BM_MSC_IFLAG_BCE
#define BP_MSC_IFLAG_BDE 19
#define BM_MSC_IFLAG_BDE 0x80000
#define BF_MSC_IFLAG_BDE(v) (((v) & 0x1) << 19)
#define BFM_MSC_IFLAG_BDE(v) BM_MSC_IFLAG_BDE
#define BF_MSC_IFLAG_BDE_V(e) BF_MSC_IFLAG_BDE(BV_MSC_IFLAG_BDE__##e)
#define BFM_MSC_IFLAG_BDE_V(v) BM_MSC_IFLAG_BDE
#define BP_MSC_IFLAG_BAE 18
#define BM_MSC_IFLAG_BAE 0x40000
#define BF_MSC_IFLAG_BAE(v) (((v) & 0x1) << 18)
#define BFM_MSC_IFLAG_BAE(v) BM_MSC_IFLAG_BAE
#define BF_MSC_IFLAG_BAE_V(e) BF_MSC_IFLAG_BAE(BV_MSC_IFLAG_BAE__##e)
#define BFM_MSC_IFLAG_BAE_V(v) BM_MSC_IFLAG_BAE
#define BP_MSC_IFLAG_BAR 17
#define BM_MSC_IFLAG_BAR 0x20000
#define BF_MSC_IFLAG_BAR(v) (((v) & 0x1) << 17)
#define BFM_MSC_IFLAG_BAR(v) BM_MSC_IFLAG_BAR
#define BF_MSC_IFLAG_BAR_V(e) BF_MSC_IFLAG_BAR(BV_MSC_IFLAG_BAR__##e)
#define BFM_MSC_IFLAG_BAR_V(v) BM_MSC_IFLAG_BAR
#define BP_MSC_IFLAG_DMAEND 16
#define BM_MSC_IFLAG_DMAEND 0x10000
#define BF_MSC_IFLAG_DMAEND(v) (((v) & 0x1) << 16)
#define BFM_MSC_IFLAG_DMAEND(v) BM_MSC_IFLAG_DMAEND
#define BF_MSC_IFLAG_DMAEND_V(e) BF_MSC_IFLAG_DMAEND(BV_MSC_IFLAG_DMAEND__##e)
#define BFM_MSC_IFLAG_DMAEND_V(v) BM_MSC_IFLAG_DMAEND
#define BP_MSC_IFLAG_AUTO_CMD12_DONE 15
#define BM_MSC_IFLAG_AUTO_CMD12_DONE 0x8000
#define BF_MSC_IFLAG_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15)
#define BFM_MSC_IFLAG_AUTO_CMD12_DONE(v) BM_MSC_IFLAG_AUTO_CMD12_DONE
#define BF_MSC_IFLAG_AUTO_CMD12_DONE_V(e) BF_MSC_IFLAG_AUTO_CMD12_DONE(BV_MSC_IFLAG_AUTO_CMD12_DONE__##e)
#define BFM_MSC_IFLAG_AUTO_CMD12_DONE_V(v) BM_MSC_IFLAG_AUTO_CMD12_DONE
#define BP_MSC_IFLAG_DATA_FIFO_FULL 14
#define BM_MSC_IFLAG_DATA_FIFO_FULL 0x4000
#define BF_MSC_IFLAG_DATA_FIFO_FULL(v) (((v) & 0x1) << 14)
#define BFM_MSC_IFLAG_DATA_FIFO_FULL(v) BM_MSC_IFLAG_DATA_FIFO_FULL
#define BF_MSC_IFLAG_DATA_FIFO_FULL_V(e) BF_MSC_IFLAG_DATA_FIFO_FULL(BV_MSC_IFLAG_DATA_FIFO_FULL__##e)
#define BFM_MSC_IFLAG_DATA_FIFO_FULL_V(v) BM_MSC_IFLAG_DATA_FIFO_FULL
#define BP_MSC_IFLAG_DATA_FIFO_EMPTY 13
#define BM_MSC_IFLAG_DATA_FIFO_EMPTY 0x2000
#define BF_MSC_IFLAG_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13)
#define BFM_MSC_IFLAG_DATA_FIFO_EMPTY(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY
#define BF_MSC_IFLAG_DATA_FIFO_EMPTY_V(e) BF_MSC_IFLAG_DATA_FIFO_EMPTY(BV_MSC_IFLAG_DATA_FIFO_EMPTY__##e)
#define BFM_MSC_IFLAG_DATA_FIFO_EMPTY_V(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY
#define BP_MSC_IFLAG_CRC_RES_ERROR 12
#define BM_MSC_IFLAG_CRC_RES_ERROR 0x1000
#define BF_MSC_IFLAG_CRC_RES_ERROR(v) (((v) & 0x1) << 12)
#define BFM_MSC_IFLAG_CRC_RES_ERROR(v) BM_MSC_IFLAG_CRC_RES_ERROR
#define BF_MSC_IFLAG_CRC_RES_ERROR_V(e) BF_MSC_IFLAG_CRC_RES_ERROR(BV_MSC_IFLAG_CRC_RES_ERROR__##e)
#define BFM_MSC_IFLAG_CRC_RES_ERROR_V(v) BM_MSC_IFLAG_CRC_RES_ERROR
#define BP_MSC_IFLAG_CRC_READ_ERROR 11
#define BM_MSC_IFLAG_CRC_READ_ERROR 0x800
#define BF_MSC_IFLAG_CRC_READ_ERROR(v) (((v) & 0x1) << 11)
#define BFM_MSC_IFLAG_CRC_READ_ERROR(v) BM_MSC_IFLAG_CRC_READ_ERROR
#define BF_MSC_IFLAG_CRC_READ_ERROR_V(e) BF_MSC_IFLAG_CRC_READ_ERROR(BV_MSC_IFLAG_CRC_READ_ERROR__##e)
#define BFM_MSC_IFLAG_CRC_READ_ERROR_V(v) BM_MSC_IFLAG_CRC_READ_ERROR
#define BP_MSC_IFLAG_CRC_WRITE_ERROR 10
#define BM_MSC_IFLAG_CRC_WRITE_ERROR 0x400
#define BF_MSC_IFLAG_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10)
#define BFM_MSC_IFLAG_CRC_WRITE_ERROR(v) BM_MSC_IFLAG_CRC_WRITE_ERROR
#define BF_MSC_IFLAG_CRC_WRITE_ERROR_V(e) BF_MSC_IFLAG_CRC_WRITE_ERROR(BV_MSC_IFLAG_CRC_WRITE_ERROR__##e)
#define BFM_MSC_IFLAG_CRC_WRITE_ERROR_V(v) BM_MSC_IFLAG_CRC_WRITE_ERROR
#define BP_MSC_IFLAG_TIME_OUT_RES 9
#define BM_MSC_IFLAG_TIME_OUT_RES 0x200
#define BF_MSC_IFLAG_TIME_OUT_RES(v) (((v) & 0x1) << 9)
#define BFM_MSC_IFLAG_TIME_OUT_RES(v) BM_MSC_IFLAG_TIME_OUT_RES
#define BF_MSC_IFLAG_TIME_OUT_RES_V(e) BF_MSC_IFLAG_TIME_OUT_RES(BV_MSC_IFLAG_TIME_OUT_RES__##e)
#define BFM_MSC_IFLAG_TIME_OUT_RES_V(v) BM_MSC_IFLAG_TIME_OUT_RES
#define BP_MSC_IFLAG_TIME_OUT_READ 8
#define BM_MSC_IFLAG_TIME_OUT_READ 0x100
#define BF_MSC_IFLAG_TIME_OUT_READ(v) (((v) & 0x1) << 8)
#define BFM_MSC_IFLAG_TIME_OUT_READ(v) BM_MSC_IFLAG_TIME_OUT_READ
#define BF_MSC_IFLAG_TIME_OUT_READ_V(e) BF_MSC_IFLAG_TIME_OUT_READ(BV_MSC_IFLAG_TIME_OUT_READ__##e)
#define BFM_MSC_IFLAG_TIME_OUT_READ_V(v) BM_MSC_IFLAG_TIME_OUT_READ
#define BP_MSC_IFLAG_SDIO 7
#define BM_MSC_IFLAG_SDIO 0x80
#define BF_MSC_IFLAG_SDIO(v) (((v) & 0x1) << 7)
#define BFM_MSC_IFLAG_SDIO(v) BM_MSC_IFLAG_SDIO
#define BF_MSC_IFLAG_SDIO_V(e) BF_MSC_IFLAG_SDIO(BV_MSC_IFLAG_SDIO__##e)
#define BFM_MSC_IFLAG_SDIO_V(v) BM_MSC_IFLAG_SDIO
#define BP_MSC_IFLAG_TXFIFO_WR_REQ 6
#define BM_MSC_IFLAG_TXFIFO_WR_REQ 0x40
#define BF_MSC_IFLAG_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6)
#define BFM_MSC_IFLAG_TXFIFO_WR_REQ(v) BM_MSC_IFLAG_TXFIFO_WR_REQ
#define BF_MSC_IFLAG_TXFIFO_WR_REQ_V(e) BF_MSC_IFLAG_TXFIFO_WR_REQ(BV_MSC_IFLAG_TXFIFO_WR_REQ__##e)
#define BFM_MSC_IFLAG_TXFIFO_WR_REQ_V(v) BM_MSC_IFLAG_TXFIFO_WR_REQ
#define BP_MSC_IFLAG_RXFIFO_RD_REQ 5
#define BM_MSC_IFLAG_RXFIFO_RD_REQ 0x20
#define BF_MSC_IFLAG_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5)
#define BFM_MSC_IFLAG_RXFIFO_RD_REQ(v) BM_MSC_IFLAG_RXFIFO_RD_REQ
#define BF_MSC_IFLAG_RXFIFO_RD_REQ_V(e) BF_MSC_IFLAG_RXFIFO_RD_REQ(BV_MSC_IFLAG_RXFIFO_RD_REQ__##e)
#define BFM_MSC_IFLAG_RXFIFO_RD_REQ_V(v) BM_MSC_IFLAG_RXFIFO_RD_REQ
#define BP_MSC_IFLAG_END_CMD_RES 2
#define BM_MSC_IFLAG_END_CMD_RES 0x4
#define BF_MSC_IFLAG_END_CMD_RES(v) (((v) & 0x1) << 2)
#define BFM_MSC_IFLAG_END_CMD_RES(v) BM_MSC_IFLAG_END_CMD_RES
#define BF_MSC_IFLAG_END_CMD_RES_V(e) BF_MSC_IFLAG_END_CMD_RES(BV_MSC_IFLAG_END_CMD_RES__##e)
#define BFM_MSC_IFLAG_END_CMD_RES_V(v) BM_MSC_IFLAG_END_CMD_RES
#define BP_MSC_IFLAG_PROG_DONE 1
#define BM_MSC_IFLAG_PROG_DONE 0x2
#define BF_MSC_IFLAG_PROG_DONE(v) (((v) & 0x1) << 1)
#define BFM_MSC_IFLAG_PROG_DONE(v) BM_MSC_IFLAG_PROG_DONE
#define BF_MSC_IFLAG_PROG_DONE_V(e) BF_MSC_IFLAG_PROG_DONE(BV_MSC_IFLAG_PROG_DONE__##e)
#define BFM_MSC_IFLAG_PROG_DONE_V(v) BM_MSC_IFLAG_PROG_DONE
#define BP_MSC_IFLAG_DATA_TRAN_DONE 0
#define BM_MSC_IFLAG_DATA_TRAN_DONE 0x1
#define BF_MSC_IFLAG_DATA_TRAN_DONE(v) (((v) & 0x1) << 0)
#define BFM_MSC_IFLAG_DATA_TRAN_DONE(v) BM_MSC_IFLAG_DATA_TRAN_DONE
#define BF_MSC_IFLAG_DATA_TRAN_DONE_V(e) BF_MSC_IFLAG_DATA_TRAN_DONE(BV_MSC_IFLAG_DATA_TRAN_DONE__##e)
#define BFM_MSC_IFLAG_DATA_TRAN_DONE_V(v) BM_MSC_IFLAG_DATA_TRAN_DONE
#define REG_MSC_LPM(_n1) jz_reg(MSC_LPM(_n1))
#define JA_MSC_LPM(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x40)
#define JT_MSC_LPM(_n1) JIO_32_RW
#define JN_MSC_LPM(_n1) MSC_LPM
#define JI_MSC_LPM(_n1) (_n1)
#define BP_MSC_LPM_DRV_SEL 30
#define BM_MSC_LPM_DRV_SEL 0xc0000000
#define BV_MSC_LPM_DRV_SEL__FALL_EDGE 0x0
#define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_1NS 0x1
#define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_QTR_PHASE 0x2
#define BF_MSC_LPM_DRV_SEL(v) (((v) & 0x3) << 30)
#define BFM_MSC_LPM_DRV_SEL(v) BM_MSC_LPM_DRV_SEL
#define BF_MSC_LPM_DRV_SEL_V(e) BF_MSC_LPM_DRV_SEL(BV_MSC_LPM_DRV_SEL__##e)
#define BFM_MSC_LPM_DRV_SEL_V(v) BM_MSC_LPM_DRV_SEL
#define BP_MSC_LPM_SMP_SEL 28
#define BM_MSC_LPM_SMP_SEL 0x30000000
#define BV_MSC_LPM_SMP_SEL__RISE_EDGE 0x0
#define BV_MSC_LPM_SMP_SEL__RISE_EDGE_DELAYED 0x1
#define BF_MSC_LPM_SMP_SEL(v) (((v) & 0x3) << 28)
#define BFM_MSC_LPM_SMP_SEL(v) BM_MSC_LPM_SMP_SEL
#define BF_MSC_LPM_SMP_SEL_V(e) BF_MSC_LPM_SMP_SEL(BV_MSC_LPM_SMP_SEL__##e)
#define BFM_MSC_LPM_SMP_SEL_V(v) BM_MSC_LPM_SMP_SEL
#define BP_MSC_LPM_ENABLE 0
#define BM_MSC_LPM_ENABLE 0x1
#define BF_MSC_LPM_ENABLE(v) (((v) & 0x1) << 0)
#define BFM_MSC_LPM_ENABLE(v) BM_MSC_LPM_ENABLE
#define BF_MSC_LPM_ENABLE_V(e) BF_MSC_LPM_ENABLE(BV_MSC_LPM_ENABLE__##e)
#define BFM_MSC_LPM_ENABLE_V(v) BM_MSC_LPM_ENABLE
#define REG_MSC_DMAC(_n1) jz_reg(MSC_DMAC(_n1))
#define JA_MSC_DMAC(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x44)
#define JT_MSC_DMAC(_n1) JIO_32_RW
#define JN_MSC_DMAC(_n1) MSC_DMAC
#define JI_MSC_DMAC(_n1) (_n1)
#define BP_MSC_DMAC_ADDR_OFFSET 5
#define BM_MSC_DMAC_ADDR_OFFSET 0x60
#define BF_MSC_DMAC_ADDR_OFFSET(v) (((v) & 0x3) << 5)
#define BFM_MSC_DMAC_ADDR_OFFSET(v) BM_MSC_DMAC_ADDR_OFFSET
#define BF_MSC_DMAC_ADDR_OFFSET_V(e) BF_MSC_DMAC_ADDR_OFFSET(BV_MSC_DMAC_ADDR_OFFSET__##e)
#define BFM_MSC_DMAC_ADDR_OFFSET_V(v) BM_MSC_DMAC_ADDR_OFFSET
#define BP_MSC_DMAC_INCR 2
#define BM_MSC_DMAC_INCR 0xc
#define BF_MSC_DMAC_INCR(v) (((v) & 0x3) << 2)
#define BFM_MSC_DMAC_INCR(v) BM_MSC_DMAC_INCR
#define BF_MSC_DMAC_INCR_V(e) BF_MSC_DMAC_INCR(BV_MSC_DMAC_INCR__##e)
#define BFM_MSC_DMAC_INCR_V(v) BM_MSC_DMAC_INCR
#define BP_MSC_DMAC_MODE_SEL 7
#define BM_MSC_DMAC_MODE_SEL 0x80
#define BF_MSC_DMAC_MODE_SEL(v) (((v) & 0x1) << 7)
#define BFM_MSC_DMAC_MODE_SEL(v) BM_MSC_DMAC_MODE_SEL
#define BF_MSC_DMAC_MODE_SEL_V(e) BF_MSC_DMAC_MODE_SEL(BV_MSC_DMAC_MODE_SEL__##e)
#define BFM_MSC_DMAC_MODE_SEL_V(v) BM_MSC_DMAC_MODE_SEL
#define BP_MSC_DMAC_ALIGN_EN 4
#define BM_MSC_DMAC_ALIGN_EN 0x10
#define BF_MSC_DMAC_ALIGN_EN(v) (((v) & 0x1) << 4)
#define BFM_MSC_DMAC_ALIGN_EN(v) BM_MSC_DMAC_ALIGN_EN
#define BF_MSC_DMAC_ALIGN_EN_V(e) BF_MSC_DMAC_ALIGN_EN(BV_MSC_DMAC_ALIGN_EN__##e)
#define BFM_MSC_DMAC_ALIGN_EN_V(v) BM_MSC_DMAC_ALIGN_EN
#define BP_MSC_DMAC_DMASEL 1
#define BM_MSC_DMAC_DMASEL 0x2
#define BF_MSC_DMAC_DMASEL(v) (((v) & 0x1) << 1)
#define BFM_MSC_DMAC_DMASEL(v) BM_MSC_DMAC_DMASEL
#define BF_MSC_DMAC_DMASEL_V(e) BF_MSC_DMAC_DMASEL(BV_MSC_DMAC_DMASEL__##e)
#define BFM_MSC_DMAC_DMASEL_V(v) BM_MSC_DMAC_DMASEL
#define BP_MSC_DMAC_ENABLE 0
#define BM_MSC_DMAC_ENABLE 0x1
#define BF_MSC_DMAC_ENABLE(v) (((v) & 0x1) << 0)
#define BFM_MSC_DMAC_ENABLE(v) BM_MSC_DMAC_ENABLE
#define BF_MSC_DMAC_ENABLE_V(e) BF_MSC_DMAC_ENABLE(BV_MSC_DMAC_ENABLE__##e)
#define BFM_MSC_DMAC_ENABLE_V(v) BM_MSC_DMAC_ENABLE
#define REG_MSC_CTRL2(_n1) jz_reg(MSC_CTRL2(_n1))
#define JA_MSC_CTRL2(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x58)
#define JT_MSC_CTRL2(_n1) JIO_32_RW
#define JN_MSC_CTRL2(_n1) MSC_CTRL2
#define JI_MSC_CTRL2(_n1) (_n1)
#define BP_MSC_CTRL2_PIN_INT_POLARITY 24
#define BM_MSC_CTRL2_PIN_INT_POLARITY 0x1f000000
#define BF_MSC_CTRL2_PIN_INT_POLARITY(v) (((v) & 0x1f) << 24)
#define BFM_MSC_CTRL2_PIN_INT_POLARITY(v) BM_MSC_CTRL2_PIN_INT_POLARITY
#define BF_MSC_CTRL2_PIN_INT_POLARITY_V(e) BF_MSC_CTRL2_PIN_INT_POLARITY(BV_MSC_CTRL2_PIN_INT_POLARITY__##e)
#define BFM_MSC_CTRL2_PIN_INT_POLARITY_V(v) BM_MSC_CTRL2_PIN_INT_POLARITY
#define BP_MSC_CTRL2_SPEED 0
#define BM_MSC_CTRL2_SPEED 0x7
#define BV_MSC_CTRL2_SPEED__DEFAULT 0x0
#define BV_MSC_CTRL2_SPEED__HIGHSPEED 0x1
#define BV_MSC_CTRL2_SPEED__SDR12 0x2
#define BV_MSC_CTRL2_SPEED__SDR25 0x3
#define BV_MSC_CTRL2_SPEED__SDR50 0x4
#define BF_MSC_CTRL2_SPEED(v) (((v) & 0x7) << 0)
#define BFM_MSC_CTRL2_SPEED(v) BM_MSC_CTRL2_SPEED
#define BF_MSC_CTRL2_SPEED_V(e) BF_MSC_CTRL2_SPEED(BV_MSC_CTRL2_SPEED__##e)
#define BFM_MSC_CTRL2_SPEED_V(v) BM_MSC_CTRL2_SPEED
#define BP_MSC_CTRL2_STPRM 4
#define BM_MSC_CTRL2_STPRM 0x10
#define BF_MSC_CTRL2_STPRM(v) (((v) & 0x1) << 4)
#define BFM_MSC_CTRL2_STPRM(v) BM_MSC_CTRL2_STPRM
#define BF_MSC_CTRL2_STPRM_V(e) BF_MSC_CTRL2_STPRM(BV_MSC_CTRL2_STPRM__##e)
#define BFM_MSC_CTRL2_STPRM_V(v) BM_MSC_CTRL2_STPRM
#define REG_MSC_CLKRT(_n1) jz_reg(MSC_CLKRT(_n1))
#define JA_MSC_CLKRT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x8)
#define JT_MSC_CLKRT(_n1) JIO_32_RW
#define JN_MSC_CLKRT(_n1) MSC_CLKRT
#define JI_MSC_CLKRT(_n1) (_n1)
#define REG_MSC_RESTO(_n1) jz_reg(MSC_RESTO(_n1))
#define JA_MSC_RESTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x10)
#define JT_MSC_RESTO(_n1) JIO_32_RW
#define JN_MSC_RESTO(_n1) MSC_RESTO
#define JI_MSC_RESTO(_n1) (_n1)
#define REG_MSC_RDTO(_n1) jz_reg(MSC_RDTO(_n1))
#define JA_MSC_RDTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x14)
#define JT_MSC_RDTO(_n1) JIO_32_RW
#define JN_MSC_RDTO(_n1) MSC_RDTO
#define JI_MSC_RDTO(_n1) (_n1)
#define REG_MSC_BLKLEN(_n1) jz_reg(MSC_BLKLEN(_n1))
#define JA_MSC_BLKLEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x18)
#define JT_MSC_BLKLEN(_n1) JIO_32_RW
#define JN_MSC_BLKLEN(_n1) MSC_BLKLEN
#define JI_MSC_BLKLEN(_n1) (_n1)
#define REG_MSC_NOB(_n1) jz_reg(MSC_NOB(_n1))
#define JA_MSC_NOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x1c)
#define JT_MSC_NOB(_n1) JIO_32_RW
#define JN_MSC_NOB(_n1) MSC_NOB
#define JI_MSC_NOB(_n1) (_n1)
#define REG_MSC_SNOB(_n1) jz_reg(MSC_SNOB(_n1))
#define JA_MSC_SNOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x20)
#define JT_MSC_SNOB(_n1) JIO_32_RW
#define JN_MSC_SNOB(_n1) MSC_SNOB
#define JI_MSC_SNOB(_n1) (_n1)
#define REG_MSC_CMD(_n1) jz_reg(MSC_CMD(_n1))
#define JA_MSC_CMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x2c)
#define JT_MSC_CMD(_n1) JIO_32_RW
#define JN_MSC_CMD(_n1) MSC_CMD
#define JI_MSC_CMD(_n1) (_n1)
#define REG_MSC_ARG(_n1) jz_reg(MSC_ARG(_n1))
#define JA_MSC_ARG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x30)
#define JT_MSC_ARG(_n1) JIO_32_RW
#define JN_MSC_ARG(_n1) MSC_ARG
#define JI_MSC_ARG(_n1) (_n1)
#define REG_MSC_RES(_n1) jz_reg(MSC_RES(_n1))
#define JA_MSC_RES(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x34)
#define JT_MSC_RES(_n1) JIO_32_RW
#define JN_MSC_RES(_n1) MSC_RES
#define JI_MSC_RES(_n1) (_n1)
#define REG_MSC_RXFIFO(_n1) jz_reg(MSC_RXFIFO(_n1))
#define JA_MSC_RXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x38)
#define JT_MSC_RXFIFO(_n1) JIO_32_RW
#define JN_MSC_RXFIFO(_n1) MSC_RXFIFO
#define JI_MSC_RXFIFO(_n1) (_n1)
#define REG_MSC_TXFIFO(_n1) jz_reg(MSC_TXFIFO(_n1))
#define JA_MSC_TXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x3c)
#define JT_MSC_TXFIFO(_n1) JIO_32_RW
#define JN_MSC_TXFIFO(_n1) MSC_TXFIFO
#define JI_MSC_TXFIFO(_n1) (_n1)
#define REG_MSC_DMANDA(_n1) jz_reg(MSC_DMANDA(_n1))
#define JA_MSC_DMANDA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x48)
#define JT_MSC_DMANDA(_n1) JIO_32_RW
#define JN_MSC_DMANDA(_n1) MSC_DMANDA
#define JI_MSC_DMANDA(_n1) (_n1)
#define REG_MSC_DMADA(_n1) jz_reg(MSC_DMADA(_n1))
#define JA_MSC_DMADA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4c)
#define JT_MSC_DMADA(_n1) JIO_32_RW
#define JN_MSC_DMADA(_n1) MSC_DMADA
#define JI_MSC_DMADA(_n1) (_n1)
#define REG_MSC_DMALEN(_n1) jz_reg(MSC_DMALEN(_n1))
#define JA_MSC_DMALEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x50)
#define JT_MSC_DMALEN(_n1) JIO_32_RW
#define JN_MSC_DMALEN(_n1) MSC_DMALEN
#define JI_MSC_DMALEN(_n1) (_n1)
#define REG_MSC_DMACMD(_n1) jz_reg(MSC_DMACMD(_n1))
#define JA_MSC_DMACMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x54)
#define JT_MSC_DMACMD(_n1) JIO_32_RW
#define JN_MSC_DMACMD(_n1) MSC_DMACMD
#define JI_MSC_DMACMD(_n1) (_n1)
#define REG_MSC_RTCNT(_n1) jz_reg(MSC_RTCNT(_n1))
#define JA_MSC_RTCNT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x5c)
#define JT_MSC_RTCNT(_n1) JIO_32_RW
#define JN_MSC_RTCNT(_n1) MSC_RTCNT
#define JI_MSC_RTCNT(_n1) (_n1)
#endif /* __HEADERGEN_MSC_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_OST_H__
#define __HEADERGEN_OST_H__
#include "macro.h"
#define REG_OST_CTRL jz_reg(OST_CTRL)
#define JA_OST_CTRL (0xb2000000 + 0x0)
#define JT_OST_CTRL JIO_32_RW
#define JN_OST_CTRL OST_CTRL
#define JI_OST_CTRL
#define BP_OST_CTRL_PRESCALE2 3
#define BM_OST_CTRL_PRESCALE2 0x38
#define BV_OST_CTRL_PRESCALE2__BY_1 0x0
#define BV_OST_CTRL_PRESCALE2__BY_4 0x1
#define BV_OST_CTRL_PRESCALE2__BY_16 0x2
#define BF_OST_CTRL_PRESCALE2(v) (((v) & 0x7) << 3)
#define BFM_OST_CTRL_PRESCALE2(v) BM_OST_CTRL_PRESCALE2
#define BF_OST_CTRL_PRESCALE2_V(e) BF_OST_CTRL_PRESCALE2(BV_OST_CTRL_PRESCALE2__##e)
#define BFM_OST_CTRL_PRESCALE2_V(v) BM_OST_CTRL_PRESCALE2
#define BP_OST_CTRL_PRESCALE1 0
#define BM_OST_CTRL_PRESCALE1 0x7
#define BV_OST_CTRL_PRESCALE1__BY_1 0x0
#define BV_OST_CTRL_PRESCALE1__BY_4 0x1
#define BV_OST_CTRL_PRESCALE1__BY_16 0x2
#define BF_OST_CTRL_PRESCALE1(v) (((v) & 0x7) << 0)
#define BFM_OST_CTRL_PRESCALE1(v) BM_OST_CTRL_PRESCALE1
#define BF_OST_CTRL_PRESCALE1_V(e) BF_OST_CTRL_PRESCALE1(BV_OST_CTRL_PRESCALE1__##e)
#define BFM_OST_CTRL_PRESCALE1_V(v) BM_OST_CTRL_PRESCALE1
#define REG_OST_ENABLE jz_reg(OST_ENABLE)
#define JA_OST_ENABLE (0xb2000000 + 0x4)
#define JT_OST_ENABLE JIO_32_RW
#define JN_OST_ENABLE OST_ENABLE
#define JI_OST_ENABLE
#define REG_OST_ENABLE_SET jz_reg(OST_ENABLE_SET)
#define JA_OST_ENABLE_SET (JA_OST_ENABLE + 0x30)
#define JT_OST_ENABLE_SET JIO_32_WO
#define JN_OST_ENABLE_SET OST_ENABLE
#define JI_OST_ENABLE_SET
#define REG_OST_ENABLE_CLR jz_reg(OST_ENABLE_CLR)
#define JA_OST_ENABLE_CLR (JA_OST_ENABLE + 0x34)
#define JT_OST_ENABLE_CLR JIO_32_WO
#define JN_OST_ENABLE_CLR OST_ENABLE
#define JI_OST_ENABLE_CLR
#define BP_OST_ENABLE_OST1 0
#define BM_OST_ENABLE_OST1 0x1
#define BF_OST_ENABLE_OST1(v) (((v) & 0x1) << 0)
#define BFM_OST_ENABLE_OST1(v) BM_OST_ENABLE_OST1
#define BF_OST_ENABLE_OST1_V(e) BF_OST_ENABLE_OST1(BV_OST_ENABLE_OST1__##e)
#define BFM_OST_ENABLE_OST1_V(v) BM_OST_ENABLE_OST1
#define BP_OST_ENABLE_OST2 1
#define BM_OST_ENABLE_OST2 0x2
#define BF_OST_ENABLE_OST2(v) (((v) & 0x1) << 1)
#define BFM_OST_ENABLE_OST2(v) BM_OST_ENABLE_OST2
#define BF_OST_ENABLE_OST2_V(e) BF_OST_ENABLE_OST2(BV_OST_ENABLE_OST2__##e)
#define BFM_OST_ENABLE_OST2_V(v) BM_OST_ENABLE_OST2
#define REG_OST_CLEAR jz_reg(OST_CLEAR)
#define JA_OST_CLEAR (0xb2000000 + 0x8)
#define JT_OST_CLEAR JIO_32_RW
#define JN_OST_CLEAR OST_CLEAR
#define JI_OST_CLEAR
#define BP_OST_CLEAR_OST1 0
#define BM_OST_CLEAR_OST1 0x1
#define BF_OST_CLEAR_OST1(v) (((v) & 0x1) << 0)
#define BFM_OST_CLEAR_OST1(v) BM_OST_CLEAR_OST1
#define BF_OST_CLEAR_OST1_V(e) BF_OST_CLEAR_OST1(BV_OST_CLEAR_OST1__##e)
#define BFM_OST_CLEAR_OST1_V(v) BM_OST_CLEAR_OST1
#define BP_OST_CLEAR_OST2 1
#define BM_OST_CLEAR_OST2 0x2
#define BF_OST_CLEAR_OST2(v) (((v) & 0x1) << 1)
#define BFM_OST_CLEAR_OST2(v) BM_OST_CLEAR_OST2
#define BF_OST_CLEAR_OST2_V(e) BF_OST_CLEAR_OST2(BV_OST_CLEAR_OST2__##e)
#define BFM_OST_CLEAR_OST2_V(v) BM_OST_CLEAR_OST2
#define REG_OST_1FLG jz_reg(OST_1FLG)
#define JA_OST_1FLG (0xb2000000 + 0xc)
#define JT_OST_1FLG JIO_32_RW
#define JN_OST_1FLG OST_1FLG
#define JI_OST_1FLG
#define REG_OST_1MSK jz_reg(OST_1MSK)
#define JA_OST_1MSK (0xb2000000 + 0x10)
#define JT_OST_1MSK JIO_32_RW
#define JN_OST_1MSK OST_1MSK
#define JI_OST_1MSK
#define REG_OST_1DFR jz_reg(OST_1DFR)
#define JA_OST_1DFR (0xb2000000 + 0x14)
#define JT_OST_1DFR JIO_32_RW
#define JN_OST_1DFR OST_1DFR
#define JI_OST_1DFR
#define REG_OST_1CNT jz_reg(OST_1CNT)
#define JA_OST_1CNT (0xb2000000 + 0x18)
#define JT_OST_1CNT JIO_32_RW
#define JN_OST_1CNT OST_1CNT
#define JI_OST_1CNT
#define REG_OST_2CNTH jz_reg(OST_2CNTH)
#define JA_OST_2CNTH (0xb2000000 + 0x1c)
#define JT_OST_2CNTH JIO_32_RW
#define JN_OST_2CNTH OST_2CNTH
#define JI_OST_2CNTH
#define REG_OST_2CNTL jz_reg(OST_2CNTL)
#define JA_OST_2CNTL (0xb2000000 + 0x20)
#define JT_OST_2CNTL JIO_32_RW
#define JN_OST_2CNTL OST_2CNTL
#define JI_OST_2CNTL
#define REG_OST_2CNTHB jz_reg(OST_2CNTHB)
#define JA_OST_2CNTHB (0xb2000000 + 0x24)
#define JT_OST_2CNTHB JIO_32_RW
#define JN_OST_2CNTHB OST_2CNTHB
#define JI_OST_2CNTHB
#endif /* __HEADERGEN_OST_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_RTC_H__
#define __HEADERGEN_RTC_H__
#include "macro.h"
#define REG_RTC_CR jz_reg(RTC_CR)
#define JA_RTC_CR (0xb0003000 + 0x0)
#define JT_RTC_CR JIO_32_RW
#define JN_RTC_CR RTC_CR
#define JI_RTC_CR
#define BP_RTC_CR_WRDY 7
#define BM_RTC_CR_WRDY 0x80
#define BF_RTC_CR_WRDY(v) (((v) & 0x1) << 7)
#define BFM_RTC_CR_WRDY(v) BM_RTC_CR_WRDY
#define BF_RTC_CR_WRDY_V(e) BF_RTC_CR_WRDY(BV_RTC_CR_WRDY__##e)
#define BFM_RTC_CR_WRDY_V(v) BM_RTC_CR_WRDY
#define BP_RTC_CR_1HZ 6
#define BM_RTC_CR_1HZ 0x40
#define BF_RTC_CR_1HZ(v) (((v) & 0x1) << 6)
#define BFM_RTC_CR_1HZ(v) BM_RTC_CR_1HZ
#define BF_RTC_CR_1HZ_V(e) BF_RTC_CR_1HZ(BV_RTC_CR_1HZ__##e)
#define BFM_RTC_CR_1HZ_V(v) BM_RTC_CR_1HZ
#define BP_RTC_CR_1HZIE 5
#define BM_RTC_CR_1HZIE 0x20
#define BF_RTC_CR_1HZIE(v) (((v) & 0x1) << 5)
#define BFM_RTC_CR_1HZIE(v) BM_RTC_CR_1HZIE
#define BF_RTC_CR_1HZIE_V(e) BF_RTC_CR_1HZIE(BV_RTC_CR_1HZIE__##e)
#define BFM_RTC_CR_1HZIE_V(v) BM_RTC_CR_1HZIE
#define BP_RTC_CR_AF 4
#define BM_RTC_CR_AF 0x10
#define BF_RTC_CR_AF(v) (((v) & 0x1) << 4)
#define BFM_RTC_CR_AF(v) BM_RTC_CR_AF
#define BF_RTC_CR_AF_V(e) BF_RTC_CR_AF(BV_RTC_CR_AF__##e)
#define BFM_RTC_CR_AF_V(v) BM_RTC_CR_AF
#define BP_RTC_CR_AIE 3
#define BM_RTC_CR_AIE 0x8
#define BF_RTC_CR_AIE(v) (((v) & 0x1) << 3)
#define BFM_RTC_CR_AIE(v) BM_RTC_CR_AIE
#define BF_RTC_CR_AIE_V(e) BF_RTC_CR_AIE(BV_RTC_CR_AIE__##e)
#define BFM_RTC_CR_AIE_V(v) BM_RTC_CR_AIE
#define BP_RTC_CR_AE 2
#define BM_RTC_CR_AE 0x4
#define BF_RTC_CR_AE(v) (((v) & 0x1) << 2)
#define BFM_RTC_CR_AE(v) BM_RTC_CR_AE
#define BF_RTC_CR_AE_V(e) BF_RTC_CR_AE(BV_RTC_CR_AE__##e)
#define BFM_RTC_CR_AE_V(v) BM_RTC_CR_AE
#define BP_RTC_CR_SELEXC 1
#define BM_RTC_CR_SELEXC 0x2
#define BF_RTC_CR_SELEXC(v) (((v) & 0x1) << 1)
#define BFM_RTC_CR_SELEXC(v) BM_RTC_CR_SELEXC
#define BF_RTC_CR_SELEXC_V(e) BF_RTC_CR_SELEXC(BV_RTC_CR_SELEXC__##e)
#define BFM_RTC_CR_SELEXC_V(v) BM_RTC_CR_SELEXC
#define BP_RTC_CR_ENABLE 0
#define BM_RTC_CR_ENABLE 0x1
#define BF_RTC_CR_ENABLE(v) (((v) & 0x1) << 0)
#define BFM_RTC_CR_ENABLE(v) BM_RTC_CR_ENABLE
#define BF_RTC_CR_ENABLE_V(e) BF_RTC_CR_ENABLE(BV_RTC_CR_ENABLE__##e)
#define BFM_RTC_CR_ENABLE_V(v) BM_RTC_CR_ENABLE
#define REG_RTC_SR jz_reg(RTC_SR)
#define JA_RTC_SR (0xb0003000 + 0x4)
#define JT_RTC_SR JIO_32_RW
#define JN_RTC_SR RTC_SR
#define JI_RTC_SR
#define REG_RTC_SAR jz_reg(RTC_SAR)
#define JA_RTC_SAR (0xb0003000 + 0x8)
#define JT_RTC_SAR JIO_32_RW
#define JN_RTC_SAR RTC_SAR
#define JI_RTC_SAR
#define REG_RTC_GR jz_reg(RTC_GR)
#define JA_RTC_GR (0xb0003000 + 0xc)
#define JT_RTC_GR JIO_32_RW
#define JN_RTC_GR RTC_GR
#define JI_RTC_GR
#define BP_RTC_GR_ADJC 16
#define BM_RTC_GR_ADJC 0x3ff0000
#define BF_RTC_GR_ADJC(v) (((v) & 0x3ff) << 16)
#define BFM_RTC_GR_ADJC(v) BM_RTC_GR_ADJC
#define BF_RTC_GR_ADJC_V(e) BF_RTC_GR_ADJC(BV_RTC_GR_ADJC__##e)
#define BFM_RTC_GR_ADJC_V(v) BM_RTC_GR_ADJC
#define BP_RTC_GR_NC1HZ 0
#define BM_RTC_GR_NC1HZ 0xffff
#define BF_RTC_GR_NC1HZ(v) (((v) & 0xffff) << 0)
#define BFM_RTC_GR_NC1HZ(v) BM_RTC_GR_NC1HZ
#define BF_RTC_GR_NC1HZ_V(e) BF_RTC_GR_NC1HZ(BV_RTC_GR_NC1HZ__##e)
#define BFM_RTC_GR_NC1HZ_V(v) BM_RTC_GR_NC1HZ
#define BP_RTC_GR_LOCK 31
#define BM_RTC_GR_LOCK 0x80000000
#define BF_RTC_GR_LOCK(v) (((v) & 0x1) << 31)
#define BFM_RTC_GR_LOCK(v) BM_RTC_GR_LOCK
#define BF_RTC_GR_LOCK_V(e) BF_RTC_GR_LOCK(BV_RTC_GR_LOCK__##e)
#define BFM_RTC_GR_LOCK_V(v) BM_RTC_GR_LOCK
#define REG_RTC_HCR jz_reg(RTC_HCR)
#define JA_RTC_HCR (0xb0003000 + 0x20)
#define JT_RTC_HCR JIO_32_RW
#define JN_RTC_HCR RTC_HCR
#define JI_RTC_HCR
#define REG_RTC_HWFCR jz_reg(RTC_HWFCR)
#define JA_RTC_HWFCR (0xb0003000 + 0x24)
#define JT_RTC_HWFCR JIO_32_RW
#define JN_RTC_HWFCR RTC_HWFCR
#define JI_RTC_HWFCR
#define REG_RTC_HRCR jz_reg(RTC_HRCR)
#define JA_RTC_HRCR (0xb0003000 + 0x28)
#define JT_RTC_HRCR JIO_32_RW
#define JN_RTC_HRCR RTC_HRCR
#define JI_RTC_HRCR
#define REG_RTC_HWCR jz_reg(RTC_HWCR)
#define JA_RTC_HWCR (0xb0003000 + 0x2c)
#define JT_RTC_HWCR JIO_32_RW
#define JN_RTC_HWCR RTC_HWCR
#define JI_RTC_HWCR
#define BP_RTC_HWCR_EPDET 3
#define BM_RTC_HWCR_EPDET 0xfffffff8
#define BF_RTC_HWCR_EPDET(v) (((v) & 0x1fffffff) << 3)
#define BFM_RTC_HWCR_EPDET(v) BM_RTC_HWCR_EPDET
#define BF_RTC_HWCR_EPDET_V(e) BF_RTC_HWCR_EPDET(BV_RTC_HWCR_EPDET__##e)
#define BFM_RTC_HWCR_EPDET_V(v) BM_RTC_HWCR_EPDET
#define BP_RTC_HWCR_EALM 1
#define BM_RTC_HWCR_EALM 0x2
#define BF_RTC_HWCR_EALM(v) (((v) & 0x1) << 1)
#define BFM_RTC_HWCR_EALM(v) BM_RTC_HWCR_EALM
#define BF_RTC_HWCR_EALM_V(e) BF_RTC_HWCR_EALM(BV_RTC_HWCR_EALM__##e)
#define BFM_RTC_HWCR_EALM_V(v) BM_RTC_HWCR_EALM
#define REG_RTC_HWRSR jz_reg(RTC_HWRSR)
#define JA_RTC_HWRSR (0xb0003000 + 0x30)
#define JT_RTC_HWRSR JIO_32_RW
#define JN_RTC_HWRSR RTC_HWRSR
#define JI_RTC_HWRSR
#define BP_RTC_HWRSR_APD 8
#define BM_RTC_HWRSR_APD 0x100
#define BF_RTC_HWRSR_APD(v) (((v) & 0x1) << 8)
#define BFM_RTC_HWRSR_APD(v) BM_RTC_HWRSR_APD
#define BF_RTC_HWRSR_APD_V(e) BF_RTC_HWRSR_APD(BV_RTC_HWRSR_APD__##e)
#define BFM_RTC_HWRSR_APD_V(v) BM_RTC_HWRSR_APD
#define BP_RTC_HWRSR_HR 5
#define BM_RTC_HWRSR_HR 0x20
#define BF_RTC_HWRSR_HR(v) (((v) & 0x1) << 5)
#define BFM_RTC_HWRSR_HR(v) BM_RTC_HWRSR_HR
#define BF_RTC_HWRSR_HR_V(e) BF_RTC_HWRSR_HR(BV_RTC_HWRSR_HR__##e)
#define BFM_RTC_HWRSR_HR_V(v) BM_RTC_HWRSR_HR
#define BP_RTC_HWRSR_PPR 4
#define BM_RTC_HWRSR_PPR 0x10
#define BF_RTC_HWRSR_PPR(v) (((v) & 0x1) << 4)
#define BFM_RTC_HWRSR_PPR(v) BM_RTC_HWRSR_PPR
#define BF_RTC_HWRSR_PPR_V(e) BF_RTC_HWRSR_PPR(BV_RTC_HWRSR_PPR__##e)
#define BFM_RTC_HWRSR_PPR_V(v) BM_RTC_HWRSR_PPR
#define BP_RTC_HWRSR_PIN 1
#define BM_RTC_HWRSR_PIN 0x2
#define BF_RTC_HWRSR_PIN(v) (((v) & 0x1) << 1)
#define BFM_RTC_HWRSR_PIN(v) BM_RTC_HWRSR_PIN
#define BF_RTC_HWRSR_PIN_V(e) BF_RTC_HWRSR_PIN(BV_RTC_HWRSR_PIN__##e)
#define BFM_RTC_HWRSR_PIN_V(v) BM_RTC_HWRSR_PIN
#define BP_RTC_HWRSR_ALM 0
#define BM_RTC_HWRSR_ALM 0x1
#define BF_RTC_HWRSR_ALM(v) (((v) & 0x1) << 0)
#define BFM_RTC_HWRSR_ALM(v) BM_RTC_HWRSR_ALM
#define BF_RTC_HWRSR_ALM_V(e) BF_RTC_HWRSR_ALM(BV_RTC_HWRSR_ALM__##e)
#define BFM_RTC_HWRSR_ALM_V(v) BM_RTC_HWRSR_ALM
#define REG_RTC_HSPR jz_reg(RTC_HSPR)
#define JA_RTC_HSPR (0xb0003000 + 0x34)
#define JT_RTC_HSPR JIO_32_RW
#define JN_RTC_HSPR RTC_HSPR
#define JI_RTC_HSPR
#define REG_RTC_WENR jz_reg(RTC_WENR)
#define JA_RTC_WENR (0xb0003000 + 0x3c)
#define JT_RTC_WENR JIO_32_RW
#define JN_RTC_WENR RTC_WENR
#define JI_RTC_WENR
#define BP_RTC_WENR_WEN 31
#define BM_RTC_WENR_WEN 0x80000000
#define BF_RTC_WENR_WEN(v) (((v) & 0x1) << 31)
#define BFM_RTC_WENR_WEN(v) BM_RTC_WENR_WEN
#define BF_RTC_WENR_WEN_V(e) BF_RTC_WENR_WEN(BV_RTC_WENR_WEN__##e)
#define BFM_RTC_WENR_WEN_V(v) BM_RTC_WENR_WEN
#define BP_RTC_WENR_WENPAT 0
#define BM_RTC_WENR_WENPAT 0xffff
#define BF_RTC_WENR_WENPAT(v) (((v) & 0xffff) << 0)
#define BFM_RTC_WENR_WENPAT(v) BM_RTC_WENR_WENPAT
#define BF_RTC_WENR_WENPAT_V(e) BF_RTC_WENR_WENPAT(BV_RTC_WENR_WENPAT__##e)
#define BFM_RTC_WENR_WENPAT_V(v) BM_RTC_WENR_WENPAT
#define REG_RTC_WKUPPINCR jz_reg(RTC_WKUPPINCR)
#define JA_RTC_WKUPPINCR (0xb0003000 + 0x48)
#define JT_RTC_WKUPPINCR JIO_32_RW
#define JN_RTC_WKUPPINCR RTC_WKUPPINCR
#define JI_RTC_WKUPPINCR
#endif /* __HEADERGEN_RTC_H__*/

481
firmware/target/mips/ingenic_x1000/x1000/sfc.h Normal file
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@ -0,0 +1,481 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_SFC_H__
#define __HEADERGEN_SFC_H__
#include "macro.h"
#define REG_SFC_GLB jz_reg(SFC_GLB)
#define JA_SFC_GLB (0xb3440000 + 0x0)
#define JT_SFC_GLB JIO_32_RW
#define JN_SFC_GLB SFC_GLB
#define JI_SFC_GLB
#define BP_SFC_GLB_THRESHOLD 7
#define BM_SFC_GLB_THRESHOLD 0x1f80
#define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7)
#define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD
#define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e)
#define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD
#define BP_SFC_GLB_PHASE_NUM 3
#define BM_SFC_GLB_PHASE_NUM 0x38
#define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3)
#define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM
#define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e)
#define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM
#define BP_SFC_GLB_TRAN_DIR 13
#define BM_SFC_GLB_TRAN_DIR 0x2000
#define BV_SFC_GLB_TRAN_DIR__READ 0x0
#define BV_SFC_GLB_TRAN_DIR__WRITE 0x1
#define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13)
#define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR
#define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e)
#define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR
#define BP_SFC_GLB_OP_MODE 6
#define BM_SFC_GLB_OP_MODE 0x40
#define BV_SFC_GLB_OP_MODE__SLAVE 0x0
#define BV_SFC_GLB_OP_MODE__DMA 0x1
#define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6)
#define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE
#define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e)
#define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE
#define BP_SFC_GLB_WP_EN 2
#define BM_SFC_GLB_WP_EN 0x4
#define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2)
#define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN
#define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e)
#define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN
#define BP_SFC_GLB_BURST_MD 0
#define BM_SFC_GLB_BURST_MD 0x3
#define BV_SFC_GLB_BURST_MD__INCR4 0x0
#define BV_SFC_GLB_BURST_MD__INCR8 0x1
#define BV_SFC_GLB_BURST_MD__INCR16 0x2
#define BV_SFC_GLB_BURST_MD__INCR32 0x3
#define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0)
#define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD
#define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e)
#define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD
#define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF)
#define JA_SFC_DEV_CONF (0xb3440000 + 0x4)
#define JT_SFC_DEV_CONF JIO_32_RW
#define JN_SFC_DEV_CONF SFC_DEV_CONF
#define JI_SFC_DEV_CONF
#define BP_SFC_DEV_CONF_SMP_DELAY 16
#define BM_SFC_DEV_CONF_SMP_DELAY 0x30000
#define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16)
#define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY
#define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e)
#define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY
#define BP_SFC_DEV_CONF_STA_TYPE 13
#define BM_SFC_DEV_CONF_STA_TYPE 0x6000
#define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0
#define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1
#define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2
#define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3
#define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13)
#define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE
#define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e)
#define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE
#define BP_SFC_DEV_CONF_THOLD 11
#define BM_SFC_DEV_CONF_THOLD 0x1800
#define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11)
#define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD
#define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e)
#define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD
#define BP_SFC_DEV_CONF_TSETUP 9
#define BM_SFC_DEV_CONF_TSETUP 0x600
#define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9)
#define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP
#define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e)
#define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP
#define BP_SFC_DEV_CONF_TSH 5
#define BM_SFC_DEV_CONF_TSH 0x1e0
#define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5)
#define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH
#define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e)
#define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH
#define BP_SFC_DEV_CONF_CMD_TYPE 15
#define BM_SFC_DEV_CONF_CMD_TYPE 0x8000
#define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0
#define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1
#define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15)
#define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE
#define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e)
#define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE
#define BP_SFC_DEV_CONF_CPHA 4
#define BM_SFC_DEV_CONF_CPHA 0x10
#define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4)
#define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA
#define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e)
#define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA
#define BP_SFC_DEV_CONF_CPOL 3
#define BM_SFC_DEV_CONF_CPOL 0x8
#define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3)
#define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL
#define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e)
#define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL
#define BP_SFC_DEV_CONF_CE_DL 2
#define BM_SFC_DEV_CONF_CE_DL 0x4
#define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2)
#define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL
#define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e)
#define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL
#define BP_SFC_DEV_CONF_HOLD_DL 1
#define BM_SFC_DEV_CONF_HOLD_DL 0x2
#define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1)
#define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL
#define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e)
#define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL
#define BP_SFC_DEV_CONF_WP_DL 0
#define BM_SFC_DEV_CONF_WP_DL 0x1
#define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0)
#define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL
#define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e)
#define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL
#define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP)
#define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8)
#define JT_SFC_DEV_STA_EXP JIO_32_RW
#define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP
#define JI_SFC_DEV_STA_EXP
#define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT)
#define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc)
#define JT_SFC_DEV_STA_RT JIO_32_RW
#define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT
#define JI_SFC_DEV_STA_RT
#define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK)
#define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10)
#define JT_SFC_DEV_STA_MSK JIO_32_RW
#define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK
#define JI_SFC_DEV_STA_MSK
#define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1))
#define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4)
#define JT_SFC_TRAN_CONF(_n1) JIO_32_RW
#define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF
#define JI_SFC_TRAN_CONF(_n1) (_n1)
#define BP_SFC_TRAN_CONF_MODE 29
#define BM_SFC_TRAN_CONF_MODE 0xe0000000
#define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29)
#define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE
#define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e)
#define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE
#define BP_SFC_TRAN_CONF_ADDR_WIDTH 26
#define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000
#define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26)
#define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH
#define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e)
#define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH
#define BP_SFC_TRAN_CONF_DUMMY_BITS 17
#define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000
#define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17)
#define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS
#define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e)
#define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS
#define BP_SFC_TRAN_CONF_COMMAND 0
#define BM_SFC_TRAN_CONF_COMMAND 0xffff
#define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0)
#define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND
#define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e)
#define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND
#define BP_SFC_TRAN_CONF_POLL_EN 25
#define BM_SFC_TRAN_CONF_POLL_EN 0x2000000
#define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25)
#define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN
#define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e)
#define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN
#define BP_SFC_TRAN_CONF_CMD_EN 24
#define BM_SFC_TRAN_CONF_CMD_EN 0x1000000
#define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24)
#define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN
#define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e)
#define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN
#define BP_SFC_TRAN_CONF_PHASE_FMT 23
#define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000
#define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23)
#define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT
#define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e)
#define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT
#define BP_SFC_TRAN_CONF_DATA_EN 16
#define BM_SFC_TRAN_CONF_DATA_EN 0x10000
#define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16)
#define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN
#define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e)
#define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN
#define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH)
#define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c)
#define JT_SFC_TRAN_LENGTH JIO_32_RW
#define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH
#define JI_SFC_TRAN_LENGTH
#define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1))
#define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4)
#define JT_SFC_DEV_ADDR(_n1) JIO_32_RW
#define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR
#define JI_SFC_DEV_ADDR(_n1) (_n1)
#define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1))
#define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40)
#define JT_SFC_DEV_PLUS(_n1) JIO_32_RW
#define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS
#define JI_SFC_DEV_PLUS(_n1) (_n1)
#define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR)
#define JA_SFC_MEM_ADDR (0xb3440000 + 0x60)
#define JT_SFC_MEM_ADDR JIO_32_RW
#define JN_SFC_MEM_ADDR SFC_MEM_ADDR
#define JI_SFC_MEM_ADDR
#define REG_SFC_TRIG jz_reg(SFC_TRIG)
#define JA_SFC_TRIG (0xb3440000 + 0x64)
#define JT_SFC_TRIG JIO_32_RW
#define JN_SFC_TRIG SFC_TRIG
#define JI_SFC_TRIG
#define BP_SFC_TRIG_FLUSH 2
#define BM_SFC_TRIG_FLUSH 0x4
#define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2)
#define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH
#define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e)
#define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH
#define BP_SFC_TRIG_STOP 1
#define BM_SFC_TRIG_STOP 0x2
#define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1)
#define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP
#define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e)
#define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP
#define BP_SFC_TRIG_START 0
#define BM_SFC_TRIG_START 0x1
#define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0)
#define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START
#define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e)
#define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START
#define REG_SFC_SR jz_reg(SFC_SR)
#define JA_SFC_SR (0xb3440000 + 0x68)
#define JT_SFC_SR JIO_32_RW
#define JN_SFC_SR SFC_SR
#define JI_SFC_SR
#define BP_SFC_SR_FIFO_NUM 16
#define BM_SFC_SR_FIFO_NUM 0x7f0000
#define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16)
#define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM
#define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e)
#define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM
#define BP_SFC_SR_BUSY 5
#define BM_SFC_SR_BUSY 0x60
#define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5)
#define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY
#define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e)
#define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY
#define BP_SFC_SR_END 4
#define BM_SFC_SR_END 0x10
#define BF_SFC_SR_END(v) (((v) & 0x1) << 4)
#define BFM_SFC_SR_END(v) BM_SFC_SR_END
#define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e)
#define BFM_SFC_SR_END_V(v) BM_SFC_SR_END
#define BP_SFC_SR_TREQ 3
#define BM_SFC_SR_TREQ 0x8
#define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3)
#define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ
#define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e)
#define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ
#define BP_SFC_SR_RREQ 2
#define BM_SFC_SR_RREQ 0x4
#define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2)
#define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ
#define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e)
#define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ
#define BP_SFC_SR_OVER 1
#define BM_SFC_SR_OVER 0x2
#define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1)
#define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER
#define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e)
#define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER
#define BP_SFC_SR_UNDER 0
#define BM_SFC_SR_UNDER 0x1
#define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0)
#define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER
#define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e)
#define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER
#define REG_SFC_SCR jz_reg(SFC_SCR)
#define JA_SFC_SCR (0xb3440000 + 0x6c)
#define JT_SFC_SCR JIO_32_RW
#define JN_SFC_SCR SFC_SCR
#define JI_SFC_SCR
#define BP_SFC_SCR_CLR_END 4
#define BM_SFC_SCR_CLR_END 0x10
#define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4)
#define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END
#define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e)
#define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END
#define BP_SFC_SCR_CLR_TREQ 3
#define BM_SFC_SCR_CLR_TREQ 0x8
#define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3)
#define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ
#define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e)
#define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ
#define BP_SFC_SCR_CLR_RREQ 2
#define BM_SFC_SCR_CLR_RREQ 0x4
#define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2)
#define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ
#define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e)
#define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ
#define BP_SFC_SCR_CLR_OVER 1
#define BM_SFC_SCR_CLR_OVER 0x2
#define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1)
#define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER
#define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e)
#define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER
#define BP_SFC_SCR_CLR_UNDER 0
#define BM_SFC_SCR_CLR_UNDER 0x1
#define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0)
#define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER
#define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e)
#define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER
#define REG_SFC_INTC jz_reg(SFC_INTC)
#define JA_SFC_INTC (0xb3440000 + 0x70)
#define JT_SFC_INTC JIO_32_RW
#define JN_SFC_INTC SFC_INTC
#define JI_SFC_INTC
#define BP_SFC_INTC_MSK_END 4
#define BM_SFC_INTC_MSK_END 0x10
#define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4)
#define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END
#define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e)
#define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END
#define BP_SFC_INTC_MSK_TREQ 3
#define BM_SFC_INTC_MSK_TREQ 0x8
#define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3)
#define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ
#define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e)
#define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ
#define BP_SFC_INTC_MSK_RREQ 2
#define BM_SFC_INTC_MSK_RREQ 0x4
#define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2)
#define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ
#define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e)
#define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ
#define BP_SFC_INTC_MSK_OVER 1
#define BM_SFC_INTC_MSK_OVER 0x2
#define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1)
#define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER
#define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e)
#define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER
#define BP_SFC_INTC_MSK_UNDER 0
#define BM_SFC_INTC_MSK_UNDER 0x1
#define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0)
#define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER
#define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e)
#define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER
#define REG_SFC_FSM jz_reg(SFC_FSM)
#define JA_SFC_FSM (0xb3440000 + 0x74)
#define JT_SFC_FSM JIO_32_RW
#define JN_SFC_FSM SFC_FSM
#define JI_SFC_FSM
#define BP_SFC_FSM_STATE_AHB 16
#define BM_SFC_FSM_STATE_AHB 0xf0000
#define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16)
#define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB
#define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e)
#define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB
#define BP_SFC_FSM_STATE_SPI 11
#define BM_SFC_FSM_STATE_SPI 0xf800
#define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11)
#define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI
#define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e)
#define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI
#define BP_SFC_FSM_STATE_CLK 6
#define BM_SFC_FSM_STATE_CLK 0x3c0
#define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6)
#define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK
#define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e)
#define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK
#define BP_SFC_FSM_STATE_DMAC 3
#define BM_SFC_FSM_STATE_DMAC 0x38
#define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3)
#define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC
#define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e)
#define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC
#define BP_SFC_FSM_STATE_RMC 0
#define BM_SFC_FSM_STATE_RMC 0x7
#define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0)
#define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC
#define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e)
#define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC
#define REG_SFC_CGE jz_reg(SFC_CGE)
#define JA_SFC_CGE (0xb3440000 + 0x78)
#define JT_SFC_CGE JIO_32_RW
#define JN_SFC_CGE SFC_CGE
#define JI_SFC_CGE
#define BP_SFC_CGE_SFC 5
#define BM_SFC_CGE_SFC 0x20
#define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5)
#define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC
#define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e)
#define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC
#define BP_SFC_CGE_FIFO 4
#define BM_SFC_CGE_FIFO 0x10
#define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4)
#define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO
#define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e)
#define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO
#define BP_SFC_CGE_DMA 3
#define BM_SFC_CGE_DMA 0x8
#define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3)
#define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA
#define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e)
#define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA
#define BP_SFC_CGE_RMC 2
#define BM_SFC_CGE_RMC 0x4
#define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2)
#define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC
#define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e)
#define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC
#define BP_SFC_CGE_SPI 1
#define BM_SFC_CGE_SPI 0x2
#define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1)
#define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI
#define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e)
#define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI
#define BP_SFC_CGE_REG 0
#define BM_SFC_CGE_REG 0x1
#define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0)
#define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG
#define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e)
#define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG
#define REG_SFC_DATA jz_reg(SFC_DATA)
#define JA_SFC_DATA (0xb3440000 + 0x1000)
#define JT_SFC_DATA JIO_32_RW
#define JN_SFC_DATA SFC_DATA
#define JI_SFC_DATA
#endif /* __HEADERGEN_SFC_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_TCU_H__
#define __HEADERGEN_TCU_H__
#include "macro.h"
#define REG_TCU_STATUS jz_reg(TCU_STATUS)
#define JA_TCU_STATUS (0xb0002000 + 0xf0)
#define JT_TCU_STATUS JIO_32_RW
#define JN_TCU_STATUS TCU_STATUS
#define JI_TCU_STATUS
#define REG_TCU_STATUS_SET jz_reg(TCU_STATUS_SET)
#define JA_TCU_STATUS_SET (JA_TCU_STATUS + 0x4)
#define JT_TCU_STATUS_SET JIO_32_WO
#define JN_TCU_STATUS_SET TCU_STATUS
#define JI_TCU_STATUS_SET
#define REG_TCU_STATUS_CLR jz_reg(TCU_STATUS_CLR)
#define JA_TCU_STATUS_CLR (JA_TCU_STATUS + 0x8)
#define JT_TCU_STATUS_CLR JIO_32_WO
#define JN_TCU_STATUS_CLR TCU_STATUS
#define JI_TCU_STATUS_CLR
#define REG_TCU_STOP jz_reg(TCU_STOP)
#define JA_TCU_STOP (0xb0002000 + 0x1c)
#define JT_TCU_STOP JIO_32_RW
#define JN_TCU_STOP TCU_STOP
#define JI_TCU_STOP
#define REG_TCU_STOP_SET jz_reg(TCU_STOP_SET)
#define JA_TCU_STOP_SET (JA_TCU_STOP + 0x10)
#define JT_TCU_STOP_SET JIO_32_WO
#define JN_TCU_STOP_SET TCU_STOP
#define JI_TCU_STOP_SET
#define REG_TCU_STOP_CLR jz_reg(TCU_STOP_CLR)
#define JA_TCU_STOP_CLR (JA_TCU_STOP + 0x20)
#define JT_TCU_STOP_CLR JIO_32_WO
#define JN_TCU_STOP_CLR TCU_STOP
#define JI_TCU_STOP_CLR
#define REG_TCU_ENABLE jz_reg(TCU_ENABLE)
#define JA_TCU_ENABLE (0xb0002000 + 0x10)
#define JT_TCU_ENABLE JIO_32_RW
#define JN_TCU_ENABLE TCU_ENABLE
#define JI_TCU_ENABLE
#define REG_TCU_ENABLE_SET jz_reg(TCU_ENABLE_SET)
#define JA_TCU_ENABLE_SET (JA_TCU_ENABLE + 0x4)
#define JT_TCU_ENABLE_SET JIO_32_WO
#define JN_TCU_ENABLE_SET TCU_ENABLE
#define JI_TCU_ENABLE_SET
#define REG_TCU_ENABLE_CLR jz_reg(TCU_ENABLE_CLR)
#define JA_TCU_ENABLE_CLR (JA_TCU_ENABLE + 0x8)
#define JT_TCU_ENABLE_CLR JIO_32_WO
#define JN_TCU_ENABLE_CLR TCU_ENABLE
#define JI_TCU_ENABLE_CLR
#define REG_TCU_FLAG jz_reg(TCU_FLAG)
#define JA_TCU_FLAG (0xb0002000 + 0x20)
#define JT_TCU_FLAG JIO_32_RW
#define JN_TCU_FLAG TCU_FLAG
#define JI_TCU_FLAG
#define REG_TCU_FLAG_SET jz_reg(TCU_FLAG_SET)
#define JA_TCU_FLAG_SET (JA_TCU_FLAG + 0x4)
#define JT_TCU_FLAG_SET JIO_32_WO
#define JN_TCU_FLAG_SET TCU_FLAG
#define JI_TCU_FLAG_SET
#define REG_TCU_FLAG_CLR jz_reg(TCU_FLAG_CLR)
#define JA_TCU_FLAG_CLR (JA_TCU_FLAG + 0x8)
#define JT_TCU_FLAG_CLR JIO_32_WO
#define JN_TCU_FLAG_CLR TCU_FLAG
#define JI_TCU_FLAG_CLR
#define REG_TCU_MASK jz_reg(TCU_MASK)
#define JA_TCU_MASK (0xb0002000 + 0x30)
#define JT_TCU_MASK JIO_32_RW
#define JN_TCU_MASK TCU_MASK
#define JI_TCU_MASK
#define REG_TCU_MASK_SET jz_reg(TCU_MASK_SET)
#define JA_TCU_MASK_SET (JA_TCU_MASK + 0x4)
#define JT_TCU_MASK_SET JIO_32_WO
#define JN_TCU_MASK_SET TCU_MASK
#define JI_TCU_MASK_SET
#define REG_TCU_MASK_CLR jz_reg(TCU_MASK_CLR)
#define JA_TCU_MASK_CLR (JA_TCU_MASK + 0x8)
#define JT_TCU_MASK_CLR JIO_32_WO
#define JN_TCU_MASK_CLR TCU_MASK
#define JI_TCU_MASK_CLR
#define REG_TCU_CMP_FULL(_n1) jz_reg(TCU_CMP_FULL(_n1))
#define JA_TCU_CMP_FULL(_n1) (0xb0002000 + 0x40 + (_n1) * 0x10)
#define JT_TCU_CMP_FULL(_n1) JIO_32_RW
#define JN_TCU_CMP_FULL(_n1) TCU_CMP_FULL
#define JI_TCU_CMP_FULL(_n1) (_n1)
#define REG_TCU_CMP_HALF(_n1) jz_reg(TCU_CMP_HALF(_n1))
#define JA_TCU_CMP_HALF(_n1) (0xb0002000 + 0x44 + (_n1) * 0x10)
#define JT_TCU_CMP_HALF(_n1) JIO_32_RW
#define JN_TCU_CMP_HALF(_n1) TCU_CMP_HALF
#define JI_TCU_CMP_HALF(_n1) (_n1)
#define REG_TCU_COUNT(_n1) jz_reg(TCU_COUNT(_n1))
#define JA_TCU_COUNT(_n1) (0xb0002000 + 0x48 + (_n1) * 0x10)
#define JT_TCU_COUNT(_n1) JIO_32_RW
#define JN_TCU_COUNT(_n1) TCU_COUNT
#define JI_TCU_COUNT(_n1) (_n1)
#define REG_TCU_CTRL(_n1) jz_reg(TCU_CTRL(_n1))
#define JA_TCU_CTRL(_n1) (0xb0002000 + 0x4c + (_n1) * 0x10)
#define JT_TCU_CTRL(_n1) JIO_32_RW
#define JN_TCU_CTRL(_n1) TCU_CTRL
#define JI_TCU_CTRL(_n1) (_n1)
#define BP_TCU_CTRL_PRESCALE 3
#define BM_TCU_CTRL_PRESCALE 0x38
#define BV_TCU_CTRL_PRESCALE__BY_1 0x0
#define BV_TCU_CTRL_PRESCALE__BY_4 0x1
#define BV_TCU_CTRL_PRESCALE__BY_16 0x2
#define BV_TCU_CTRL_PRESCALE__BY_64 0x3
#define BV_TCU_CTRL_PRESCALE__BY_256 0x4
#define BV_TCU_CTRL_PRESCALE__BY_1024 0x5
#define BF_TCU_CTRL_PRESCALE(v) (((v) & 0x7) << 3)
#define BFM_TCU_CTRL_PRESCALE(v) BM_TCU_CTRL_PRESCALE
#define BF_TCU_CTRL_PRESCALE_V(e) BF_TCU_CTRL_PRESCALE(BV_TCU_CTRL_PRESCALE__##e)
#define BFM_TCU_CTRL_PRESCALE_V(v) BM_TCU_CTRL_PRESCALE
#define BP_TCU_CTRL_SOURCE 0
#define BM_TCU_CTRL_SOURCE 0x7
#define BV_TCU_CTRL_SOURCE__EXT 0x4
#define BV_TCU_CTRL_SOURCE__RTC 0x2
#define BV_TCU_CTRL_SOURCE__PCLK 0x1
#define BF_TCU_CTRL_SOURCE(v) (((v) & 0x7) << 0)
#define BFM_TCU_CTRL_SOURCE(v) BM_TCU_CTRL_SOURCE
#define BF_TCU_CTRL_SOURCE_V(e) BF_TCU_CTRL_SOURCE(BV_TCU_CTRL_SOURCE__##e)
#define BFM_TCU_CTRL_SOURCE_V(v) BM_TCU_CTRL_SOURCE
#define BP_TCU_CTRL_BYPASS 11
#define BM_TCU_CTRL_BYPASS 0x800
#define BF_TCU_CTRL_BYPASS(v) (((v) & 0x1) << 11)
#define BFM_TCU_CTRL_BYPASS(v) BM_TCU_CTRL_BYPASS
#define BF_TCU_CTRL_BYPASS_V(e) BF_TCU_CTRL_BYPASS(BV_TCU_CTRL_BYPASS__##e)
#define BFM_TCU_CTRL_BYPASS_V(v) BM_TCU_CTRL_BYPASS
#define BP_TCU_CTRL_CLRZ 10
#define BM_TCU_CTRL_CLRZ 0x400
#define BF_TCU_CTRL_CLRZ(v) (((v) & 0x1) << 10)
#define BFM_TCU_CTRL_CLRZ(v) BM_TCU_CTRL_CLRZ
#define BF_TCU_CTRL_CLRZ_V(e) BF_TCU_CTRL_CLRZ(BV_TCU_CTRL_CLRZ__##e)
#define BFM_TCU_CTRL_CLRZ_V(v) BM_TCU_CTRL_CLRZ
#define BP_TCU_CTRL_SHUTDOWN 9
#define BM_TCU_CTRL_SHUTDOWN 0x200
#define BV_TCU_CTRL_SHUTDOWN__GRACEFUL 0x0
#define BV_TCU_CTRL_SHUTDOWN__ABRUPT 0x1
#define BF_TCU_CTRL_SHUTDOWN(v) (((v) & 0x1) << 9)
#define BFM_TCU_CTRL_SHUTDOWN(v) BM_TCU_CTRL_SHUTDOWN
#define BF_TCU_CTRL_SHUTDOWN_V(e) BF_TCU_CTRL_SHUTDOWN(BV_TCU_CTRL_SHUTDOWN__##e)
#define BFM_TCU_CTRL_SHUTDOWN_V(v) BM_TCU_CTRL_SHUTDOWN
#define BP_TCU_CTRL_INIT_LVL 8
#define BM_TCU_CTRL_INIT_LVL 0x100
#define BF_TCU_CTRL_INIT_LVL(v) (((v) & 0x1) << 8)
#define BFM_TCU_CTRL_INIT_LVL(v) BM_TCU_CTRL_INIT_LVL
#define BF_TCU_CTRL_INIT_LVL_V(e) BF_TCU_CTRL_INIT_LVL(BV_TCU_CTRL_INIT_LVL__##e)
#define BFM_TCU_CTRL_INIT_LVL_V(v) BM_TCU_CTRL_INIT_LVL
#define BP_TCU_CTRL_PWM_EN 7
#define BM_TCU_CTRL_PWM_EN 0x80
#define BF_TCU_CTRL_PWM_EN(v) (((v) & 0x1) << 7)
#define BFM_TCU_CTRL_PWM_EN(v) BM_TCU_CTRL_PWM_EN
#define BF_TCU_CTRL_PWM_EN_V(e) BF_TCU_CTRL_PWM_EN(BV_TCU_CTRL_PWM_EN__##e)
#define BFM_TCU_CTRL_PWM_EN_V(v) BM_TCU_CTRL_PWM_EN
#define BP_TCU_CTRL_PWM_IN_EN 6
#define BM_TCU_CTRL_PWM_IN_EN 0x40
#define BF_TCU_CTRL_PWM_IN_EN(v) (((v) & 0x1) << 6)
#define BFM_TCU_CTRL_PWM_IN_EN(v) BM_TCU_CTRL_PWM_IN_EN
#define BF_TCU_CTRL_PWM_IN_EN_V(e) BF_TCU_CTRL_PWM_IN_EN(BV_TCU_CTRL_PWM_IN_EN__##e)
#define BFM_TCU_CTRL_PWM_IN_EN_V(v) BM_TCU_CTRL_PWM_IN_EN
#endif /* __HEADERGEN_TCU_H__*/

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firmware/target/mips/ingenic_x1000/x1000/wdt.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* x1000 version: 1.0
* x1000 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_WDT_H__
#define __HEADERGEN_WDT_H__
#include "macro.h"
#define REG_WDT_DATA jz_reg(WDT_DATA)
#define JA_WDT_DATA (0xb0002000 + 0x0)
#define JT_WDT_DATA JIO_32_RW
#define JN_WDT_DATA WDT_DATA
#define JI_WDT_DATA
#define REG_WDT_ENABLE jz_reg(WDT_ENABLE)
#define JA_WDT_ENABLE (0xb0002000 + 0x4)
#define JT_WDT_ENABLE JIO_32_RW
#define JN_WDT_ENABLE WDT_ENABLE
#define JI_WDT_ENABLE
#define REG_WDT_COUNT jz_reg(WDT_COUNT)
#define JA_WDT_COUNT (0xb0002000 + 0x8)
#define JT_WDT_COUNT JIO_32_RW
#define JN_WDT_COUNT WDT_COUNT
#define JI_WDT_COUNT
#define REG_WDT_CTRL jz_reg(WDT_CTRL)
#define JA_WDT_CTRL (0xb0002000 + 0xc)
#define JT_WDT_CTRL JIO_32_RW
#define JN_WDT_CTRL WDT_CTRL
#define JI_WDT_CTRL
#define BP_WDT_CTRL_PRESCALE 3
#define BM_WDT_CTRL_PRESCALE 0x38
#define BV_WDT_CTRL_PRESCALE__BY_1 0x0
#define BV_WDT_CTRL_PRESCALE__BY_4 0x1
#define BV_WDT_CTRL_PRESCALE__BY_16 0x2
#define BV_WDT_CTRL_PRESCALE__BY_64 0x3
#define BV_WDT_CTRL_PRESCALE__BY_256 0x4
#define BV_WDT_CTRL_PRESCALE__BY_1024 0x5
#define BF_WDT_CTRL_PRESCALE(v) (((v) & 0x7) << 3)
#define BFM_WDT_CTRL_PRESCALE(v) BM_WDT_CTRL_PRESCALE
#define BF_WDT_CTRL_PRESCALE_V(e) BF_WDT_CTRL_PRESCALE(BV_WDT_CTRL_PRESCALE__##e)
#define BFM_WDT_CTRL_PRESCALE_V(v) BM_WDT_CTRL_PRESCALE
#define BP_WDT_CTRL_SOURCE 0
#define BM_WDT_CTRL_SOURCE 0x7
#define BV_WDT_CTRL_SOURCE__EXT 0x4
#define BV_WDT_CTRL_SOURCE__RTC 0x2
#define BV_WDT_CTRL_SOURCE__PLCK 0x1
#define BF_WDT_CTRL_SOURCE(v) (((v) & 0x7) << 0)
#define BFM_WDT_CTRL_SOURCE(v) BM_WDT_CTRL_SOURCE
#define BF_WDT_CTRL_SOURCE_V(e) BF_WDT_CTRL_SOURCE(BV_WDT_CTRL_SOURCE__##e)
#define BFM_WDT_CTRL_SOURCE_V(v) BM_WDT_CTRL_SOURCE
#endif /* __HEADERGEN_WDT_H__*/