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Fix S5L870x cache coherency functions. They were split into a different file, as changes were needed all over the place.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
4562e683a2
commit
3ac50ca9ff
5 changed files with 140 additions and 6 deletions
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@ -1281,8 +1281,8 @@ target/arm/tcc780x/cowond2/audio-cowond2.c
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#endif /* COWON_D2 */
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#ifdef CPU_S5L870X
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target/arm/mmu-arm.S
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target/arm/s5l8700/system-s5l8700.c
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target/arm/s5l8700/mmu-s5l8700.S
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#ifndef SIMULATOR
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#ifndef BOOTLOADER
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target/arm/s5l8700/timer-s5l8700.c
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@ -156,8 +156,6 @@ cpucache_invalidate:
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#else /* !IMX31L */
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/* S5L870X doesn't have a MMU */
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#ifndef CPU_S5L870X
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/** MMU setup **/
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/*
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@ -247,8 +245,6 @@ enable_mmu:
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.size enable_mmu, .-enable_mmu
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.ltorg
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#endif /* S5L870X */
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/** Cache coherency **/
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/*
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95
firmware/target/arm/s5l8700/mmu-s5l8700.S
Normal file
95
firmware/target/arm/s5l8700/mmu-s5l8700.S
Normal file
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@ -0,0 +1,95 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/** Cache coherency **/
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache
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.type clean_dcache, %function
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.global cpucache_flush @ Alias
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clean_dcache:
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cpucache_flush:
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@ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ
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mov r1, #0x00000000 @
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1: @ clean_start @
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mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index
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add r0, r1, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ clean_start @
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size clean_dcache, .-clean_dcache
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/*
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* Invalidate entire DCache
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* will do writeback
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* void invalidate_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache
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.type invalidate_dcache, %function
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invalidate_dcache:
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@ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ
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mov r1, #0x00000000 @
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1: @ inv_start @
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mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r1, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ inv_start @
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size invalidate_dcache, .-invalidate_dcache
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/*
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* Invalidate entire ICache and DCache
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* will do writeback
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* void invalidate_idcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_idcache
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.type invalidate_idcache, %function
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.global cpucache_invalidate @ Alias
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invalidate_idcache:
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cpucache_invalidate:
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mov r2, lr @ save lr to r2, call uses r0 and r1 only
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bl invalidate_dcache @ Clean and invalidate entire DCache
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mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call)
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mov pc, r2 @
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.size invalidate_idcache, .-invalidate_idcache
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43
firmware/target/arm/s5l8700/mmu-target.h
Normal file
43
firmware/target/arm/s5l8700/mmu-target.h
Normal file
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@ -0,0 +1,43 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* This file MUST be included in your system-target.h file if you want arm
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* cache coherence functions to be called (I.E. during codec load, etc).
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*/
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#ifndef MMU_S5L8700_H
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#define MMU_S5L8700_H
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/* Cleans entire DCache */
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void clean_dcache(void);
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/* Invalidate entire DCache */
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/* will do writeback */
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void invalidate_dcache(void);
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/* Invalidate entire ICache and DCache */
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/* will do writeback */
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void invalidate_idcache(void);
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#define HAVE_CPUCACHE_INVALIDATE
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#define HAVE_CPUCACHE_FLUSH
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#endif /* MMU_S5L8700_H */
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@ -22,7 +22,7 @@
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "mmu-arm.h"
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#include "mmu-target.h"
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#define CPUFREQ_DEFAULT 32000000
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#define CPUFREQ_NORMAL 48000000
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