diff --git a/firmware/SOURCES b/firmware/SOURCES index 2cb97a241b..3d9539d17d 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -1281,8 +1281,8 @@ target/arm/tcc780x/cowond2/audio-cowond2.c #endif /* COWON_D2 */ #ifdef CPU_S5L870X -target/arm/mmu-arm.S target/arm/s5l8700/system-s5l8700.c +target/arm/s5l8700/mmu-s5l8700.S #ifndef SIMULATOR #ifndef BOOTLOADER target/arm/s5l8700/timer-s5l8700.c diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S index ef595ac3d8..d83188b528 100644 --- a/firmware/target/arm/mmu-arm.S +++ b/firmware/target/arm/mmu-arm.S @@ -156,8 +156,6 @@ cpucache_invalidate: #else /* !IMX31L */ -/* S5L870X doesn't have a MMU */ -#ifndef CPU_S5L870X /** MMU setup **/ /* @@ -247,8 +245,6 @@ enable_mmu: .size enable_mmu, .-enable_mmu .ltorg -#endif /* S5L870X */ - /** Cache coherency **/ /* diff --git a/firmware/target/arm/s5l8700/mmu-s5l8700.S b/firmware/target/arm/s5l8700/mmu-s5l8700.S new file mode 100644 index 0000000000..d6098a8593 --- /dev/null +++ b/firmware/target/arm/s5l8700/mmu-s5l8700.S @@ -0,0 +1,95 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006,2007 by Greg White + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include "config.h" +#include "cpu.h" + +/** Cache coherency **/ + +/* + * Cleans entire DCache + * void clean_dcache(void); + */ + .section .text, "ax", %progbits + .align 2 + .global clean_dcache + .type clean_dcache, %function + .global cpucache_flush @ Alias +clean_dcache: +cpucache_flush: + @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ + mov r1, #0x00000000 @ +1: @ clean_start @ + mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index + add r0, r1, #0x00000010 @ + mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index + add r0, r0, #0x00000010 @ + mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index + add r0, r0, #0x00000010 @ + mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index + adds r1, r1, #0x04000000 @ will wrap to zero at loop end + bne 1b @ clean_start @ + mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer + bx lr @ + .size clean_dcache, .-clean_dcache + +/* + * Invalidate entire DCache + * will do writeback + * void invalidate_dcache(void); + */ + .section .text, "ax", %progbits + .align 2 + .global invalidate_dcache + .type invalidate_dcache, %function +invalidate_dcache: + @ Index format: 31:26 = index, 7:5 = segment, remainder = SBZ + mov r1, #0x00000000 @ +1: @ inv_start @ + mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index + add r0, r1, #0x00000010 @ + mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index + add r0, r0, #0x00000010 @ + mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index + add r0, r0, #0x00000010 @ + mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index + adds r1, r1, #0x04000000 @ will wrap to zero at loop end + bne 1b @ inv_start @ + mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer + bx lr @ + .size invalidate_dcache, .-invalidate_dcache + +/* + * Invalidate entire ICache and DCache + * will do writeback + * void invalidate_idcache(void); + */ + .section .text, "ax", %progbits + .align 2 + .global invalidate_idcache + .type invalidate_idcache, %function + .global cpucache_invalidate @ Alias +invalidate_idcache: +cpucache_invalidate: + mov r2, lr @ save lr to r2, call uses r0 and r1 only + bl invalidate_dcache @ Clean and invalidate entire DCache + mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) + mov pc, r2 @ + .size invalidate_idcache, .-invalidate_idcache diff --git a/firmware/target/arm/s5l8700/mmu-target.h b/firmware/target/arm/s5l8700/mmu-target.h new file mode 100644 index 0000000000..b0baa90037 --- /dev/null +++ b/firmware/target/arm/s5l8700/mmu-target.h @@ -0,0 +1,43 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006,2007 by Greg White + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* This file MUST be included in your system-target.h file if you want arm + * cache coherence functions to be called (I.E. during codec load, etc). + */ + +#ifndef MMU_S5L8700_H +#define MMU_S5L8700_H + +/* Cleans entire DCache */ +void clean_dcache(void); + +/* Invalidate entire DCache */ +/* will do writeback */ +void invalidate_dcache(void); + +/* Invalidate entire ICache and DCache */ +/* will do writeback */ +void invalidate_idcache(void); + +#define HAVE_CPUCACHE_INVALIDATE +#define HAVE_CPUCACHE_FLUSH + +#endif /* MMU_S5L8700_H */ diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 6d4b69135d..8f10301563 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h @@ -22,7 +22,7 @@ #define SYSTEM_TARGET_H #include "system-arm.h" -#include "mmu-arm.h" +#include "mmu-target.h" #define CPUFREQ_DEFAULT 32000000 #define CPUFREQ_NORMAL 48000000