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Enable UC870x "auto baud" and "fine tune" features based on the SoC capabilities
This makes it easier to add support for the remaining SoCs of the S5L87xx series. Change-Id: I563aa55eed385b5f8e1c52edb866b08176ea116e
This commit is contained in:
Vencislav Atanasov
Solomon Peachy
parent
1c7fddad5b
commit
39f8101d60
2 changed files with 79 additions and 63 deletions
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@ -33,9 +33,16 @@
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* UC870x: UART controller for s5l870x
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*
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* This UART is similar to the UART described in s5l8700 datasheet,
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* (see also s3c2416 and s3c6400 datasheets). On s5l8701/2 the UC870x
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* includes autobauding, and fine tunning for Tx/Rx on s5l8702.
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* (see also s3c2416 and s3c6400 datasheets). On s5l8701+ the UC870x
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* includes autobauding, and fine tuning for Tx/Rx speed on s5l8702+.
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*/
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#if (CONFIG_CPU == S5L8701)
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#define UART_CAP_AUTOBAUD
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#elif (CONFIG_CPU == S5L8702) || (CONFIG_CPU == S5L8720)
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#define UART_CAP_AUTOBAUD
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#define UART_CAP_FINETUNE
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#endif
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/*
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* Controller registers
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@ -53,11 +60,13 @@
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#define UTXH(ba) (*((REG32_PTR_T)((ba) + 0x20))) /* transmission hold */
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#define URXH(ba) (*((REG32_PTR_T)((ba) + 0x24))) /* receive buffer */
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#define UBRDIV(ba) (*((REG32_PTR_T)((ba) + 0x28))) /* baud rate divisor */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UABRCNT(ba) (*((REG32_PTR_T)((ba) + 0x2c))) /* autobaud counter */
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#define UABRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x30))) /* autobaud status */
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#endif
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UBRCONTX(ba) (*((REG32_PTR_T)((ba) + 0x34))) /* Tx frame config */
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#define UBRCONRX(ba) (*((REG32_PTR_T)((ba) + 0x38))) /* Rx frame config */
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#endif
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@ -106,19 +115,20 @@
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#define UCON_CLKSEL_PCLK 0 /* internal */
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#define UCON_CLKSEL_ECLK 1 /* external */
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UCON_RX_TOUT_INT_BIT (1 << 11) /* Rx timeout INT enable */
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#endif
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#define UCON_RX_INT_BIT (1 << 12) /* Rx INT enable */
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#define UCON_TX_INT_BIT (1 << 13) /* Tx INT enable */
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#define UCON_ERR_INT_BIT (1 << 14) /* Rx error INT enable */
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#define UCON_MODEM_INT_BIT (1 << 15) /* modem INT enable (TBC) */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UCON_AUTOBR_INT_BIT (1 << 16) /* autobauding INT enable */
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#define UCON_AUTOBR_START_BIT (1 << 17) /* autobauding start/stop */
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#endif
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#if CONFIG_CPU == S5L8701
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#if (CONFIG_CPU == S5L8701)
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/* WTF! ABR bits are swapped on reads, so don't forget to
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always use this workaround to read the UCON register. */
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static inline uint32_t _UCON_RD(uint32_t ba)
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@ -130,7 +140,8 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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}
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#else
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#define _UCON_RD(ba) UCON(ba)
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#endif
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#endif /* (CONFIG_CPU == S5L8701) */
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#endif /* UART_CAP_AUTOBAUD */
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/* UFCON register */
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#define UFCON_FIFO_ENABLE_BIT (1 << 0)
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@ -159,14 +170,17 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UTRSTAT_RXBUF_RDY_BIT (1 << 0)
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#define UTRSTAT_TXBUF_EMPTY_BIT (1 << 1)
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#define UTRSTAT_TX_EMPTY_BIT (1 << 2)
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UTRSTAT_RX_TOUT_INT_BIT (1 << 3) /* Rx timeout INT status */
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#endif
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#define UTRSTAT_RX_INT_BIT (1 << 4)
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#define UTRSTAT_TX_INT_BIT (1 << 5)
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#define UTRSTAT_ERR_INT_BIT (1 << 6)
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#define UTRSTAT_MODEM_INT_BIT (1 << 7) /* modem INT status */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UTRSTAT_AUTOBR_INT_BIT (1 << 8) /* autobauding INT status */
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#endif
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@ -192,7 +206,7 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UMSTAT_CTS_DELTA_BIT (1 << 4)
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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/* Bitrate:
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*
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* Master UCLK clock is divided by 16 to serialize data, UBRDIV is
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@ -215,10 +229,10 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UBRCON_JITTER_INC 1 /* increment 1/16 bit width */
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#define UBRCON_JITTER_UNUSED 2 /* does nothing */
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#define UBRCON_JITTER_DEC 3 /* decremet 1/16 bit width */
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#endif /* CONFIG_CPU == S5L8702 */
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#endif /* UART_CAP_FINETUNE */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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/* Autobauding:
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*
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* Initial UABRSTAT is NOT_INIT, it goes to READY when either of
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@ -249,7 +263,7 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UABRSTAT_STATUS_NOT_INIT 0 /* initial status */
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#define UABRSTAT_STATUS_READY 1 /* machine is ready */
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#define UABRSTAT_STATUS_COUNTING 2 /* count in progress */
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#endif /* CONFIG_CPU != S5L8700 */
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#endif /* UART_CAP_AUTOBAUD */
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/*
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@ -281,7 +295,7 @@ struct uartc_port
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const uint8_t clksel; /* UFCON_CLKSEL_xxx */
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const uint32_t clkhz; /* UCLK (PCLK or ECLK) frequency */
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void (* const tx_cb) (int len); /* ISRs */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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void (* const rx_cb) (int len, char *data, char *err, uint32_t abr_cnt);
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#else
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void (* const rx_cb) (int len, char *data, char *err);
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@ -292,7 +306,7 @@ struct uartc_port
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uint32_t utrstat_int_mask;
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uint8_t rx_data[UART_FIFO_SIZE]; /* data buffer for rx_cb */
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uint8_t rx_err[UART_FIFO_SIZE]; /* error buffer for rx_cb */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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bool abr_aborted;
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#endif
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@ -303,12 +317,11 @@ struct uartc_port
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uint32_t n_parity_err;
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uint32_t n_frame_err;
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uint32_t n_break_detect;
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#if CONFIG_CPU != S5L8700
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/* autobauding */
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#ifdef UART_CAP_AUTOBAUD
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uint32_t n_abnormal0;
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uint32_t n_abnormal1;
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#endif
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#endif
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#endif /* UART_CAP_AUTOBAUD */
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#endif /* UC870X_DEBUG */
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};
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@ -342,7 +355,7 @@ bool uartc_port_rx_ready(struct uartc_port *port);
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uint8_t uartc_port_rx_byte(struct uartc_port *port);
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uint8_t uartc_port_read_byte(struct uartc_port *port);
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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/* Autobauding */
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void uartc_port_abr_start(struct uartc_port *port);
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void uartc_port_abr_stop(struct uartc_port *port);
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@ -357,7 +370,7 @@ void uartc_port_get_line_info(struct uartc_port *port,
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int *tx_status, int *rx_status,
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int *tx_speed, int *rx_speed, char *line_cfg);
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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enum {
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ABR_INFO_ST_IDLE,
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ABR_INFO_ST_LAUNCHED,
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@ -366,7 +379,7 @@ enum {
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};
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int uartc_port_get_abr_info(struct uartc_port *port, uint32_t *abr_cnt);
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#endif
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#endif /* UART_CAP_AUTOBAUD */
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#endif /* UC870X_DEBUG */
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#endif /* __UC870X_H__ */
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@ -32,26 +32,29 @@
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* UC870x: UART controller for s5l870x
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*/
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/* Rx related masks */
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#if CONFIG_CPU == S5L8700
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#define UTRSTAT_RX_RELATED_INTS (UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT)
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#define UCON_RX_RELATED_INTS (UCON_RX_INT_BIT | UCON_ERR_INT_BIT)
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#elif CONFIG_CPU == S5L8701
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#define UTRSTAT_RX_RELATED_INTS \
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(UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT | UTRSTAT_AUTOBR_INT_BIT)
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#define UCON_RX_RELATED_INTS \
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(UCON_RX_INT_BIT | UCON_ERR_INT_BIT | UCON_AUTOBR_INT_BIT)
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#else /* CONFIG_CPU == S5L8702 */
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#define UTRSTAT_RX_RELATED_INTS \
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(UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT | \
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UTRSTAT_AUTOBR_INT_BIT | UTRSTAT_RX_TOUT_INT_BIT)
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#define UCON_RX_RELATED_INTS \
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(UCON_RX_INT_BIT | UCON_ERR_INT_BIT | \
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UCON_AUTOBR_INT_BIT | UCON_RX_TOUT_INT_BIT)
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/* Rx related INTs */
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#ifdef UART_CAP_AUTOBAUD
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#define AUTOBAUD_UTRSTAT_INT UTRSTAT_AUTOBR_INT_BIT
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#define AUTOBAUD_UCON_INT UCON_AUTOBR_INT_BIT
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#else
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#define AUTOBAUD_UTRSTAT_INT 0
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#define AUTOBAUD_UCON_INT 0
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#endif
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#ifdef UART_CAP_FINETUNE
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#define FINETUNE_UTRSTAT_INT UTRSTAT_RX_TOUT_INT_BIT
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#define FINETUNE_UCON_INT UCON_RX_TOUT_INT_BIT
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#else
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#define FINETUNE_UTRSTAT_INT 0
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#define FINETUNE_UCON_INT 0
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#endif
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#define UTRSTAT_RX_INTS (UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT | \
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AUTOBAUD_UTRSTAT_INT | FINETUNE_UTRSTAT_INT)
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#define UCON_RX_INTS (UCON_RX_INT_BIT | UCON_ERR_INT_BIT | \
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AUTOBAUD_UCON_INT | FINETUNE_UCON_INT)
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#define UART_PORT_BASE(u,i) (((u)->baddr) + (u)->port_off * (i))
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/* Initialization */
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@ -68,7 +71,7 @@ static void uartc_reset_port_id(const struct uartc* uartc, int port_id)
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UFCON(baddr) = UFCON_RX_FIFO_RST_BIT | UFCON_TX_FIFO_RST_BIT;
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UTRSTAT(baddr) = ~0; /* clear all interrupts */
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UBRDIV(baddr) = 0;
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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UBRCONTX(baddr) = 0;
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UBRCONRX(baddr) = 0;
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#endif
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@ -119,14 +122,14 @@ void uartc_port_open(struct uartc_port *port)
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UCON(baddr) = (UCON_MODE_DISABLED << UCON_RX_MODE_POS)
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| (UCON_MODE_DISABLED << UCON_TX_MODE_POS)
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| ((port->clksel & UCON_CLKSEL_MASK) << UCON_CLKSEL_POS)
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| (port->rx_cb ? UCON_RX_RELATED_INTS|UCON_RX_TOUT_EN_BIT : 0)
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| (port->rx_cb ? UCON_RX_INTS|UCON_RX_TOUT_EN_BIT : 0)
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| (port->tx_cb ? UCON_TX_INT_BIT : 0);
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/* init and register port struct */
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port->baddr = baddr;
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port->utrstat_int_mask = (port->rx_cb ? UTRSTAT_RX_RELATED_INTS : 0)
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port->utrstat_int_mask = (port->rx_cb ? UTRSTAT_RX_INTS : 0)
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| (port->tx_cb ? UTRSTAT_TX_INT_BIT : 0);
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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port->abr_aborted = 0;
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#endif
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uartc->port_l[port->id] = port;
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@ -156,7 +159,7 @@ void uartc_port_set_bitrate_raw(struct uartc_port *port, uint32_t brdata)
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{
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uint32_t baddr = port->baddr;
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UBRDIV(baddr) = brdata & 0xff;
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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UBRCONRX(baddr) = brdata >> 8;
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UBRCONTX(baddr) = brdata >> 8;
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#endif
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@ -174,7 +177,7 @@ void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed)
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uint32_t brdata = brdiv - 1;
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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/* Fine adjust:
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*
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* Along the whole frame, insert/remove "jittered" bauds when needed
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@ -210,7 +213,7 @@ void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed)
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}
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brdata |= (brcon << 8);
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#endif /* CONFIG_CPU == S5L8702 */
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#endif /* UART_CAP_FINETUNE */
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uartc_port_set_rawbr(port, brdata);
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}
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@ -269,7 +272,7 @@ uint8_t uartc_port_read_byte(struct uartc_port *port)
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return uartc_port_rx_byte(port);
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}
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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/* Autobauding */
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static inline int uartc_port_abr_status(struct uartc_port *port)
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{
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@ -300,7 +303,7 @@ void uartc_port_abr_stop(struct uartc_port *port)
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else
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UCON(port->baddr) = _UCON_RD(port->baddr) & ~UCON_AUTOBR_START_BIT;
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}
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#endif /* CONFIG_CPU != S5L8700 */
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#endif /* UART_CAP_AUTOBAUD */
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/* ISR */
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void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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@ -315,10 +318,10 @@ void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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this ISR will be processed in the next call */
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UTRSTAT(baddr) = ints;
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if (ints & UTRSTAT_RX_RELATED_INTS)
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if (ints & UTRSTAT_RX_INTS)
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{
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int len = 0;
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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uint32_t abr_cnt = 0;
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if (ints & UTRSTAT_AUTOBR_INT_BIT)
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@ -335,8 +338,8 @@ void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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abr_cnt = UABRCNT(baddr);
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}
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if (ints & (UTRSTAT_RX_RELATED_INTS ^ UTRSTAT_AUTOBR_INT_BIT))
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#endif /* CONFIG_CPU != S5L8700 */
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if (ints & (UTRSTAT_RX_INTS ^ UTRSTAT_AUTOBR_INT_BIT))
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#endif /* UART_CAP_AUTOBAUD */
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{
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/* get FIFO count */
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uint32_t ufstat = UFSTAT(baddr);
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@ -355,11 +358,11 @@ void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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* When overrun, it is marked on the first error:
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* overrun = len ? (rx_err[0] & UERSTAT_OVERRUN_BIT) : 0
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*/
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#if CONFIG_CPU == S5L8700
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port->rx_cb(len, port->rx_data, port->rx_err);
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#else
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#ifdef UART_CAP_AUTOBAUD
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/* 'abr_cnt' is zero when no ABR interrupt exists */
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port->rx_cb(len, port->rx_data, port->rx_err, abr_cnt);
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#else
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port->rx_cb(len, port->rx_data, port->rx_err);
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#endif
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#ifdef UC870X_DEBUG
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@ -394,7 +397,7 @@ void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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static int get_bitrate(int uclk, int brdiv, int brcon, int frame_len)
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{
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logf("get_bitrate(%d, %d, 0x%08x, %d)", uclk, brdiv, brcon, frame_len);
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@ -426,7 +429,7 @@ static int get_bitrate(int uclk, int brdiv, int brcon, int frame_len)
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return avg_speed;
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}
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#endif /* CONFIG_CPU == S5L8702 */
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#endif /* UART_CAP_FINETUNE */
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void uartc_port_get_line_info(struct uartc_port *port,
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int *tx_status, int *rx_status,
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@ -446,7 +449,7 @@ void uartc_port_get_line_info(struct uartc_port *port,
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int parity = (ulcon >> ULCON_PARITY_POS) & ULCON_PARITY_MASK;
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uint32_t brdiv = UBRDIV(baddr) + 1;
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
|
||||
int frame_len = 1 + n_data + (parity ? 1 : 0) + n_stop;
|
||||
if (tx_speed)
|
||||
*tx_speed = get_bitrate(port->clkhz, brdiv, UBRCONTX(baddr), frame_len);
|
||||
|
|
@ -471,7 +474,7 @@ void uartc_port_get_line_info(struct uartc_port *port,
|
|||
}
|
||||
}
|
||||
|
||||
#if CONFIG_CPU != S5L8700
|
||||
#ifdef UART_CAP_AUTOBAUD
|
||||
/* Autobauding */
|
||||
int uartc_port_get_abr_info(struct uartc_port *port, uint32_t *abr_cnt)
|
||||
{
|
||||
|
|
@ -502,5 +505,5 @@ int uartc_port_get_abr_info(struct uartc_port *port, uint32_t *abr_cnt)
|
|||
|
||||
return status;
|
||||
}
|
||||
#endif /* CONFIG_CPU != S5L8700 */
|
||||
#endif /* UART_CAP_AUTOBAUD */
|
||||
#endif /* UC870X_DEBUG */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue