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Enable UC870x "auto baud" and "fine tune" features based on the SoC capabilities
This makes it easier to add support for the remaining SoCs of the S5L87xx series. Change-Id: I563aa55eed385b5f8e1c52edb866b08176ea116e
This commit is contained in:
Vencislav Atanasov
Solomon Peachy
parent
1c7fddad5b
commit
39f8101d60
2 changed files with 79 additions and 63 deletions
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@ -33,9 +33,16 @@
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* UC870x: UART controller for s5l870x
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*
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* This UART is similar to the UART described in s5l8700 datasheet,
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* (see also s3c2416 and s3c6400 datasheets). On s5l8701/2 the UC870x
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* includes autobauding, and fine tunning for Tx/Rx on s5l8702.
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* (see also s3c2416 and s3c6400 datasheets). On s5l8701+ the UC870x
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* includes autobauding, and fine tuning for Tx/Rx speed on s5l8702+.
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*/
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#if (CONFIG_CPU == S5L8701)
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#define UART_CAP_AUTOBAUD
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#elif (CONFIG_CPU == S5L8702) || (CONFIG_CPU == S5L8720)
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#define UART_CAP_AUTOBAUD
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#define UART_CAP_FINETUNE
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#endif
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/*
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* Controller registers
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@ -53,11 +60,13 @@
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#define UTXH(ba) (*((REG32_PTR_T)((ba) + 0x20))) /* transmission hold */
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#define URXH(ba) (*((REG32_PTR_T)((ba) + 0x24))) /* receive buffer */
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#define UBRDIV(ba) (*((REG32_PTR_T)((ba) + 0x28))) /* baud rate divisor */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UABRCNT(ba) (*((REG32_PTR_T)((ba) + 0x2c))) /* autobaud counter */
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#define UABRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x30))) /* autobaud status */
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#endif
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UBRCONTX(ba) (*((REG32_PTR_T)((ba) + 0x34))) /* Tx frame config */
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#define UBRCONRX(ba) (*((REG32_PTR_T)((ba) + 0x38))) /* Rx frame config */
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#endif
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@ -106,19 +115,20 @@
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#define UCON_CLKSEL_PCLK 0 /* internal */
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#define UCON_CLKSEL_ECLK 1 /* external */
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UCON_RX_TOUT_INT_BIT (1 << 11) /* Rx timeout INT enable */
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#endif
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#define UCON_RX_INT_BIT (1 << 12) /* Rx INT enable */
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#define UCON_TX_INT_BIT (1 << 13) /* Tx INT enable */
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#define UCON_ERR_INT_BIT (1 << 14) /* Rx error INT enable */
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#define UCON_MODEM_INT_BIT (1 << 15) /* modem INT enable (TBC) */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UCON_AUTOBR_INT_BIT (1 << 16) /* autobauding INT enable */
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#define UCON_AUTOBR_START_BIT (1 << 17) /* autobauding start/stop */
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#endif
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#if CONFIG_CPU == S5L8701
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#if (CONFIG_CPU == S5L8701)
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/* WTF! ABR bits are swapped on reads, so don't forget to
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always use this workaround to read the UCON register. */
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static inline uint32_t _UCON_RD(uint32_t ba)
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@ -130,7 +140,8 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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}
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#else
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#define _UCON_RD(ba) UCON(ba)
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#endif
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#endif /* (CONFIG_CPU == S5L8701) */
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#endif /* UART_CAP_AUTOBAUD */
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/* UFCON register */
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#define UFCON_FIFO_ENABLE_BIT (1 << 0)
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@ -159,14 +170,17 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UTRSTAT_RXBUF_RDY_BIT (1 << 0)
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#define UTRSTAT_TXBUF_EMPTY_BIT (1 << 1)
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#define UTRSTAT_TX_EMPTY_BIT (1 << 2)
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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#define UTRSTAT_RX_TOUT_INT_BIT (1 << 3) /* Rx timeout INT status */
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#endif
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#define UTRSTAT_RX_INT_BIT (1 << 4)
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#define UTRSTAT_TX_INT_BIT (1 << 5)
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#define UTRSTAT_ERR_INT_BIT (1 << 6)
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#define UTRSTAT_MODEM_INT_BIT (1 << 7) /* modem INT status */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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#define UTRSTAT_AUTOBR_INT_BIT (1 << 8) /* autobauding INT status */
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#endif
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@ -192,7 +206,7 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UMSTAT_CTS_DELTA_BIT (1 << 4)
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#if CONFIG_CPU == S5L8702
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#ifdef UART_CAP_FINETUNE
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/* Bitrate:
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*
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* Master UCLK clock is divided by 16 to serialize data, UBRDIV is
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@ -215,10 +229,10 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UBRCON_JITTER_INC 1 /* increment 1/16 bit width */
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#define UBRCON_JITTER_UNUSED 2 /* does nothing */
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#define UBRCON_JITTER_DEC 3 /* decremet 1/16 bit width */
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#endif /* CONFIG_CPU == S5L8702 */
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#endif /* UART_CAP_FINETUNE */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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/* Autobauding:
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*
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* Initial UABRSTAT is NOT_INIT, it goes to READY when either of
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@ -249,7 +263,7 @@ static inline uint32_t _UCON_RD(uint32_t ba)
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#define UABRSTAT_STATUS_NOT_INIT 0 /* initial status */
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#define UABRSTAT_STATUS_READY 1 /* machine is ready */
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#define UABRSTAT_STATUS_COUNTING 2 /* count in progress */
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#endif /* CONFIG_CPU != S5L8700 */
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#endif /* UART_CAP_AUTOBAUD */
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/*
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@ -281,7 +295,7 @@ struct uartc_port
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const uint8_t clksel; /* UFCON_CLKSEL_xxx */
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const uint32_t clkhz; /* UCLK (PCLK or ECLK) frequency */
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void (* const tx_cb) (int len); /* ISRs */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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void (* const rx_cb) (int len, char *data, char *err, uint32_t abr_cnt);
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#else
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void (* const rx_cb) (int len, char *data, char *err);
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@ -292,7 +306,7 @@ struct uartc_port
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uint32_t utrstat_int_mask;
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uint8_t rx_data[UART_FIFO_SIZE]; /* data buffer for rx_cb */
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uint8_t rx_err[UART_FIFO_SIZE]; /* error buffer for rx_cb */
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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bool abr_aborted;
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#endif
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@ -303,12 +317,11 @@ struct uartc_port
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uint32_t n_parity_err;
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uint32_t n_frame_err;
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uint32_t n_break_detect;
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#if CONFIG_CPU != S5L8700
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/* autobauding */
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#ifdef UART_CAP_AUTOBAUD
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uint32_t n_abnormal0;
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uint32_t n_abnormal1;
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#endif
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#endif
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#endif /* UART_CAP_AUTOBAUD */
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#endif /* UC870X_DEBUG */
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};
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@ -342,7 +355,7 @@ bool uartc_port_rx_ready(struct uartc_port *port);
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uint8_t uartc_port_rx_byte(struct uartc_port *port);
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uint8_t uartc_port_read_byte(struct uartc_port *port);
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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/* Autobauding */
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void uartc_port_abr_start(struct uartc_port *port);
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void uartc_port_abr_stop(struct uartc_port *port);
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@ -357,7 +370,7 @@ void uartc_port_get_line_info(struct uartc_port *port,
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int *tx_status, int *rx_status,
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int *tx_speed, int *rx_speed, char *line_cfg);
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#if CONFIG_CPU != S5L8700
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#ifdef UART_CAP_AUTOBAUD
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enum {
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ABR_INFO_ST_IDLE,
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ABR_INFO_ST_LAUNCHED,
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@ -366,7 +379,7 @@ enum {
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};
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int uartc_port_get_abr_info(struct uartc_port *port, uint32_t *abr_cnt);
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#endif
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#endif /* UART_CAP_AUTOBAUD */
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#endif /* UC870X_DEBUG */
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#endif /* __UC870X_H__ */
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